Subject: RE: BIRD 68.1

From: "Lorang, David D" <[email-masked]>
Date: Wed, 13 Jun 2001 14:40:51 -0700

Adam,

You wrote:
>David,  The netlists we use in S2I translation include only the buffers (
>we are currently considering using netlists that include full data paths
>instead ) and so my question is, should additional delay be added to the
>rising and falling waveforms to account for the delay through circuitry not
>included in these netlists?

Possibly, but not necessarily.  It depends on how well you want to model the
duty cycle distortion in your actual design.  You can choose to simulate a
certain signal all the way from the input pins of your IC, depending on what
internal timing differences for that signal that you want to capture.  

In general, IBIS tries to specify only the edges, but not their timings.
But in the case of an individual signal, if you are conserned about--and
want to model--duty cycle distortion, you need to maintain some timing
information.  That timing information can be carried in the assumption the
start of each edge table as a common point of reference.  So the number of
nanoseconds into the tables where the rising and falling edges occur
relative to each other should match up with where the edges occur relative
to each other in the silicon (or the transistor level simulation of the
silicon if that is what you are correlating to.)  

Dave Lorang