Subject: EIA IBIS European IBIS Summit Meeting Minutes

From: [email-masked] (Guy de Burgh)
Date: Thu, 22 Mar 2001 18:28:01 -0800

Date: 3/22/01

SUBJECT: 3/16/01 EIA IBIS European IBIS Summit Meeting Minutes

VOTING MEMBERS AND 2001 PARTICIPANTS LIST:
3Com (& CommWorks)             Roy Leventhal
Agilent                        (Mark Chang)
Ansoft Corporation             (Eric Bracken)
Apple Computer                 John Figueroa
Applied Simulation Technology  Raj Raghuram, Norio Matsui, Fred Balistreri
Avanti                         (Chen Hongyu)
Brocade Communications         Robert Badal
Cadence Design                 Ian Dodd, Patrick Dos Santos*, Heiko Dudek*
Cisco Systems                  Syed Huq, Lungfu Chen
Compaq                         Peter LaFlamme, Ron Bellomio, Quang Dam
Cypress                        (Rajesh Manapat)
EMC Corporation                Brian Arsenault, Jinhua Chen
Fairchild Semiconductor        Adam Tambone
IBM                            Michael Cohen, Greg Edlund, Wes Martin,
                               Yeon-Chang Hahm, Bill DeVey, Pravin Patel
Innoveda (& HyperLynx)         Guy de Burgh, John Angulo, Cary Mandel*
Intel Corporation              Stephen Peters, Arpad Muranyi*, Dave Lorang,
                               Michael Mirmak, Qinglun Chen, Will Hobbs
LSI Logic                      Larry Barnes
Mentor Graphics                Bob Ross*, Tom Dagostino*, Chris Reid,
                               Mike Donnelly, Hazem Hegazy, Tony Dunbar,
                               Griff Derryberry, Dan Lake, Sherif Hammad*,
                               Mohammed Korany*, Weston Beal, Chris Swaim*,
                               Ali Samii*, Eric Ronger*, Karine Loudet*
Micron Technology              Randy Wolff, Yong Phan
Mitsubishi                     (Tam (Tom) Cao)
Molex Incorporated             Gus Panella, Brian O'Malley
Motorola                       (Ron Werner)
National Semiconductor         Milt Schwartz
Nortel Networks                Calvin Trowell
North East Systems Associates  Edward Sayre
Philips Semiconductor          Zack Ciccone, Rob Mataheroe*
Quantic EMC                    (Mike Ventham)
Robinson-Nugent, Inc.          (Alexander Barr)
Siemens (& Automotive) AG      Bernhard Unger*, Helmut Katzier, Katja Koller*, 
                               Wolfram Meyer*, Eckhard Lenski*,
                               Gerald Bannert*, Burkhard Muller*, 
                               Christian Marot*, Manfred Maurer*,
                               Amir Motamedi*, Hans Pichlmaier*
Signal Integrity Software      Douglas Burns, Barry Katz, Walter Katz
SiQual                         Scott McMorrow, Rob Hinz, Bernard Voss,
                               Chris Brewster
Texas Instruments              Thomas Fisher, Stephen Nolan, Ramzi Ammar,
                               Jean Claude Perrin*
Time Domain Analysis Systems   Dima Smolyansky, Steve Corey
Tyco Electronics               (Russell Moser)
Via Technologies               (Weber Chuang)
Zuken (& Incases)              John Berrie*

OTHER PARTICIPANTS IN 2001:
Actel Corporation              Silvia Montoya
Acuson                         Kim Helliwell
AMCC                           Jeff Smith
ASIS Ltd                       David Wright
BMW                            Friedrich Hasinger*
Cereva Networks                Bob Haller
EADS Airbus Industry           Claude Huet*
  (Aerospatiale)
EFM                            Ekkehard Miersch*, Horle Raines*
EIA                            Cecilia Fleming
FCI                            Sercu Stefaan
Foundary Networks              Bertram Chan
Framatom Conectors             Danny Morlion
Fraunhofer Institute           Mariusz Faferko*, Peter Kralicek*
  Reliability and
  Integration
Fujitsu Ltd                    Tadashi Arai, Takeshi Murakami
Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt*
Huawei Technologies            Rachild Chen
Hyundai Electronics            Jongho Kang
Infineon Technologies          Christian Sporrer*
Intrinsix Corporation          Steven Chin
National Institute of Applied  Etienne Sicard*
  Science (INSA)
Nokia                          Tapani von Ravner, Mika Castren*,
                               Janne Uusitalo*
Oak Technology                 Darmin Jin
Plexus Technology Group        Joseph Socha
Sintecs                        Hans Klos*
STMicroelectronics             Peter Hirt, Fabrice Boissieres*
Sun                            Adrian Udenze*
Xilinx                         Susan Wu
Independent, Consultant        Al Davis

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
follows:

  Date                Bridge Number    Reservation #    Passcode
  March 30, 2001       (916) 356-9200   2-524673         6244264
  April 20, 2001       (916) 356-9200   2-524674         3881934

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out
7 days before each Open Forum and meeting minutes out within 7 days after.
When you call into the meeting, ask for the IBIS Open Forum hosted by Will
Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------
INTRODUCTIONS AND MEETING QUORUM
The European IBIS Summit Meeting held all day at the Astron Hotel/Neue Messe, 
Munich Germany.  About 39 people from 19 companies and institutes attended.
The notes below capture some of the meeting content and discussions.  The
meeting presentations and other material will be uploaded at: 

  http://www.eda.org/pub/ibis/summits/mar01/

Bob Ross opened the meeting by having everyone introduce themselves.  The EDA,
user and semiconductor were well represented.  Bob thanked the co-sponsors for 
the meeting, Cadence, Innoveda, Mentor Graphics, and Zuken for sharing the 
meeting expenses.  Bob also thanked Karine Loudet of Mentor Graphics for 
helping in the meeting logistics, collecting registrations, copying 
presentations, creating badges, and producing the beautiful European IBIS 
Summit Meeting poster.

As a business item, Bob stated that Apple Computer is now a full EIA IBIS
Open Forum member and is now listed in the Voting Members portion of the
Participants list.

Bob gave a brief overview of the meeting agenda:

  Current IBIS Model Development and Validation 
  Specific Bus Technology Problems and Experiences
  EMI/EMC Modeling Issues
  High-Speed Issues
  Future IBIS-X Progress and Discussion
  Closing Issues and Discussions

EXPERIENCES WITH AND TIPS FOR IBIS MODELS
Eckhard Lenski, Siemens AG, Germany
Eckhard Lenski shared his experiences regarding the problems that he has seen
with IBIS models.  He currently supports about 1500 IBIS I/O models for 
internal Siemens usage world-wide.  Models come from all sources including
measurement, Spice extraction, IBIS Web sites, and data books.  Newer
technologies (LVDS, CAN, PCML, PECL etc.) provide additional challenges.
Complete and consistent information is needed.

Eckhard showed some typical concerns in models and some details that should be
considered.  The topics included the gap between ground and power clamps,
unreasonable ramp voltage values, inconsistent ramp values, I-V and V-T data
load line mismatch, double counting of clamps, incorrect V_fixture voltage
information.

Because Siemens provides models for different simulators, Eckhard shared some
tips and experiences on model details.  He showed how models referenced by the 
[Driver Schedule] keyword has pullup, pulldown and clamp table keywords that
are located differently in non-IBIS formats (or visa versa).  These details
must be understood to provide correct translations.  Eckhard also commented
that differential buffers need the Vdiff parameter.  When different Vmeas 
values exist for rising and falling edges (a situation that cannot be handled 
by the existing IBIS syntax), Eckhard suggests using the average value.  He 
also showed how the timing test loads given by parallel resistors could be 
converted into the equivalent load required by the IBIS syntax.

Eckhard spoke about package model details.  He showed simulations differences
between a model with cascaded lumped sections and with a single lumped stage.
Eckhard also showed that different sized packages may actually use the same  
die and have different lengths to the pins.  Semiconductor vendors often
shrink the die in later versions of the chip.  These details should be modeled
correctly, with different package models for different component packages.

Additional details were presented.  Differential inputs can have termination
resistors connected to a common voltage such as 1.2 V.  Clamp tables can model
this effect and also include any clamp diodes.  Eckhard needs to create three
separate models for timing test load variations for typ/min/max cases.  Also,
Eckhard commented on LVDS ramp model difficulties with 50 Ohms to Ground and
to Vcc.  A waveform model is required.

The datasheet may give guidance regarding the number of model variations that
the IBIS model needs.  Different output strengths may be documented for
output buffers, and different leakage currents may be documented for inputs.
The IBIS model should be consistent with this information.  The correct C_comp
value is critical for DIMM models where a number of inputs are in parallel.
Also input capacitance can have different values at different frequencies.
A bad value can introduce delay errors.

Often when the die is shrunk (for manufacturing yield improvement), the
electrical characteristics change.  A new model should be requested.  Fabrice
Boissieres commented that clamps also change with die shrinkage.

Eckhard presented some future needs.  He really wants different component
keywords for different devices for the same family instead of a generic part.
Finally, he listed quick (one-week) responses to questions to vendors, an 
electrical model checker, and EMI model parameters.

He summarized that both IBIS-X and the new approved BIRDs are good.  Complete
IBIS Version 3.2 models are currently needed that have the relevant optional
parameters, have two rising and two falling waveforms, have the over and
undershoot parameters and better package model files (not just R_pkg, L_pkg,
and C_pkg).  When you see a pyramid top in a rain forest, you do not see the
larger base underneath that is needed.

Fabrice added that typ/min/max values for Vref are needed.

EXTRACTION OF KEY IBIS PARAMETERS FOR EASIER MODEL SELECTION
John Berrie, Zuken, England and Michael Schaeder, Zuken Germany
John Berrie described some common problems he has seen when getting IBIS
models from Web sites.  Problems (observed more often in older models) include
pins not even modeled or modeled incorrectly.  Unique model names are
needed for different types of buffers.

The ibischk3 parser provides one level of testing and specific EDA tools can
provide additional tests.  However, a method to provide just basic file
information is needed.
                      
John stated that Michael Schaeder is developing such a tool for giving basic
information about the contents of the file containing IBIS models.  This tool
(still being improved) lists the number of pins (modeled and supply pins),
model names and model types, and package model references, and model details.  
These details include the additional keywords and subparameters such as
thresholds, timing test loads, voltage range, and static characteristics (such
as inclusion of power and ground clamps).  Also, output parameters include
documenting the [Ramp] values and the [Rising Waveform] and [Falling Waveform]
fixture resistance and voltage values.

John showed samples of the output.  Such a utility would provide a quick check
of the contents of the file for the user to see that the information is
complete and consistent.  Normally such information is scattered throughout
the file and is difficult to detect.

Zuken is planning to donate this utility to the IBIS Open Forum for public
use.  This will assist in visual inspection and could be the basis for some
additional automatic reality checking in the future.  The utility, designated
"ibsinf" (IBIS Information), is expected to be ready in several months.

Bob Ross asked, and John responded that it will be supplied in Windows and
in Unix (Sun Solaris and Hewlett Packard) formats.  Gerald Bannert suggested
that more checks are possible.

DOGEN, A SIEMENS INTERNAL MODEL TOOL, EXTENSIONS 1999 - 2001
Hans Pichlmaier, Siemens AG, Germany
Hans Pichlmaier gave an overview of DOGEN, an internal modeling tool he has 
been working on for several years.  It does: 

  Quad to IBIS, IBIS to Quad and Spice to IBIS .ebd Conversions
  IBIS Scaling of typ to min/max
  Checks of Quad and IBIS models
  Works standalone or within a BIOLIB library environment
  Supports the BIOLIB structure

BIOLIB is IBIS+ with IC, passive and module data structures.  ELAN provides
layout data with the part numbers and passive components.  These are used in
as system to generate project tool libraries for Quad, ICX and Specctra based
projects.  The library generator gives local copies with EDA tool specific
features.  For example, four cases of models for signal integrity, minimum
delay, maximum delay, and worst case crosstalk analysis are generated for
Quad based projects.

The extension made in the last two years consists of:

  Passive component models
  .ebd modules inside BIOLIB
  Evidence of usage in projects
  Complex packages inside BIOLIB
  Model Viewer for I-V and V-T tables
  Conversion of Altera and Xilinx FPGA files to IBIS Pinouts
  IBIS split and IBIS expand to make BIOLIB Elements from IBIS models
  Support of IBIS Version 3.2
  Support of new Quad syntaxes for DIFFPIN and SERIESPIN

Hans illustrated the passive part generation utility where internal part
numbers, values, packages and tolerances can be input.  The appropriate IBIS
models are generated.  He also showed the command line and resulting files
for module generation within BIOLIB.  The [Reference Designator Map] is used
differently in BIOLIB than in IBIS to refer to actual part numbers instead of
file names.  

ELAN keeps track of model usage by projects.  Updates to models can be sent
automatically to any site world-wide by e-mail.

Hans stated that the data base will be extended for EMI analysis and power bus
decoupling in the future.

Arpad Muranyi asked about scaling, and Hans indicated that V-T and I-V typical
data can be scaled independently for min and max columns.  The V-T scaling is
done in a manner that the starting and ending values are consistent with the
adjusted I-V data.

Adrian Udenze asked about the monotonic check on V-T tables.  Overshoots and
undershoots are clipped if less than 10 percent to be compatible with some
EDA tools.  Over or undershoots greater than 10 percent are suspicious and
flagged as an error.  Non-monotonic ledges during the ramp section is removed
by straight line approximations.  Tom Dagostino commented that this could lead
to slower model transition times if the ledge were due to an internal package
reflection.

At the conclusion, Hans announced that he will lead the third annual Bavarian
IBIS Summit climb in the Bavarian Alps on March 17, 2001.  Everyone is 
invited.

LVDS MODELING
Hazem Hegazy and Mohammed Korany, Mentor Graphics, Egypt
Mohammed Korany provided new material from a similar presentation given at
the DesignCon 2001 IBIS Summit Meeting on January 29, 2001.  Mohammed started
by introducing some LVDS basic terminology.  The problem is how to extract
the correct I-V tables when differential outputs are connected to internal
differential termination resistors.  Sometimes such a topology is not evident
in encrypted models output models, and sometimes there is a equal current
sourcing and sinking circuitry.  Conventional techniques may cause unexpected
DC shifts if the termination resistor is changed.  Normally each pad and padn
path is terminated by a single-ended resistor (usually 50 ohms) connected to
a Vref value.  Some original methods (Methods I - III) based on some early
ideas all had DC shift mismatches for some loads.

Proposal I used equal, but opposite sign delta voltages connected to the
pad and padn pins and attached to a common Vms (mid swing voltage).  The time
response had correct DC values when the termination resistor was 50 ohms
(same as the fixture value), but significant DC shift from Spice reference
simulations when the termination resistor was 100 ohms.

Proposal II overcame the DC shift problem by doing the DC sweeps by connecting
equal resistors to pad and padn.  The resistor value was swept to obtain the
I-V tables.  This proposal had overlaying waveforms for both the single-ended
50 and 100 ohm loads, and excellent correlation with a lossy differential
transmission line interconnection.

Proposal III was a new proposal that used sweeps to actually extract the value 
of the differential termination resistor.  Two equal sweeps connected to the
pad and padn sides of the internal differential resistor was used to extract
the I-V tables values for each buffer while nulling out the effect of the
differential terminator.  This setup sparked some questions which were
discussed and resolved off-line.  Mohammed showed the schematic for the
first set of sweeps for padn set to 0 V and 1 V respectively to extract the
differential resistance value.  The resulting LVDS differential model based
on single-ended models and an [R Series] differential termination correlated
very well to the same tests as Proposal II.

Mohammed added that the C_comp value is important for such simulations.  He
showed that severe mismatched single-ended terminations (such as 150 ohms for
50 ohm lines), produce reflections.  The input C_comp value impacts the shape
and amplitude of the reflections and glitches.   The correct value of C_comp
can be estimated by such a setup by providing a value that produces the
closest responses to a reference Spice simulation.

Mohammed concluded that Proposals II and III produced the best results.  The
estimation of C_comp was very important.

SSTL_2 MODELING EXPERIENCES
Bernhard Unger, Siemens AG, Germany
Bernhard Unger investigated simulations for one and two waveform based IBIS 
models for SSTL_2 (Stub Series Terminated Logic for 2.5V) Class 1
symmetrically single parallel terminated output load and series series
resistor.

The one waveform models (suggested by Bob Ross) used R_fixture = 50 ohms and 
V_fixture = 1.25 V.  The two waveform models (suggested by Eckhard Lenski) 
used R_fixture = 50 ohms and V_fixture = 0 and 2.5 V.  Spice (HSpice 
B-element) and IBIS model simulations were compared.

Three loading conditions were checked:

  Case 1: Parallel terminated tr-line (Z0 = 50, Td = 1.5 nS); Rpara = 50 ohms, 
          Vterm = 1.125 V; Cload = 2.5 pF

  Case 2: Unterminated tr-line (Z0 = 50, Td = 1.5 nS); Cload = 2.5 pF
  
  Case 3: Parallel and series terminated tr-line (Z0 = 50, Td = 1.5 nS); 
          Rseries = 25 ohms; Rpara = 50 ohms, Vterm = 1.125 V; Cload = 2.5 pF

Bernhard showed the overlaid simulations for these cases: 

                Case 1           Case 2            Case 3

  1 Waveform:   Good             Bad mismatch      More mismatch
  
  2 Waveforms:  Slight mismatch  Slight mismatch   Slight mismatch

The Case 2, 1 Waveform simulations had a strong dependence on the HSpice 
specific multiplier relationship of rwf/rfw.  The default setting of 0.1
produced poor results, and the setting of 1.0 provided improved results.

Bernhard checked the 1 Waveform results using an arbitrary multipler table
constraint:  

  Kpudr/f(t) + Kpdr/f(t) = 1

The 1 Waveform results were better, but a zoomed in view showed that the
2 Waveform simulations were still closer to the reference simulations.

Bernhard concluded that there is a strong dependency on loading conditions and
assumptions on multiplier relationships.  He said that golden waveforms may
be needed to check the tool dependent behavioral models and real world
applications.

Bob questioned why Case 2 was considered since that case SSTL-2 was typically
used with parallel terminations.  Bernhard responded that a specific customer
had requested comparisons for Case 2 in order to save power.

LUNCH
The participants were treated to a delicious hot lunch.

CAN BUS MODELING
Manfred Maurer, Bernhard Unger, Siemens, Friedrich Hasinger, BMW
Manfred Maurer described a project to develop models for automotive control 
units to support CAN (Controller Area Network) busses.  CAN is a serial 2-wire
differential bus concept introduced by BOSCH to interconnect microcontrollers,
actuators, and sensors.  Spice models were not available, so IBIS models were
produced from measurement data.

Manfred present the CAN characteristics, applications areas, and a circuit 
model.  The network has bit rates up to 1 Mbit/sec and up to 40 m length, and 
supports at least 30 bus participants.  It also can be used in other 
applications such as for medical equipment and systems.  Busses are doublely 
terminated by 120 ohms at each end, and are wired using a 120 Ohm 
differential characteristic impedance interconnections per ISO/DIS 11898.

The electrical operation for differential signals is not symmetrical.  The 
CAN_H signal swings between 2.5 V and 3.5 V.  The CAN_L signal swings between
1.5 V and 2.5 V.  The Recessive state is when both sides are at 2.5 V (0 V
differential), and the Dominant state is when the CAN_H and CAN_L differential
voltage is 2.0 V.  An internal termination provides a 2.5 V reference.

Manfred showed actual automotive routing (in a BMW) and some electrical bus
configurations.  He stated, in response to a question from Arpad Muranyi, that
twisted cable can be used.  Manfred created single-ended IBIS models
independently for the CAN_H and CAN_L drivers.  The waveforms were extracted
by measurement using a 60 ohm differential load.  It is normal to a single
cycle of significant preshoot and corresponding overshoot ring.  The initial
modeling approach based on assuming a fixed V_fixture value of 2.5 V did not 
produce satisfactory simulation results.

Manfred presented a new approach to derive the Kpu(t) and Kpd(t) coefficients.
He connected the CAN_H pad to a 60 ohm load, and terminated it with a variable
V_fixture(t) equal to the the CAN_L voltage (and visa-versa for CAN_L).  With
this approach, the resulting IBIS differential IBIS model gave overlaying 
simulations with the measurement data.  

Manfred also showed excellent simulation correlation with in an actual bus
applications.  The comparisons showed similar similar ringing on the lines,  
the simulation ringing amplitude was less damped.  This provided a more 
conservative response and indicated that some losses in the bus might not have 
been modeled.  Manfred concluded that the IBIS can be used to produce a good 
match between behavioral simulation and measurements when a a new algorithm 
to generate switching coefficients is used.

Arpad Muranyi suggested considering issuing a BIRD for adding time a varying 
V_fixture(t) table to support this new approach.

PARASITIC IC EMISSION MODELING
Etienne Sicard, National Institute of Applied Science, France
Etienne Sicard provided the overall context of the study by showing examples
of increasing EMI radiation.  Over the past 10 years the number of components
and the clock frequencies have increased significantly, voltage levels have
decreased, but transition times and scaled currents have become more of a
problem.  He showed that radiation can be generated from many sources.

The IERSET project is a cooperative effort with industry and academia by the
European Research Centre on Electronics for Transportation.  Its objectives
are to (1) study and evaluate emission and susceptibility measurement methods
for integrated circuits, and (2) to define and validate a model to be used in 
PCB CAD tools to guarantee the EMC of electronic systems.  EMC simulation
compliance should be part of the IC design flow.

Etienne introduced the core emission model.  It consists of a current source
Ib, and the following parameters connected to the external Vdd and Vss: Rvdd,
Lvdd, Rvss, Lvss, Cb and Cd.  Existing approaches are too detailed and become
impractical for large sized chips or else are too simple and not accurate.  
With the new approach, Ib is an equivalent current generator.  Etienne showed
reasonable simulation and measurement correlation.  This model can be attached
to the IBIS I/O cell through a Zsub resistance and Cio decoupling capacitor.
This added detail gives better validation.  Etienne also added inductive and
capacitive coupling for better correlation with measurement in a TEM cell.

Etienne concluded by noting that a simple model has been proposed and has
produced satisfactory predictions of emission.  The model proposal is being
standardized by the French standards body UTE as ICEM.  The next step is to
produce an ICEM cookbook.

Bernhard Unger asked about the physical meaning of the inductance, and 
Etienne stated that it is related to length of the supply paths within a
chip.  Arpad Muranyi was concerned about lumping all pins into one model.
Etienne stated that there was a 15 dB error in simulations in non-critical
regions.  The simple model was a good start.  Gerald Bannert commented that
he expected a 5 dB mismatch.  Tom Dagostino stated that shielding within
shielding could affect the actual measurement.  Patrick dos Santos commented
that a plane close to the die also could change the results.

INTEGRATED CIRCUITS MODELING, ELECTROMAGNETIC COMPATIBILITY SIMULATION ON
PRINTED CIRCUIT BOARD
Christian Marot, Siemens, France
Christian Marot continued the ICEM presentation by showing actual testing
environments for systems and boards.  All electronic systems have to fulfill
Electromagnetic compatibility tests.  It is too late in the design cycle and
very expensive if the unit fails EMC testing in an anechoic chamber.

Christian showed how IC noise sources based on clock resonances cause the PCB
to act as an antenna through supply lines and signal lines.  Simulations are
needed early in the design process to reduce EMC test stage costs.  Currently
Spice and IBIS are used for models, and IMIC and ICEM are new proposals to
be used along with board RLGC matrices.  Increase IC model accuracy is to be
linked to the IC internal activity through supply lines, signal lines and
direct radiations.  

Christian advocated an IC data flow linking models and simulation tools.  The
objective is to use EMC simulation tools to tune virtual test boards and to
reduce the amount of expensive actual measurement validation testing.

INTEGRATED CIRCUITS MODELING, ICEM INTEGRATED CIRCUITS ELECTROMAGNETIC MODEL
PROPOSAL: IEC 62014-3
Jean Claude Perrin, Texas Instruments, France and Christian Huet, EADS Airbus,
France
Jean Claude Perrin concluded the presentation of ICEM by noting that this is
the fourth year that he has participated in the European IBIS Summit.  

Jean Claude summarized simulation needs for EMC/EMI for integrated circuit
manufacturers and printed circuit board designers.  Simulation is now needed
to comply with EMC directives and standards.  Jean Claude listed the members
of the UTE EMC Task Force and also traced the history starting with a Working
Group in 1994 and continuing through the current CDV proposal that is sent 
to IEC for standards approval in March 2001 as IEC 62014-3.  This is intended 
to be technical document.

The details of the proposed model were again presented.  The first schematic 
showed the power line contribution.  The second schematic added the I/O
contribution to a single supply structure.  The third schematic showed how
the I/O contribution can be modeled in a multiple supply structure.

Then Jean Claude showed how ICEM can be implemented in an IBIS data base.
He showed some related keywords for package modeling and then presented
some new keyword possibilities to describe the current generator and to
document the intercoupling between supplies.  Direct IC electromagnetic
emission is mainly due to the package.  The variables of interest are pin
length, frequency and RLC resonances.

Jean Claude concluded that ICEM data can be added to files such as IBIS for
simulations for EMC due to internal activity and I/O noise coupling.  He
listed some planned actions:

  Issue a cookbook to explain how ICEM model parameters are obtained (a first
    draft is written)
  Evaluate the model through the IBIS Open Forum
  Integrate ICEM in model data bases such as IBIS
  Integrate EMC simulation capability with ICEM
  Validate the software

There was some discussion on how to obtain the internal currents.  Jean Claude 
commented that IC manufactures must know this information in order to prevent 
metal migration problems in package designs.  Other comments related to
getting information from measurements and field solvers.  Patrick dos Santos 
commented that the package model may need to be more detailed.

MODELING OF GROUND-NOISE FOR CIRCUITS WITH SHORT-CHANNEL TRANSISTORS
Mariusz Faferko, Fraunhofer Institute Reliability and Microintegration,
Germany
Mariusz Faferko defined ground-noise in terms of a voltage drop across an
effective inductance.  The test circuit consists of N buffers that switch
simultaneously from high to low.  Each buffer is simplified to just a CMOS 
inverter.

His solution to model the resulting ground noise is to split the ground noise
signal into three phases:

  Slew Rate linear increase
  Time response RL circuit
  Oscillation Circuit

The presentation shows the equivalent circuits and mathematical derivations
for each phase.  Mariusz summarized the resulting equations.  These equations
were in terms of some physical parameters taken from transistor models,
circuit parameters from the schematic some simulation parameters that could
be available from IBIS models.

Mariusz showed excellent correlation between simulations based on the new
model and full circuit Spice simulations, both in the time and frequency
domains.  He also showed excellent correlation in a second example between
simulation and actual measurement.  Mariusz added later that this approach 
has been implemented in a commercial EDA tool.  The resulting noise could
be added as a source to the signal.

Tom Dagostino asked what is covered by Leff, and Mariusz clarified that it 
does include the package inductance.  Tom commented that the formulation 
ignores common mode (crossbar) currents through the driver.  This could be
added.  Ekkehard Miersch questioned whether this approach could scale linearly
for a very large number of drivers (100 or so), as implied in the formulation.  
There may be other interactions such as supply current limits and voltage 
drops.  Mariusz stated that he thought that it would, and he has had excellent 
correlation with about 30 drivers.

AN ELECTROMAGNETIC EMISSION MODEL FOR INTEGRATED CIRCUITS
Peter Kralicek, Fraunhofer Institute Reliability and Microintegration, 
Germany
Peter Kralicek noted that ICs typically are modeled by equivalent circuits
that do not contribute to emitted field analysis.  This is not sufficient for 
today's speeds and complex packages.  He proposes a another new macromodel. 

Peter listed the modeling requirements:

  Good approximation of near and far fields
  Low number of model parameters
  Parameter determination via measurement and simulation
  Simple integration into existing commercial EDA tools
  Support different modes of operation and connected circuitry

He listed a number of possible approaches and is pursuing multipole expansion
of the electromagnetic field.  The advantage of this approach is that it is
scalable for the complexity of the analysis.  He showed plots for dipole,
quadrupole, octopole and hexapole patterns.  More modes can be added, if
needed, for more accurate analysis.

Two models are proposed: the Simple Emission Model (SEM) and the Voltage 
Controlled Emission Model (VCEM).  The SEM has these attributes:

  Valid in near and far field
  Physical model
  Parameter determination via measurement of simulation
  No consideration of external circuitry

The model parameters are multipole coefficients, and these can optionally
support different modes.  The VCEM adds these attributes:

  Voltages at IC ports control modal emissions
  External circuitry (parasitic effects) considered

Peter summarized the workflow.  The model parameters could be added to IBIS
models.  This method has been used in an EDA tool that uses a method of 
moments field solver to approximate the fields for multipole expansion.  
Linear system matrix mathematics is used to determine unknown currents.
Peter reports only a minimal increase in calculation time.

Several different coupling methods are taken into account in a diagram that
shows radiations from the PCB/MCM, coupling to/from an antenna, conductive 
coupling of wires to/from the PCB/MCM, and field coupling of the wires to the 
PCB/MCM and to/from the antenna.

Peter shared some excellent simulation correlation results with almost
overlaying comparisons in the time and frequency domains to full wave
references.  He also showed a case where multipole expansion added more 
accurate simulation detail.  This approach is computationally efficient.  

POINTS OF VIEW FOR HIGH FREQUENCY IBIS MODELS
Gerald Bannert, Siemens AG, Germany
Gerald Bannert provided a list of number of detailed points regarding high 
frequency IBIS models.  His classifications are extensive and detailed, and he 
talked about several of them during the presentation.  Some other points had 
been covered in earlier presentations.  Overall, Gerald supports including 
many of the relevant optional parameters in IBIS models including some new 
ones that are described in approved BIRDs.

He listed a number of technological changes made over the past 10 years.  The
general trend is for higher speed and complexity, greater I/O variety and 
greater influence of parasitics.

In another table Gerald provided some desired Version 3.2 improvements for
handling:

  New output technologies
  Scaling algorithm for process, temperature and voltages
  Coupled package sections
  Ground bounce
  Complex input
  EMI parameters

He needs better package detail using coupled sections, but some of the losses
are currently not so important.  These include skin effect and dielectric 
losses.

One needed improvement is to model cross bar current.  Gerald summarized his 
concerns:

  He questions if there is a big demand for IBIS-X
  Further development is needed for IBIS
  He proposes technical model classification with supporting examples
  Official IBIS statement on proper model development methods

IBIS-X AND THE IBIS MACRO LANGUAGE
Stephen Peters and Arpad Muranyi, Intel, USA
In the remaining time, Arpad Muranyi gave a brief overview of the IBIS-X
ongoing work.  He adapted some of Stephen Peters' earlier presentation
material for this presentation.  The problem is that IBIS is has some serious
limitations regarding a number of important parameters.  These include:

  Dealing with some new technologies
  Return path modeling support
  Coupled package modeling support
  Receiver model advances
  Frequency domain analysis

The IBIS-X approach is to keep the good features of IBIS, but add flexibility
including nodal interconnection support for model and die interconnect
advances, and a macro language for the flexibility of creating new model
prototypes.  The presentation gave some examples of details.  Arpad warned
that the syntax is still evolving, so some IBIS-X details are presented only
for information on what is being considered.  IBIS-X has the flexibility to
define new tables and add other formats for numerical data.  The IBIS-X
extensions also include a number of Spice compatible primitives.  

Arpad touched on a number of topics.  The syntax of elements looks like a
more formal version of Spice syntax.  Data input can take on may forms from
numerical and symbolic values to multidimensional tables.  A number of 
familiar operators are defined, such as || for OR. 

Extended blocks are defined for:

  Driver
  Reshape
  Delay
  Voltage Controlled Delay

Other likely extensions include:

  Behavioral voltage and current sources similar to the Berkeley "B" element
  Integrator block
  Differentiator block
  Behavioral integrator
  Behavioral differentiator

Other extensions being considered include:

  Model creation/functionality -
    .trigger, .local, .inherit 
    
  Debug/visibility related -
    .export, .alarm, .assert
  
  Program flow -
    .if .elseif, .endif, .select, .case, .end select, .array <name>

  General equations -
    Berkeley B element

Arpad summarized the current status:

  IBIS Version 3.2 has been implemented in the IBIS-ML (macrolanguage)
  The Working Group is meeting bi-weekly doing -
    The overall IBIS-X specification
    Library guide
    Programmers Language Reference Manual
  Much work remains on the die interconnection section

In response to Gerald Bannert's question, Arpad stated that IBIS-X goes beyond 
both Spice and IBIS and addresses things that cannot be done currently. 
Gerald added that analog simulation can be possible.  Ekkehard Miersch 
commented that lumped package approximations are not sufficient.  Bob Ross 
stated that distributed models are expected to be supported.  Etienne Sicard 
questioned how IBIS-X relates ot IBIS and IMIC, and Arpad responded that these 
formats and other formats are just levels of abstraction for model details.

Someone asked why an existing higher level language such as VHDL-AMS or
Verilog-AMS was not used.  Arpad responded that we had heard presentations
and considered a number of approaches at the June 8, 2000 IBIS Summit Meeting. 
We chose the macro language approach because in matched what we were trying 
to accomplish and we were not expert enough to deal with understanding other
approaches.  The alternatives including extending IBIS, using Spice or IMIC, 
etc. seemed to be limited in some respects.  In a sense, IBIS-X could also be
viewed as a Spice-X extension since Spice was also limited for our needs.  For 
example, IMIC table model extensions could be issued using the macro language 
to describe the table transistor format and its interconnections.  Arpad added 
that when the IBIS-X discussion is moved from the Working Group to the IBIS 
Open Forum for review, and the macro language is better defined, that topic 
could be revisited.

Bob Ross added that someone would have to help drive an alternative higher
level language approach.  A formal description of IBIS-X might be the starting
point.  However, the current plan is to continue with the macro language
development and concurrent parser implementation.

CONCLUDING REMARKS
Bob Ross thanked the participants for attending and the presentors for 
providing a fine set of presentations.  Bob also thanked the sponsors and
Karine Loudet again for the setup.  The poster she produced is available at
the Web site given above.

NEXT MEETING:
The next teleconference meeting will be on Friday, March 30, 2001, from
8:00 AM to 10:00 AM.

==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            [email-masked]
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            [email-masked]
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-209
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

SECRETARY:  Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN:  Roy Leventhal (837) 797-2152, Fax: (847) 222-2799
            [email-masked]
            Senior Engineer, CommWorks Corp. (a wholly owned 3Com subsidiary)
            1800 W. Central Rd.
            Mt. Prospect, IL 60056-2293

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            [email-masked]
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
            [email-masked]
            Development Engineer, Innoveda
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  [email-masked]
      To join, change, or drop from either the IBIS Open Forum Reflector
      ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
      or both.  State your request.

  [email-masked]
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  [email-masked]
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  [email-masked]
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  [email-masked]
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results.  You can get on via FTP anonymous.
==============================================================================