Subject: RE: question on Tflight

From: "Ingraham, Andrew" <[email-masked]>
Date: Tue, 17 Apr 2001 11:40:43 -0400

> i have a question on Tflight
> when i am measuring Tflight  b/n  processor and 440bx both for fast and
> slow
> corner,
> i  am getting Tflight_min (fastcorner) value more than Tflight_max
> (slowcorner).
> I am  measuring Tflight as per guide lines.
> can i get like that ?
 
I am not sure if this is relevant to your question; I don't know whose
"guidelines" you are using; etc.

But if you define Tflight as the difference between the signal at the far
end of your actual trace, and the transmitted signal with a standard test
load, this can happen, especially if the test load is capacitive.  (Doing it
this way makes it easier to add the driver's datasheet delay to Tflight, and
the result is the total delay to the receiver's input.)

In the slow corner case, the driving device's delay into the standard test
load is more, so it is a larger number that you subtract from the total
delay to get Tflight.  If the test load is highly capacitive, it can
exaggerate this effect, causing the delay with the test load to become
larger at a faster rate than that with your real load.  You can even get
negative "wire" delays this way, especially in the slow corner case.

Regards,
Andy

---

From: "Todd Westerhoff" <[email-masked]>
Date: Tue, 17 Apr 2001 13:22:02 -0400

Andy is absolutely right ... and capacitive test loads make the problems
worse.

Moral of the story:

When using a fast driver, look only at the min flight times (ignore the max
ones)
When using a slow driver, look only at the max flight times (ignore the min
ones)

If you want to perform an intersting "sanity check" of your SI models, find
the output delay into the test load for the fast and slow driver cases
(variously called "Buffer Delay", "TIME_TO_VM" and others), and then
subtract those numbers from the datasheet values for Tcomin and Tcomax,
respectively.

The number you get represents what I think of as the "internal delay" of the
part - the time between when the clock input triggers and time "0" of the SI
simulation.  This isn't a real delay, because of the different ways the
output can be modeled, but it's an interesting "figure of merit" exercise.
In some of the devices we've worked with recently, this exercise led to the
conclusion that the output stage could be triggered up to 1ns _before_ the
device received its input clock.  This wasn't the actual case - but it
provided us with some valuable insight about just how much the part's timing
numbers were being guard-banded.

Todd.

-----Original Message-----
From: Ingraham, Andrew [mailto:[email-masked]]
Sent: Tuesday, April 17, 2001 11:41 AM
To: [email-masked]'
Cc: [email-masked]
Subject: RE: question on Tflight

Regards,
Andy

---

From: "Todd Westerhoff" <[email-masked]>
Date: Tue, 17 Apr 2001 15:33:35 -0400

A clarification to my earlier post --

Please note that the statements:

are meant only for the case where the output delay in spec'd into a large
(~50pF) capacitive load.

Sorry for any confusion ...

Todd.
-----Original Message-----
From: Todd Westerhoff [mailto:[email-masked]]
Sent: Tuesday, April 17, 2001 1:22 PM
To: Ingraham, Andrew; [email-masked]
Cc: [email-masked]
Subject: RE: question on Tflight

Moral of the story:

Todd.

-----Original Message-----
From: Ingraham, Andrew [mailto:[email-masked]]
Sent: Tuesday, April 17, 2001 11:41 AM
To: [email-masked]'
Cc: [email-masked]
Subject: RE: question on Tflight

Regards,
Andy