Subject: Reduced strength drivers and Driver Schedules

From: "Reid, Chris" <[email-masked]>
Date: Mon, 16 Apr 2001 10:13:58 -0700

Hello,

At the IBIS summit meeting in January Larry Barnes indicated the need for
IBIS support
of the SCSI drivers which reduce their drive strength when the same bit
value is held for
more than one bit period.  This can be accomplished with the current driver
schedule,
and can be made a little more robust by adding a new (previously illegal)
schedule
with a change in the interpretation.  It is easiest to explain with an
example.

As I understand it the driver can be modeled as two stages.
Both stages are on for the first bit, then only one of them if the next bit
is the same as
the previous bit.  For example, if the bit pattern is:

0 1 1 1 0 1 0 0 0

Then the pattern for the two drivers should be:

0 1 1 1 0 1 0 0 0 (the primary driver has the same bit pattern as above.)
1 1 0 0 0 1 0 1 1 (the secondary driver helps only when the bit sense
changes.)

(here I'm assuming the initial bit value (0) has been held for at least one
previous bit period.)

For example, if the primary driver is 50 ohm and the secondary driver is 100
ohm
then the combined driver has four states:

Ls: Both pulling low: (1/(1/50 + 1/100)) = 33.333 ohms pulling low
Lw: 100 ohms high and 50 ohms low
Hw: 100 ohms low and 50 ohms high
Hs: Both pulling high

So the combined two drivers in the above case are in the states:

Lw Hs Hw Hw Ls Hs Ls Lw Lw
(0   1   1    1    0   1   0   0   0)

For simplicity assume the bit period is 5 ns (in actuality its 6.25 ns).
Then
a driver schedule as follows will produce the desired states:

MS1:
Driver      Rise-On  Rise-Off   Fall-On  Fall-Off
d50Ohm      0           NA           0          NA
d100Ohm    NA         5ns          NA        5ns

The initial state is obtained by assuming the driver has been in that state
for
a long time.  For example, suppose the simulation starts with the driver
low.
Then we assume that a long time ago there was a falling transition.  This
means that d50Ohm is in the low state and d100Ohm is in the high state
(because a "long time" is more than 5 ns.)

Remember, the Fall-Off delay is when the driver is supposed to make a
rising transition relative to the falling edge.  Similarly a Rise-Off delay
is
when the driver is supposed to make a falling transition relative to the
rising edge.  Thus the d100Ohm driver switches exactly opposite to the
d50Ohm driver but with a 5ns delay.

If each bit period is 5 ns then a little work will convince you that the
above
driver schedule will produce the sequence of states given above as the
desired sequence for the example bit pattern.

There is another way to accomplish almost the same thing, but with more
flexibility and some differences as will be explained below.  Consider the
driver schedule:

MS2:
Driver      Rise-On  Rise-Off   Fall-On  Fall-Off
d50Ohm      0           NA           0          NA
d100Ohm    0           5ns          0          5ns

This schedule is not legal in IBIS 3.2.  The reason is that it calls for a
falling
transition (fall-on delay equal to zero) when the driver may already be low
because of the 5ns rise-off delay!  However, there is a simple way to use
this
schedule.  If the schedule says to transition low when the device is already
low, just stay there.  Similarly, if it says to transition high when it is
already
high, just leave the device high.

With this understanding the second driver schedule (MS2) produces exactly
the
same result as the first one (MS1) in the case where every bit period is
5ns.  The
difference is that MS2 also allows other possibilities which may
be interesting for some devices.  It also behaves differently if some bits
are held
for less than 5ns.  For example, consider driving these two schedules with a
pulse train defined as:

Start Low (assume it has been low for a long time)
Then transition at the times: 0ns 4ns

Then MS1 produces the states:
Lw if t < 0
Hs if 0 <= t < 4ns
Lw if 4ns <= t < 5ns
Ls if 5ns <= t < 9ns
Lw if 9ns <= t

But MS2 produces the states:
Lw if t < 0
Hs if 0 <= t < 4ns
Ls if 4ns <= t <= 9ns
Lw if 9ns <= t

The difference is that MS1 is in state Lw from 4ns to 5ns while
MS2 is in state Ls for that time period (the low transition starts
at 4ns.)  The reason for this difference is the MS2 schedules d100Ohm
to transition low at time 5ns because of the master rising transition at
time 0.
It also schedules a falling transition at time 4ns because of the master
falling
transition at time 4ns.  Thus the transition occurs at 4ns and when the 5ns
transition is reached d100Ohm is already in the low state so there is
nothing to do.

Thus the MS2 version may be better than the MS1 version because:
1) It responds better to over clocking (the 4ns transition example.)
2) It is more flexible.

On the other hand, MS1 requires no change to IBIS so can be used now.  Note
that the change to make MS2 usable would not involve a new syntax, just a
new
way to use the driver schedule when all four transitions are specified.

Interested parties please respond.  We need a BIRD if people think MS2 is
a good way to go.  Otherwise, MS1 shows that these drivers can already be
simulated with IBIS (assuming your simulation vendor supports full driver
schedules.)

Thanks,

Chris Reid