Subject: ibis V1 #2
From: owner-ibis@ (ibis)
To: [email-masked]

ibis             Friday, October 19 2001             Volume 01 : Number 002

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Subject: IBIS Open Forum Minutes (8/10/01)
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Date: Tue Aug 14 2001 - 09:07:41 PDT

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Subject: Re: IBIS - I/O Buffer Modeling Cookbook
From: yoked erlich ([email-masked])
Date: Tue Aug 21 2001 - 07:39:43 PDT

   * Next message: Peters, Stephen: "RE: IBIS - I/O Buffer Modeling
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   * Previous message: Guy de Burgh: "IBIS Open Forum Minutes (8/10/01)"
   * In reply to: Ross, Bob: "IBIS - I/O Buffer Modeling Cookbook"
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     Cookbook"
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Hi ,

There are another few questions about ibischk3 results:

1. I've got the next warning:
 WARNING - [Model] iovb has no description of the buffer's high state
                    DC drive characteristics (no [Pullup] table). This
warning
                    can be silenced by changing the Model_type or by adding

a
                    [Pullup] table.
This cell ('iovb') is 'Open_drain' type which according to Ibis maker cook
book do not
suppose to have [Pullup] table , only the [pulldown],[gnd_clamp] and
[power_clamp] tables ,
What do you think might be the reason of this error ?.

2. I've got the next warning:
WARNING (line 427) - Pulldown Typical data is non-monotonic
WARNING (line 427) - Pulldown Maximum data is non-monotonic
WARNING (line 428) - Pulldown Minimum data is non-monotonic
according to pulldn subtraction gnd_clamp cookbook and standard
instructions
,
it is impossible to get monotonic data.
It is even mentioned in the standard that the [pulldn] or [pullup] tables
might be non-monotonic.
Is it all right to ignore this warning ?

With regards

Yoked.
"Ross, Bob" wrote:

> Hello Yoked:
>
> We are temporarily having reflector e-mail problems,
> so you message did not get sent to the general list.
>
> However, I am responding on the ibis-users reflector
> and copying Stephen Peters, who authored the Cookbook.
> My responses are in your text noted by "*" marks. These
> are brief responses without looking at the Cookbook
> document. I am trying to convey what was intended,
> not any editorial issues regarding how it is documented.
>
> Bob Ross
> Mentor Graphics
>
> ---------------------
>
> Subject: I/O buffer modeling cookbook
> From: Yoked Erlich (r58559) ([email-masked])
> Date: Sun Aug 12 2001 - 04:18:21 PDT
>
> Hi ,
>
> I would like to ask some questions about the 'I/O buffer modeling
> cookbook'
> paper (revision 2.0X) , Which I've got from 'www.eig.org' web site.
>
> 1. Is there anywhere I can find revision 3.2 cookbook?
>
> * No, a Version 3.2 Cookbook has not been written. Cookbook 2 was
> intended to cover Version 3.2 features, but we never got that far.
>
> 2. I've an I/O buffer model which working in some chip pads as I/O ,
> some pads as steady input and some pads as steady output.
> I would like to know if the buffer grouping is made by the buffer
> type or by the pad direction?
> If buffer type is the answer so one model with I/O type in enough
> for this buffer,
> If pad direction is the answer so three model is needed for this
> buffer , I/O model , Input model and Output model
> ( in this case Input and Output model tests will be exactly the same
> as I/O model ) .
>
> * If the buffer is truely an I/O, then it should be provided and
> documented as I/O. A user might have additional knowledge that
> certain I/O buffers are configured only as Input or Output buffers.
> It would be permissible to modify that instance of the model and
> just change the Model_type. That would help the EDA tool do
> only the simulations that are relevant for the design.
>
> 3-6 questions are about 'Extracting Data for the [Ramp] keyword'
> paragraph in the cookbook :
> 3. It is written that 'if the device does not have enough
> drive capability to make a significant output transition than a
> higher load may be used' ,
> How much is significant output transition ?
>
> * I do not have any hard guideline. I prefer impedances in the
> order of magnitude of transmission line loads since that is a
> typical high-speed design application. That ususally captures
> a fast edge that would be seen with a PCB interconnect.
>
> * This makes no sense for certain weak buffers which would
> require multiple reflections to change from one state to the
> other for an open line. If the application is not high-speed,
> then it does not manner. I would guess that a higher value
> load might be OK for a driver source impedance > 300 ohms.
> Others might have different ideas.
>
> 4. it is written that ' For an open drain , measure the rise and fall
> time into the load resistor and voltage used
> by the manufacture when specifying propagation delays' , This
> sentence is not clear
> what is the test structure in open drain buffer case?.
>
> * This is ambiguous. I prefer low impedance (50 ohm) pullups to
> capture a faster edge. This may be in the order of magnitude of
> the load seen during the intial part of the transition when the
> device is connected through a PCB interconnect.
>
> 5. it is written that ' Falling edge ramp data is captured with the load
> resistor tied to VCC'
> , Is VCC mean the pmos Driver source voltage (pad voltage) or low
> voltage?
>
> * This means that one end of the load resistor is connected to
> Vcc, and the other end is connected to the output pad.
>
> 6. It is written that 'simulations are performed with C_comp included in
> the circuit' , This sentence is not clear.
> As I understood C_comp is the capacitance seen when looking from the
> pad back into the buffer ,
> It is written that C_comp should be added to the simulation , but
> C_comp is not a capacitor it is capacitance measurement.
>
> * It is difficult to de-embed the die capacitance information from a
> Spice net list (since some of the contribution is due to paramaters
> within the transistor/diode models) or from a real physical measurements.

>
> * So the intent is to clarify that the die capacitance is already
> included in any waveform extraction. Since C_comp is a first order
> approximation of the die capacitance, its effects should be included
> in an EDA tool simulation. I have not looked at the specific
> wording, but I assume this is confusing.
>
> 7. In 'Ground Clamp' paragraph it is written that 'The data in table
> must cover the range of -Vcc to Vcc ' ,
> Isn't it suppose to be -Vcc to 2*Vcc ?
>
> * This response also covers 9.
>
> * No, the minimum range is intended to be -vcc to vcc. The Power
> Clamp covers from vcc to 2vcc. When this minimum range was
> established, most Inputs were at negligle current at Vcc and the
> slope (current vs voltage) was also nearly 0. So concatenation
> of the tables produced the same effect as extrapolation.
>
> * It is allowed to extend the clamp ranges beyond the specified
> range. In some cases you should do so, especially if you are
> including the effect of an internal terminator. In such cases,
> the conditions above are not met, and I prefer -vcc to 2vcc for
> both clamp tables. Care must be taken so that
> currents are not double counted. However, for many situations,
> the "minimal" IBIS guidelines are sufficient.
>
> 8. In 'pulldn' paragraph it is written 'If the buffer is a 3-state
> device then first subtract the ground clamp current
> from the pulldown current then enter the result into the [pulldown]
> table' ,
> first , it is written above the graph 'Pullup I/V curve after
> subtraction of ground clamp currents' Which is probably mistake.
> second , Should I replace the pulldn results in Ibis model file
> after the subtraction?
>
> * What is entered in the [Pulldown] table is the result after
> subtraction.
>
> 9. In 'Power Clamp' It is written that 'the data in the table must cover
> the range of vcc to vcc*2' ,
> Isn't the range suppose to be -Vcc to 2*Vcc ?
>
> * See 7 above.
>
> --
> With regards,
> Yoked.
> _____________________________________
> E-mail: [email-masked]
> Tel: 972-9-9522482 Fax: 972-9-9522888
> WIRELESS CIRCUIT - IO GROUP
> MOTOROLA SEMICONDUCTOR ISRAEL

- --
With regards,
Yoked.
_____________________________________
E-mail:           [email-masked]
Tel: 972-9-9522482 Fax: 972-9-9522888
WIRELESS     CIRCUIT  - IO      GROUP
MOTOROLA     SEMICONDUCTOR     ISRAEL

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Subject: RE: IBIS - I/O Buffer Modeling Cookbook
From: Peters, Stephen ([email-masked])
Date: Tue Aug 21 2001 - 11:39:09 PDT

   * Next message: Ross, Bob: "IBIS - Reissue of BIRD72 - Accommodating
     PMOS and NMOS//PMOS Seri es FET Models"
   * Previous message: yoked erlich: "Re: IBIS - I/O Buffer Modeling
     Cookbook"
   * Maybe in reply to: Ross, Bob: "IBIS - I/O Buffer Modeling Cookbook"
   * Maybe reply: Peters, Stephen: "RE: IBIS - I/O Buffer Modeling
     Cookbook"
   * Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

  --------------------------------------------------------------------

Hi Yoked:

  Regarding the non-monotonic warnings, I would still check the line number

on the pulldown curves and verify what is causing the non-monotonic
warning.
It should be the area where ground clamp current was subtracted from the
total pulldown current and not somewhere else.
  By the way, when creating a model for a non-tristatable output (i.e. one
in which either the pullup or pulldown curves are always on) one does not
have to subtract ground and power clamp current from the curves. In this
case the warning should not occur.

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: yoked erlich [mailto:[email-masked]]
Sent: Tuesday, August 21, 2001 7:40 AM
To: Ross, Bob; [email-masked]; [email-masked]; [email-masked];
Sergey Sofer (r53493)
Cc: Lior Aviv
Subject: Re: IBIS - I/O Buffer Modeling Cookbook

Hi ,

There are another few questions about ibischk3 results:

1. I've got the next warning:
 WARNING - [Model] iovb has no description of the buffer's high state
                    DC drive characteristics (no [Pullup] table). This
warning
                    can be silenced by changing the Model_type or by adding

a
                    [Pullup] table.
This cell ('iovb') is 'Open_drain' type which according to Ibis maker cook
book do not
suppose to have [Pullup] table , only the [pulldown],[gnd_clamp] and
[power_clamp] tables ,
What do you think might be the reason of this error ?.

2. I've got the next warning:
WARNING (line 427) - Pulldown Typical data is non-monotonic
WARNING (line 427) - Pulldown Maximum data is non-monotonic
WARNING (line 428) - Pulldown Minimum data is non-monotonic
according to pulldn subtraction gnd_clamp cookbook and standard
instructions
,
it is impossible to get monotonic data.
It is even mentioned in the standard that the [pulldn] or [pullup] tables
might be non-monotonic.
Is it all right to ignore this warning ?

With regards

Yoked.
"Ross, Bob" wrote:

Hello Yoked:

We are temporarily having reflector e-mail problems,
so you message did not get sent to the general list.

However, I am responding on the ibis-users reflector
and copying Stephen Peters, who authored the Cookbook.
My responses are in your text noted by "*" marks. These
are brief responses without looking at the Cookbook
document. I am trying to convey what was intended,
not any editorial issues regarding how it is documented.

Bob Ross
Mentor Graphics

- ---------------------

Subject: I/O buffer modeling cookbook
From: Yoked Erlich (r58559) ([email-masked])
Date: Sun Aug 12 2001 - 04:18:21 PDT

Hi ,

I would like to ask some questions about the 'I/O buffer modeling
cookbook'
paper (revision 2.0X) , Which I've got from 'www.eig.org' web site.

1. Is there anywhere I can find revision 3.2 cookbook?

* No, a Version 3.2 Cookbook has not been written. Cookbook 2 was
intended to cover Version 3.2 features, but we never got that far.

2. I've an I/O buffer model which working in some chip pads as I/O ,
some pads as steady input and some pads as steady output.
    I would like to know if the buffer grouping is made by the buffer
type or by the pad direction?
    If buffer type is the answer so one model with I/O type in enough
for this buffer,
    If pad direction is the answer so three model is needed for this
buffer , I/O model , Input model and Output model
    ( in this case Input and Output model tests will be exactly the same
as I/O model ) .

* If the buffer is truely an I/O, then it should be provided and
documented as I/O. A user might have additional knowledge that
certain I/O buffers are configured only as Input or Output buffers.
It would be permissible to modify that instance of the model and
just change the Model_type. That would help the EDA tool do
only the simulations that are relevant for the design.

3-6 questions are about 'Extracting Data for the [Ramp] keyword'
paragraph in the cookbook :
3. It is written that 'if the device does not have enough
     drive capability to make a significant output transition than a
higher load may be used' ,
     How much is significant output transition ?

* I do not have any hard guideline. I prefer impedances in the
order of magnitude of transmission line loads since that is a
typical high-speed design application. That ususally captures
a fast edge that would be seen with a PCB interconnect.

* This makes no sense for certain weak buffers which would
require multiple reflections to change from one state to the
other for an open line. If the application is not high-speed,
then it does not manner. I would guess that a higher value
load might be OK for a driver source impedance > 300 ohms.
Others might have different ideas.

4. it is written that ' For an open drain , measure the rise and fall
time into the load resistor and voltage used
    by the manufacture when specifying propagation delays' , This
sentence is not clear
    what is the test structure in open drain buffer case?.

* This is ambiguous. I prefer low impedance (50 ohm) pullups to
capture a faster edge. This may be in the order of magnitude of
the load seen during the intial part of the transition when the
device is connected through a PCB interconnect.

5. it is written that ' Falling edge ramp data is captured with the load
resistor tied to VCC'
    , Is VCC mean the pmos Driver source voltage (pad voltage) or low
voltage?

* This means that one end of the load resistor is connected to
Vcc, and the other end is connected to the output pad.

6. It is written that 'simulations are performed with C_comp included in
the circuit' , This sentence is not clear.
    As I understood C_comp is the capacitance seen when looking from the
pad back into the buffer ,
    It is written that C_comp should be added to the simulation , but
C_comp is not a capacitor it is capacitance measurement.

* It is difficult to de-embed the die capacitance information from a
Spice net list (since some of the contribution is due to paramaters
within the transistor/diode models) or from a real physical measurements.

* So the intent is to clarify that the die capacitance is already
included in any waveform extraction. Since C_comp is a first order
approximation of the die capacitance, its effects should be included
in an EDA tool simulation. I have not looked at the specific
wording, but I assume this is confusing.

7. In 'Ground Clamp' paragraph it is written that 'The data in table
must cover the range of -Vcc to Vcc ' ,
    Isn't it suppose to be -Vcc to 2*Vcc ?

* This response also covers 9.

* No, the minimum range is intended to be -vcc to vcc. The Power
Clamp covers from vcc to 2vcc. When this minimum range was
established, most Inputs were at negligle current at Vcc and the
slope (current vs voltage) was also nearly 0. So concatenation
of the tables produced the same effect as extrapolation.

* It is allowed to extend the clamp ranges beyond the specified
range. In some cases you should do so, especially if you are
including the effect of an internal terminator. In such cases,
the conditions above are not met, and I prefer -vcc to 2vcc for
both clamp tables. Care must be taken so that
currents are not double counted. However, for many situations,
the "minimal" IBIS guidelines are sufficient.

8. In 'pulldn' paragraph it is written 'If the buffer is a 3-state
device then first subtract the ground clamp current
    from the pulldown current then enter the result into the [pulldown]
table' ,
    first , it is written above the graph 'Pullup I/V curve after
subtraction of ground clamp currents' Which is probably mistake.
    second , Should I replace the pulldn results in Ibis model file
after the subtraction?

* What is entered in the [Pulldown] table is the result after
subtraction.

9. In 'Power Clamp' It is written that 'the data in the table must cover
the range of vcc to vcc*2' ,
    Isn't the range suppose to be -Vcc to 2*Vcc ?

* See 7 above.

- --
With regards,
Yoked.
_____________________________________
E-mail:       [email-masked]
Tel: 972-9-9522482 Fax: 972-9-9522888
WIRELESS     CIRCUIT  - IO      GROUP
MOTOROLA     SEMICONDUCTOR     ISRAEL
- --
With regards,
Yoked.
_____________________________________
E-mail:           [email-masked]
Tel: 972-9-9522482 Fax: 972-9-9522888
WIRELESS     CIRCUIT  - IO      GROUP
MOTOROLA     SEMICONDUCTOR     ISRAEL

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     Cookbook"
   * Maybe in reply to: Ross, Bob: "IBIS - I/O Buffer Modeling Cookbook"
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Subject: IBIS - Reissue of BIRD72 - Accommodating PMOS and NMOS//PMOS Seri
es FET Models
From: Ross, Bob ([email-masked])
Date: Tue Aug 21 2001 - 13:00:26 PDT

   * Next message: Ross, Bob: "IBIS - BIRD73 - Fall Back Submodel"
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To All:

BIRD72 authored by Tom Dagostino is reissued for discussion since
it was not properly distributed earlier. Copies of BIRDs can
also be found under

  http://www.eda.org/pub/ibis/birds/

Bob Ross
Mentor Graphics

******************************************************************************

******************************************************************************

BIRD ID#: 72
ISSUE TITLE: Accommodating PMOS and NMOS//PMOS Series FET Models
REQUESTER: Tom Dagostino, Mentor Graphics
DATE SUBMITTED: July 26, 2001
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

******************************************************************************

******************************************************************************

STATEMENT OF THE ISSUE:

The IBIS FET Bus Switch model assumes a series NMOS FET which has its gate
tied to Vdd. We have come across two other topologies for the FET switches,

specifically:

1. What appears to be a PMOS device with it's gate tied to ground
2. Parallel NMOS and PMOS devices with gates respectively tied to Vdd and
   ground.

The IBIS Golden Parser produces warnings and errors with models that
describe
this behavior.

******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

These models cause issues with the IBIS Golden Parser and, depending on
assumptions in the simulator's implementations that support the bus switch,

analysis issues.

For the single PMOS case:

The parser is set up to see increasing current as Vgs increase where Vgs is

defined as Vcc - Vsource. Given this definition for Vgs the current Id will

decrease as 'Vgs' increases for the PMOS device with its gate to ground.
The
parser gives an error of decreasing current as 'Vgs' increases.

Simulators may make the assumption the FET is a NMOS device and may not
handle
the characteristics properly if the model gets parsed in.

For the dual PMOS/NMOS case:

In the case of the dual PMOS/NMOS topology the currents through the
parallel
FET's will sum and produce an Id curve that:

- -- starts with significant current at 'Vgs' = 0 (current is flowing through

the PMOS device)

- -- decreases by 10 to 90% at about 40% of 'Vgs' range where both the PMOS
and
NMOS devices are both on

- -- increases to a larger value at 'Vgs' = Vdd than at 'Vgs" = 0. This is
where the NMOS device is fully on

This characteristic has been observed in several devices. This will cause a

non-monotonic warning from the parser.

It is not known how all simulators will handle this non-monotonic behavior.

In general the simulators should be able to handle these characteristics.
The IV curves define the device's characteristics and the simulator should
just work with that definition.

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

The following changes are proposed:

The definition of Voltage in the IV table changes. Vgs has been Vcc -
Vsource
assuming the gate was tied to Vcc. IBIS should now assume the voltage in
the
IV table is really Vcc minus the FET's source voltage (Voltage = Vcc -
Vsource). This makes old models compatible and no change in the model
format
is required.

Decreasing current vs. Voltage are allowed.

Non-monotonic currents in the table are expected in the parallel case but
warnings can still be issued. It may be useful to have the modeler note the

type of switch in the model so the user can better understand any
non-monotonic issues.

******************************************************************************

Changes and additions to the IBIS Specification are shown by the |* lines

|=============================================================================

| Keyword: [Series MOSFET]
| Required: Yes, for series MOSFET switches
| Description: The data points under this keyword define the I-V tables for

| voltages measured at Pin 2 for a given Vds setting. Currents
| are considered positive if they flow into Pin 1. Pins 1 and
| 2 are listed under the [Series Pin Mapping] keyword under
| [Series Pin Mapping] and pin_2 columns, respectively.
| Sub-Params: Vds
| Usage Rules: The first column contains the voltage value, and the three
| remaining columns hold the typical, minimum, and maximum
| current values. The four entries, Voltage, I(typ), I(min),
| and I(max) must be placed on a single line and must be
| separated by at least one white space.
|
| All four columns are required under these keywords. However,
| data is only required in the typical column. If minimum
| and/or maximum current values are not available, the reserved
| word "NA" must be used. "NA" can be used for currents in the
| typical column, but numeric values MUST be specified for the
| first and last voltage points on any I-V table. Each I-V
| table must have at least 2, but not more than 100, voltage
| points.
|
| Other Notes: There is no monotonicity requirement. However the model
| supplier should realize that it may not be possible to derive
| a behavioral model from non-monotonic data.
|
|* the old model is:
|* The model is:
|*
|* Table Current
|* ------->
|* + Vds -
|* Pin 1 Pin 2
|* <---| |---> +
|* d |_____| - s
|* --+-- Vgs Vs
|* | g +
|* -
|* Vg = [Voltage Range] = Vcc
|* Vgs = Table Voltage = Vtable = Vcc - Vs
|* Ids = Table Current for a given Vcc and Vds
|
|*The new model is:
|*
|* Table Current
|* -------> Ids
|* + Vds -
|*
|* Vcc
|* | g
|* ----+----
|* ------- NMOS
|* Pin 1 | | Pin 2
|* <---| |---> Voltage = Vcc - Vs
|* PMOS d |_____| s
|* --+--
|* | g
|* GND
|*
|* Either of the FET's could be removed (or have zero current
|* contribution. Thus this model covers all four conditions, off,
|* single NMOS, single PMOS and parallel NMOS/PMOS.
|*
|* Voltage = Table Voltage = Vtable = Vcc - Vs
|* Ids = Table Current for a given Vcc and Vds
|
|
|* old Internal logic that is generally referenced to the power rail
|* is used to set the MOSFET switch to its 'On' state. Thus the
|* [Voltage Range] settings provide the assumed gate voltages.
|* If the [POWER Clamp Reference] exists, it overrides the
|* [Voltage Range] value. The table entries are actually the Vgs
|* values referenced to the power rail. The polarity conventions
|*
|* new Internal Logic that is generally referenced to the power rail
|* is used to set the NMOS MOSFET switch to its 'ON' state.
|* Internal logic likewise referenced to ground is used to set the
|*- PMOS device to its 'ON' state if the PMOS device is present.
|* Thus the [Voltage Range] settings provide the assumed
|* gate voltages. If the [POWER Clamp Reference] exists, it
|* overrides the [Voltage Range] value. The table entries are
|* actually Vgs of the NMOS device and Vcc - Vgs of the PMOS
!* device if present. The polarity conventions

| are identical with those used for other tables that are
| referenced to power rails. Thus the voltage column can be
| viewed as a table defining the source voltages Vs according to
| the convention: Vtable = Vcc - Vs.
|
| If the switch is used in an application such as interfacing
| between 3.3 V and 5.0 V logic, the Vcc may be biased at a
| voltage (such as 4.3 V) that is different from a power rail
| voltage (such as 5.0 V) used to create the model. Just
| readjust the [Voltage Range] entries (or [POWER Clamp
| Reference] entries).
|
| One fundamental assumption in the MOSFET switch model is that
| it operates in a symmetrical manner. The tables and
| expressions are given assuming that Vd >= Vs. If Vd < Vs,
| then apply the same relationships under the assumption that
| the source and drain nodes are interchanged. A consequence of
| this assumption is that the Vds subparameter is constrained to
| values Vds > 0. It is assumed that with Vds = 0 the currents
| will be 0 mA. A further consequence of this assumption that
| would be embedded in the analysis process is that the voltage
| table is based on the side of the model with the lowest
| voltage (and that side is defined as the source). Thus the
| analysis must allow current to flow in both directions, as
| would occur due to reflections when the switch is connected in
| series with an unterminated transmission line.
|
| The model data is used to create an On state relationship
| between the actual drain to source current, ids, and the
| actual drain to source voltage, vds:
|
| ids = f(vds).
|
| This functional relationship depends on the actual source
| voltage Vs and can be expressed in terms of the corresponding
| table currents associated with Vs (and expressed as a function
| of Vgs).
|
| If only one [Series MOSFET] table is supplied (as a first
| order approximation), the functional relationship is assumed
| to be linearly related to the table drain to source current,
| Ids, for the given Vds subparameter value and located at the
| existing gate to source voltage value Vgs. This table current
| is denoted as Ids(Vgs, Vds). The functional relationship
| becomes:
|
|* old ids = Ids(Vgs, Vds) * vds / Vds.
|*
|* new ids = Idsn(V, Vds) * vds/Vds + Idsp((Vcc - V), Vds) * vds/Vds
|
| More than one [Series MOSFET] table is permitted, but it is
| simulator dependent how the data will be used. Each
| successive [Series MOSFET] table must have a different
| subparameter value for Vds. The number of tables must not
| exceed 100.
|
| C_comp values are ignored for [Series MOSFET] models.
|-----------------------------------------------------------------------------

[On]
[Series MOSFET]
Vds = 1.0
| Voltage I(typ) I(min) I(max)
    5.0V 257.9m 153.3m 399.5m | Defines the Ids current as a
    4.0V 203.0m 119.4m 317.3m | function of Vgs, for Vds = 1.0
    3.0V 129.8m 74.7m 205.6m
    2.0V 31.2m 16.6m 51.0m
    1.0V 52.7p 46.7p 56.7p
    0.0V 0.0p 0.0p 0.0p
|=============================================================================

******************************************************************************

ANY OTHER BACKGROUND INFORMATION:

An Ad Hoc presentation on this topic was initially presented at the IBIS
Summit Meeting on June 21, 2001.

******************************************************************************

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Subject: IBIS - BIRD73 - Fall Back Submodel
From: Ross, Bob ([email-masked])
Date: Tue Aug 21 2001 - 13:03:04 PDT

   * Next message: Peters, Stephen: "IBIS Open Forum Meeting Agenda for
     8/31"
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To All:

BIRD73 is also reissued since it has not been properly
distributed.

Bob Ross
Mentor Graphics

****************************************************************************

**
****************************************************************************

**

BIRD ID#: 73
ISSUE TITLE: Fall Back Submodel
REQUESTER: Bob Ross, Mentor Graphics
DATE SUBMITTED: 8-2-2001
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

****************************************************************************

**
****************************************************************************

**

STATEMENT OF THE ISSUE:

Existing submodels have a trigger for turning on functions. This works for
Bus_hold (and corresponding active terminators) and Dynamic_clamp
functions.

However another mechanism to turn off the submodels is needed for AVC type
devices which have the overall driver strength reduced after the output
passes through a voltage threshold value.

****************************************************************************

**

STATEMENT OF THE RESOLVED SPECIFICATIONS:

This BIRD proposes a new Submodel_type: Fall_back. The new submodel
operates
similar to the Bus_hold submodel, but with opposite action. The trigger
turns off a submodel (presumed on) when the output die voltage passes
through a trigger threshold.

Additions are noted in the relevant sections below by |* lines:

Comments for a new section or for unchanged sections are shown using
**** lines.

|===========================================================================

==
|===========================================================================

==
|
| Section 6a
|
| A D D S U B M O D E L D E S C R I P T I O N
|
|===========================================================================

==
|===========================================================================

==
|
| The [Add Submodel] keyword can be used under a top-level [Model] keyword
to
| to add special-purpose functionality to the existing top-level model.
This
| section describes the structure of the top-level model and the submodel.
|
| TOP-LEVEL MODEL:
|
| When special-purpose functional detail is needed, the top-level model can

| call one or more submodels. The [Add Submodel] keyword is positioned
| after the initial set of required and optional subparameters of the
[Model]
| keyword and among the keywords under [Model].
|
| The [Add Submodel] keyword lists of name of each submodel and the
permitted
| mode (Driving, Non-Driving or All) under which each added submodel is
used.
|
| SUBMODEL:
|
| A submodel is defined using the [Submodel] keyword. It contains a subset
| of keywords and subparameters used for the [Model] keyword along with
other
| keywords and subparameters that are needed for the added functionality.
|
| The [Submodel] and [Submodel Spec] keywords are defined first since they
| are used for all submodels
|
| The only required subparameter in [Submodel] is Submodel_type to define
the
| list of submodel types. No subparameters under [Model] are permitted
under
| the [Submodel] keyword.
|
| The following set of keywords that are defined under the [Model] keyword
are
| supported by the [Submodel] keyword:
|
| [Pulldown]
| [Pullup]
| [GND Clamp]
| [POWER Clamp]
| [Ramp]
| [Rising Waveform]
| [Falling Waveform]
|
| The [Voltage Range], [Pullup Reference], [Pulldown Reference], [GND Clamp

| Reference], and [POWER Clamp Reference] keywords are not permitted. The
| voltage settings are inherited from the top-level model.
|
| These additional keywords are used only for the [Submodel] are documented

| in this section:
|
| [Submodel Spec]
| [GND Pulse Table]
| [POWER Pulse Table]
|
| The application of these keywords depends upon the Submodel_type entries
| listed below:
|
| Dynamic_clamp
| Bus_hold
|* Fall_back
|
| Permitted keywords that are not defined for any of these submodel types
are
| ignored. The rules for what set of keywords are required are found under
| the Dynamic Clamp and Bus Hold headings of this section.
|
|===========================================================================

==
| Keyword: [Submodel]
| Required: No
| Description: Used to define a submodel, and its attributes.
| Sub-Params: Submodel_type
| Usage Rules: Each submodel must begin with the keyword [Submodel]. The
| submodel name must match the one that is listed under an
| [Add Submodel] keyword and must not contain more than 20
| characters. A .ibs file must contain enough [Submodel]
| keywords to cover all of the model names specified under the
| [Add Submodel] keyword.
|
| Submodel_type subparameter is required and must be one of
the
| following:
|
|* Dynamic_clamp, Bus_hold, Fall_back
|
| The C_comp subparameter is not permitted under the
[Submodel]
| keyword. The total effective die capacitance including the
| submodel contributions are provided in the top-level model.
|
| Other Notes: The following list of keywords that are defined under the
| [Model] keyword can be used under [Submodel]: [Pulldown],
| [Pullup], [GND Clamp], [POWER Clamp], [Ramp], [Rising
| Waveform], and [Falling Waveform].
|
| The following list of additional keywords can be used:
| [Submodel Spec], [GND Pulse Table], and [POWER Pulse Table].
|---------------------------------------------------------------------------

- --
[Submodel]      Dynamic_clamp1
Submodel_type   Dynamic_clamp
|
**** The next two sections are unchanged, but are shown for reference:
|===========================================================================
==
|     Keyword:  [Submodel Spec]
|    Required:  No
| Description:  The [Submodel Spec] keyword defines four columns under which
|               specification and information subparameters are defined for
|               submodels.
|  Sub-Params:  V_trigger_r, V_trigger_f, Off_delay
| Usage Rules:  The [Submodel Spec] is to be used only with submodels.
|
|               The following subparameters are used:
|                 V_trigger_r           Rising edge trigger voltage
|                 V_trigger_f           Falling edge trigger voltage
|                 Off_delay             Turn-off delay from V_trigger_r or
|                                       V_trigger_f
|
|               For each subparameter contained in the first column, the
|               remaining three hold its typical, minimum and maximum
values.
|               The entries of typical, minimum and maximum be must be
placed
|               on a single line and must be separated by at least one white
|               space.  All four columns are required under the [Submodel
|               Spec] keyword.  However, data is required only in the
typical
|               column.  If minimum and/or maximum values are not available,
|               the reserved word "NA" must be used to indicate the typical
|               value by default.
|
|               The values in the minimum and maximum columns usually
|               correspond to the values in the same columns for the
inherited
|               top-level voltage range or reference voltages in the
top-level
|               model.  The V_trigger_r and V_trigger_f subparameters should
|               hold values in the minimum and maximum columns that
correspond
|               to the voltage range or reference voltages of the top-level
|               model.  The Off_delay subparameter, however, is an exception
|               to this rule because in some cases it may be completely or
|               or partially independent from supply voltages and/or
|               manufacturing process variations.  Therefore the minimum and
|               maximum entries for the Off_delay subparameter should be
|               ordered simply by their magnitude.
|
|               Unless noted, each [Submodel Spec] subparameter is
independent
|               of any other subparameter.
|
|               V_trigger_r, V_trigger_f rules:
|
|               The voltage trigger values for the rising and falling edges
|               provide the starting time when an action is initiated.
|
|               Off_delay rules:
|
|               The functionality of the Off_delay subparameter is to
provide
|               an additional time related mechanism to turn off circuit
|               elements.
|
|---------------------------------------------------------------------------
- --
| Dynamic Clamp Example:
|
[Submodel Spec]
|   Subparameter          typ        min        max
|
V_trigger_r               3.6        2.9        4.3 | Starts power pulse
table
V_trigger_f               1.4        1.2        1.6 | Starts gnd pulse table
|
| Bus Hold Example:
|
[Submodel Spec]
|   Subparameter          typ        min        max
V_trigger_r               3.1        2.4        3.7 | Starts low to high
                                                    | bus hold transition
V_trigger_f               1.8        1.6        2.0 | Starts high to low
                                                    | bus hold transition
|
| Bus_hold application with pullup structure triggered on and then clocked
off:
|
[Submodel Spec]
|   Subparameter          typ        min        max
V_trigger_r               3.1        2.4        3.7 | Low to high transition
                                                    | triggers the turn on
                                                    | process of the pullup
V_trigger_f             -10.0      -10.0      -10.0 | Not used, so trigger
                                                    | voltages are set out
                                                    | of range
Off_delay                 5n         6n         4n  | Time from rising edge
                                                    | trigger at which the
                                                    | pullup turned off
|
|===========================================================================
==
|===========================================================================
==
|
| Bus Hold:
|
| When the Submodel_type subparameter under the [Submodel] keyword is set to
| Bus_hold, the added model describes the bus hold functionality.  However,
| while described in terms of bus hold functionality, active terminators
| can also be modeled.
|
| Existing keywords and subparameters are used to describe bus hold models.
| The [Pullup] and [Pulldown] tables both are used to define an internal
| buffer that is triggered switch to its opposite state.  This switching
| transition is specified by a [Ramp] keyword or by the [Rising Waveform]
and
| [Falling Waveform] keywords.  The usage rules for these keywords are the
| same as under the [Model] keyword.  In particular, at least either the
| [Pullup] or [Pulldown] keyword is required.  Also, the [Ramp] keyword is
| required, even if the [Rising Waveform] and [Falling Waveform] tables
exist.
| However, the voltage ranges and reference voltages are inherited from the
| top-level model.
|
| For bus hold submodels, the [Submodel Spec] keyword, V_trigger_r, and
| V_trigger_f are required.  The Off_delay subparameter is optional, but can
| only be used if the submodel consists of a pullup or a pulldown structure
| only, and not both.  Devices which have both pullup and pulldown
structures
| controlled in this fashion can be modeled using two submodels, one for
each
| half of the circuit.
|
| The transition is triggered by action at the die using the [Submodel Spec]
| V_trigger_r and V_trigger_f subparameters as follows:
|
| If the starting voltage is below V_trigger_f, then the bus hold model is
set
| to the low state causing additional pulldown current.  If the starting
| voltage is above V_trigger_r, the bus hold model is set to the high state
| for additional pullup current.  When the input passes though V_trigger_f
| during a high-to-low transition at the die, the bus hold output switches
to
| the low state.  Similarly, when the input passes though V_trigger_r during
| a low-to-high transition at the die, the bus hold output switches to the
| high state.
|
| If the bus hold submodel has a pullup structure only, V_trigger_r provides
| the time when its pullup is turned on and V_trigger_f or Off_delay
provides
| the time when it is turned off, whichever occurs first.  Similarly, if the
| submodel has a pulldown structure only, V_trigger_f provides the time when
| its pulldown is turned on and V_trigger_r or Off_delay provides the time
| when it is turned off, whichever occurs first.  The required V_trigger_r
| and V_trigger_f voltage entries can be set to values outside of the input
| signal range if the pullup or pulldown structures are to be held on until
| the Off_delay turns them off.
|
| The starting mode for each of the submodels which include the Off_delay
| subparameter of the [Submodel Spec] keyword is the off state.  Also, while
| two submodels provide the desired operation, either of the submodels may
| exist without the other to simulate turning on and off only a pullup or a
| pulldown current.
|
| No additional keywords are needed for this functionality.
|---------------------------------------------------------------------------
- --
|
| Complete Bus Hold Model Example:
|
[Submodel]       Bus_hold_1
Submodel_type    Bus_hold
|
[Submodel Spec]
|   Subparameter          typ        min        max
|
V_trigger_f               1.3        1.2        1.4  | Falling edge trigger
V_trigger_r               3.1        2.6        4.6  | Rising edge trigger
|
|                         typ        min        max
| [Voltage Range]           5.0        4.5        5.5
| Note, the actual voltage range and reference voltages are inherited from
| the top-level model.
|
[Pulldown]
|
- -5V     -100uA     -80uA     -120uA
- -1V     -30uA      -25uA     -40uA
0V       0           0         0
1V       30uA       25uA     40uA
3V       50uA       45uA     50uA
5V       100uA      80uA     120uA
10v      120uA      90uA     150uA
|
[Pullup]
|
- -5V      100uA      80uA     120uA
- -1V      30uA       25uA     40uA
0V       0           0         0
1V      -30uA      -25uA    -40uA
3V      -50uA      -45uA    -50uA
5V      -100uA     -80uA    -120uA
10v     -120uA     -90uA    -150uA
|
|---------------------------------------------------------------------------
- --
|
[Ramp]
|                       typ             min             max
dV/dt_r                 2.0/0.50n       2.0/0.75n       2.0/0.35n
dV/dt_f                 2.0/0.50n       2.0/0.75n       2.0/0.35n
R_load = 500
|
|---------------------------------------------------------------------------
- --
|
| Complete Pullup Timed Latch Example:
|
[Submodel]       Timed_pullup_latch
Submodel_type    Bus_hold
|
[Submodel Spec]
|   Subparameter          typ        min        max
|
V_trigger_r               3.1        2.6        4.6  | Rising edge trigger
                                                     | Values could be set
out
                                                     | of range to disable
the
                                                     | trigger
V_trigger_f               1.3        1.2        1.4  | Falling edge
trigger[Submodel]       Dynamic_Output_r
Submodel_type    Fall_back
|
[Submodel Spec]
|   Subparameter          typ        min        max
|
V_trigger_f             -10.0      -10.0      -10.0  | Falling edge trigger
                                                     | set out of range to
                                                     | disable trigger
V_trigger_r               3.1        2.6        4.6  | Rising edge trigger
|
|                         typ        min        max
| [Voltage Range]           5.0        4.5        5.5
| Note, the actual voltage range and reference voltages are inherited from
| the top-level model.
|
[Pullup]
|
- -5V      100mA      80mA      120mA
0V       0           0         0
10v     -200mA     -160mA    -240mA
|
| [Pulldown] table omitted to signify an Open_source Submodel.
|
|---------------------------------------------------------------------------
- --
|
[Ramp]
|                       typ             min             max
dV/dt_r                 1.5/0.50n       1.43/0.75n      1.58/0.35n
dV/dt_f                 1.5/0.50n       1.43/0.75n      1.58/0.35n
R_load = 50
|
|---------------------------------------------------------------------------
- --
[Submodel]       Dynamic_Output_r
Submodel_type    Fall_back
|
[Submodel Spec]
|   Subparameter          typ        min        max
|
V_trigger_f             -10.0      -10.0      -10.0  | Falling edge trigger
                                                     | set out of range to
                                                     | disable trigger
V_trigger_r               3.1        2.6        4.6  | Rising edge trigger
|
|                         typ        min        max
| [Voltage Range]           5.0        4.5        5.5
| Note, the actual voltage range and reference voltages are inherited from
| the top-level model.
|
[Pullup]
|
- -5V      100mA      80mA      120mA
0V       0           0         0
10v     -200mA     -160mA    -240mA
|
| [Pulldown] table omitted to signify an Open_source Submodel.
|
|---------------------------------------------------------------------------
- --
|
[Ramp]
|                       typ             min             max
dV/dt_r                 1.5/0.50n       1.43/0.75n      1.58/0.35n
dV/dt_f                 1.5/0.50n       1.43/0.75n      1.58/0.35n
R_load = 50
|
|---------------------------------------------------------------------------
- --
Off_delay                 3n         5n         2n   | Delay to turn off the
                                                     | pullup table
|
| Note that if the input signal goes above the V_trigger_r value, the
| pulldown structure will turn off even if the timer didn't expire yet.
|
|                         typ        min        max
| [Voltage Range]         5.0        4.5        5.5
| Note, the actual voltage range and reference voltages are inherited from
| the top-level model.
|
[Pulldown]
|
- -5V     -100uA     -80uA     -120uA
- -1V      -30uA     -25uA     -40uA
0V       0           0         0
1V       30uA       25uA     40uA
3V       50uA       45uA     50uA
5V       100uA      80uA     120uA
10v      120uA      90uA    150uA
|
| [Pullup] table is omitted to signal Open_source functionality
|
|---------------------------------------------------------------------------
- --
|
[Ramp]
|                       typ             min             max
dV/dt_r                 2.0/0.50n       2.0/0.75n       2.0/0.35n
dV/dt_f                 2.0/0.50n       2.0/0.75n       2.0/0.35n
R_load = 500
|
|===========================================================================
==
**** This section is added:
|===========================================================================
==
|===========================================================================
==
|
| Fall Back:
|
| When the Submodel_type subparameter under the [Submodel] keyword is set to
| Fall_back, the added model describes the fall back functionality.  This
| submodel can be used to model drivers that reduce their strengths and
| increase their output impedances during their transitions.  The fall back
| function can be considered opposite of the bus hold function, but there
| some details discussed below that are unique.
|
| Existing keywords and subparameters are used to describe fall back models.
| The [Pullup] and [Pulldown] tables both are used to define an internal
| buffer that is triggered switch to its opposite state.  This switching
| transition is specified by a [Ramp] keyword or by the [Rising Waveform]
and
| [Falling Waveform] keywords.  The usage rules for these keywords are the
| same as under the [Model] keyword.  In particular, at least either the
| [Pullup] or [Pulldown] keyword is required.  Also, the [Ramp] keyword is
| required, even if the [Rising Waveform] and [Falling Waveform] tables
exist.
| However, the voltage ranges and reference voltages are inherited from the
| top-level model.
|
| For fallback submodels, the [Submodel Spec] keyword, V_trigger_r, and
| V_trigger_f are required.  Unlike the bus hold model, the Off_delay
| subparameter is not permitted.  Devices which have both pullup and
pulldown
| structures can be modeled using two submodels, one for the rising cycle
| and one for the falling cycle.
|
| The transition is triggered by action at the die using the [Submodel Spec]
| V_trigger_r and V_trigger_f subparameters as follows:
|
|   SIMULATOR RISING CYCLE:
|
|   Prior         Vdie            Rising Edge    Vdie > V_trigger_r
|   State                         Transition     Transition
|
|   low/none      <= V_trigger_r  low-to-high    high-to-low
|                 > V_trigger_r   Set/stays low  Stays low
|
|   high          <= V_trigger_r  Stays high     high-to-low
|                 > V_trigger_r   high-to-low    Stays low
|
|   SIMULATOR FALLING CYCLE:
|
|   Prior         Vdie            Falling Edge   Vdie < V_trigger_f
|   State                         Transition     Transition
|
|   high/none     => V_trigger_f  high-to-low    low-to-high
|                 < V_trigger_f   Set/stays high Stays high
|
|   low           <= V_trigger_f  Stays low      high-to-low
|                 > V_trigger_f   low-to-high    Stays high
|
|   The prior state of "none" describes the initial setting for the first
|   simulator edge encountered, either RISING or FALLING.  After that the
|   prior state is tracked.
|
| One application is to configure the submodel with one pullup structure
only.
| At the beginning of the rising edge cycle, the pullup is turned on to the
| high state.  When the die voltage passes V_trigger_r, the pullup structure
| is turned off.  Because only the pullup structure is used, the off state
is
| the same as a high-Z state.  During the falling transition, the pullup
| remains in the high-Z state.  The V_trigger_f is set out of range, so no
| futher change of state occurs.  With this approach, the overall rising
| transition starts by turning the fall back submodel turned on.  This
| submodel is triggered to drop out after the output die voltage passes a
| trigger voltage, and it remains off until the next rising transition is
| initiated.
|
| A similar submodel consisting of only a pulldown structure could be
| constructed to provide added drive strength only at the beginning of the
| falling cycle.  The complete IBIS model would have both submodels to give
| added drive strength for both the start of the rising and the start of the
| falling cycles.
|
| No additional keywords are needed for this functionality.
|---------------------------------------------------------------------------
- --
|
| Complete Dynamic Output Model Example Using Two Submodels:
|
[Submodel]       Dynamic_Output_r
Submodel_type    Fall_back
|
[Submodel Spec]
|   Subparameter          typ        min        max
|
V_trigger_f             -10.0      -10.0      -10.0  | Falling edge trigger
                                                     | set out of range to
                                                     | disable trigger
V_trigger_r               3.1        2.6        4.6  | Rising edge trigger
|
|                           typ        min        max
| [Voltage Range]           5.0        4.5        5.5
| Note, the actual voltage range and reference voltages are inherited from
| the top-level model.
|
[Pullup]
|
- -5V      100mA      80mA      120mA
0V       0           0         0
10v     -200mA     -160mA    -240mA
|
| [Pulldown] table omitted to signify an Open_source Submodel.
|
|---------------------------------------------------------------------------
- --
|
[Ramp]
|                       typ             min             max
dV/dt_r                 1.5/0.50n       1.43/0.75n      1.58/0.35n
dV/dt_f                 1.5/0.50n       1.43/0.75n      1.58/0.35n
R_load = 50
|
|---------------------------------------------------------------------------
- --
|
[Submodel]       Dynamic_Output_f
Submodel_type    Fall_back
|
[Submodel Spec]
|   Subparameter          typ        min        max
|
V_trigger_r               10.0       10.0       10.0 | Rising edge trigger
                                                     | set out of range to
                                                     | disable trigger
V_trigger_f               1.3        1.2        1.4  | Falling edge trigger
|
|                           typ        min        max
| [Voltage Range]           5.0        4.5        5.5
| Note, the actual voltage range and reference voltages are inherited from
| the top-level model.
|
[Pulldown]
|
- -5V     -100mA     -80mA     -120mA
0V       0           0         0
10v      200mA      160mA     240mA
|
| [Pullup] table omitted to signify an Open_drain Submodel.
|
|---------------------------------------------------------------------------
- --
|
[Ramp]
|                       typ             min             max
dV/dt_r                 1.5/0.50n       1.43/0.75n      1.58/0.35n
dV/dt_f                 1.5/0.50n       1.43/0.75n      1.58/0.35n
R_load = 50
|
|---------------------------------------------------------------------------
- --
****************************************************************************
**
ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:
The AVC technology is structured using various trade marked terms such as
Dynamic Output Control(tm), Dynamic Control Output(tm), etc.  They are
designed to operate by starting at full strength, but finishing at a reduced
strength (higher impedance) when the output voltage passes through a trigger
voltage.  The final higher impedance usually matches better the load (such
as
a transmission line equivalent circuit of the printed circuit board trace)
to
produce better signal integrity matching conditions.
The operation is opposite of the Bus_hold submodel which is triggered to
turn on when the die voltage passes a threshold voltage.  So a bus hold
structure cannot be configured or modified to produce this "fall back"
effect.
BIRD73 proposes a new submodel which mimics the opposite effect.  The main
idea is that when the output voltage passes a trigger voltage, a rising
transition buffer changed to a falling transition, and a falling transition
buffer is changed to a rising transition.  The two existing [Submodel]
subparameters V_trigger_r and V_trigger_f are used for the fall back
operation.
Unlike the bus hold submodel, the rules for setting the initial state are
more complicated.  Furthermore, prior history or conditions could already
nullify some transitions.  Within a simulator rising edge cycle, 0, 1 or 2
transitions are possible.  One can be initiated at the start of the cycle,
and the other initiated when the output voltage passes V_trigger_r.  Several
initialization and switching conditions exist, and a table is used to
document the allowable fixed and transition states:
SIMULATOR RISING CYCLE:
  Prior         Vdie            Rising Edge    Vdie > V_trigger_r
  State                         Transition     Transition
  low/none      <= V_trigger_r  low-to-high    high-to-low
                > V_trigger_r   Set/stays low  Stays low
  high          <= V_trigger_r  Stays high     high-to-low
                > V_trigger_r   high-to-low    Stays low
SIMULATOR FALLING CYCLE:
  Prior         Vdie            Falling Edge   Vdie < V_trigger_f
  State                         Transition     Transition
  high/none     => V_trigger_f  high-to-low    low-to-high
                < V_trigger_f   Set/stays high Stays high
  low           <= V_trigger_f  Stays low      high-to-low
                > V_trigger_f   low-to-high    Stays high
The prior state of "none" describes the initial setting for the first
simulator edge encountered, either RISING or FALLING.  After that the
prior state is tracked.
The number of transitions for each simulator cycle is limited to two or
less.
It might be possible to connect several fall back and bus hold submodels in
a manner and with different V_trigger_r and V_trigger_f values to work
against each other to cause the Vdie to move above and below the V_trigger_*
values several times within a cycle.  There does not appear to be any
practical reason to make the above state and transition tables more
complicated to account for opposite direction movement (or oscillation)
around V_trigger_*.  So after the RISING or FALLLING transitions are
initiated, some states are simply held constant regardless of potential
oscillations.  Such fixed stated are defined by "Stays high" or "Stays low".
The rules are set to work in a manner consistent with the bus hold submodel.
However, Off_delay subparameter is not supported here.  Nor is the opposite
acting subparameter proposed that might be called "Off_delay" that might
add one more transition reversal after a V_trigger_* transition.  There does
not appear to be any practical need for such an extension which would add
complication to the state and transition conditions above.
While a complete set of states and transitions are defined, the most
practical implementation for AVC technology is intended to be done with
adding two submodels, one with only a [Pullup] table for rising edge
impedance control, and one with only a [Pulldown] table for falling edge
impedance control.  With this setup, the corresponding "off" states will
be high-Z making each submodel function independently for each edge only
to increase the impedance of the final state of the buffer.  As in other
submodels, letting the V_trigger_* values to be set out of range is used
to keep the off state of the submodel in the high-Z mode.  This is shown
in an example.
The need for providing the new functionality currently exists and is
proposed
for IBIS Version 4.0 as a shorter term solution.  BIRD73 also provides the
basis for considering a more advanced solution that could be achieved using
a proposed IBIS-X Macro language.  This later solution could also provide
more
detail and a superset of what is currently practical for Version 4.0.
****************************************************************************
**
ANY OTHER BACKGROUND INFORMATION:
****************************************************************************
**

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Subject: IBIS Open Forum Meeting Agenda for 8/31
From: Peters, Stephen ([email-masked])
Date: Fri Aug 24 2001 - 08:37:15 PDT

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                     IBIS Open Forum Meeting Agenda
                              for 8/31/01

                 Bridge Number Reservation # Passcode
             (916) 356-2663 2 4779396

All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the
meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements Peters

     - Intros of New IBIS Participants, Meeting Quorum Peters
     - Membership Update and Treasurers Report Fleming/Ross
     - Review of Previous Meeting's Minutes (and ARs) Peters
     - Miscellany/Announcements All
     - Press & Web Page Updates Huq, All
     - New Models Available, Library Update Leventhal, All
     - Opens for New Issues All

8:15 Administrative and Project Discussions

     International/External Progress
     - pr EIAJ ED-5302 Standard for I/O Interface Model
          for Integrated Circuits (IMIC) Peters
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters
     - JEDEC JC-16 Modeling and Testing Sessions
     - T10, Project 1414-DT - SCSI Signal Modeling Barnes

     PCBEAST 2001 IBIS Summit Meeting Ross

     DESIGNCON 2002 IBIS Summit Meeting Planning Ross

     IBIS Model Review Committee Ross

     Majordomo Update Angulo

     New Administrative Issues All

8:45 Technical Discussion

     Connector Proposal Report Peters/Ross

     IBIS Futures Group Report Peters

     BIRD72 - Accommodating PMOS and NMOS/PMOS Series FET Dagostino/Ross
              Models

     BIRD73 - Fall Back Submodel Ross

     ibischk3 Status Ross

     BUG59 - Crash with Decimal Points for [Package] Mirmak
             Subparameters

     BUG60 - Incorrect Series Function Table Order Ross
             Dependency

     New Technical Issues All

9:50 Wrap Up and Next Meetings Plans Peters

9:55 Sign Off

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Subject: Reminder: IBIS Summit - East 9/13/01
From: Kathy Breda ([email-masked])
Date: Mon Aug 27 2001 - 12:23:46 PDT

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Subject: Re: IBIS Open Forum Meeting Agenda for 8/31
From: [email-masked]
Date: Mon Aug 27 2001 - 14:40:53 PDT

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All,

I'll be out of town and unable to attend. I'm retesting the model links as
I
write this.

Best Regards,

Roy

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Subject: IBIS SUMMIT THIRD CALL REMINDER
From: Ross, Bob ([email-masked])
Date: Tue Aug 28 2001 - 08:35:59 PDT

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To All:

Here is an updated reminder with more presentation
detail.

Bob Ross
Mentor Graphics

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- -------------------------------------------------------
IBIS SUMMIT
        THIRD CALL FOR
                PARTICIPATION &
                        PRESENTATIONS!!!
- -------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

             I B I S S U M M I T M E E T I N G

Time/Date: 8:30 AM - 5:00 PM, Thursday, September 13, 2001

Location: The Crowne Plaza Hotel
             10 Lincoln Square
             Worcester, MA
             Tel: (508) 791-1600
             Fax: (508) 791-1796

Content: Presentations and Discussions

Purpose: Solicit and Exchange IBIS Model Related Information and Ideas.

Sponsors: North East Systems Associates, Inc. (NESA),
             IBIS Users Group
             Mentor Graphics
             IBIS Open Forum
             WE ARE LOOKING FOR ADDITIONAL SPONSORS!
                  (contact Kathy Breda, [email-masked]
                  or Bob Ross, [email-masked])

PCB Conference: September 10-14, 2001
East Worcester's Centrum Centre
                Worcester, Massachusetts
                See http://www.pcbeast.com/ for more information.

BACKGROUND

The IBIS Users Group (IBIS East) has been formed under the leadership of
Dr. Edward Sayre from North East Systems Associates, Inc. (NESA) and has
been meeting to consider and forward IBIS model user concerns. As a result

of East coast meetings, the group has developed an IBIS Accuracy Handbook
document and has initiated the project to format Connector Models. These
topics plus others of current interest to the EIA IBIS Open Forum will be
discussed at this meeting.

This meeting will be conducted as a formal IBIS Summit Meeting.
Presentation
are expected to be available and archived in an electronic format, and
minutes
of the meeting will be issued. Any pending formal decisions (votes) will be

announced at least two weeks prior to the meeting.

CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development, and
digital

circuit design are invited to participate to the Summit meeting. If you
plan
to participate, please register with the information below:

  Name:
  E-mail address:
  Company:
  Telephone:

Send to:

  Kathy Breda ([email-masked])

CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS experiences
or issues.

Format of Presentation: Overhead Projections
Time: 15-30 Minutes
Electronic Archival: We request electronic versions so that the
                         presentations can be archived and also made
                         available to non-attendees. Formats used in
                         the past have been text, Power Point, Word,
                         Postscript, and Acrobat. Electronic presentations

                         should be made available by September 7, 2001.
                         Otherwise the presenter will be expected to
provide

                         up to 50 copies for distribution.

If you plan a presentation, please supply

  Title:
  Presenter:
  E-mail address:
  Company:
  Telephone:

  Estimate Time:

Send this to:

  Kathy Breda ([email-masked])

AGENDA

The agenda includes presentations, discussions, breaks, and a luncheon
(which
will be provided). This will be developed as presentation proposals are
received. So far the following presentations are planned:

  "A Proposal for s2ibis3", Michael Steer, North Carolina State University

  "Modeling the Radiated Emission of Micro-controllers", Etienne Sicard,
  National Institute of Applied Science (INSA/DEIG), France

  "Power/Ground Simulation with IBIS Models and Pin Mapping Issues",
  Raj Raghuram, Sigrity, Inc.

  "From Model Creator to Model User", Bob Haller, Cereva

  Plus IBIS Macro Language and demonstration, IBIS Connector Specification,

  and other IBIS issues.

LIST OF NEARBY HOTELS

See http://www.pcbeast.com for travel directions, hotels and other
information.

**************************************************************

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From: John Angulo ([email-masked])
Date: Wed Aug 29 2001 - 11:22:42 PDT

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Test msg only...

John Angulo
IBIS Open Forum Postmaster

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Subject: Updated with presentations - IBIS Summit Announcement
From: Kathy Breda ([email-masked])
Date: Wed Aug 29 2001 - 11:48:20 PDT

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Subject: EIA IBIS Open Forum Meeting Minutes
From: Guy de Burgh ([email-masked])
Date: Tue Sep 04 2001 - 10:18:00 PDT

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DATE: 9/4/01

SUBJECT: August 31, 2001 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2001 PARTICIPANTS LIST:
3Com (& CommWorks) Roy Leventhal
Ansoft Corporation (Eric Bracken)
Apple Computer John Figueroa
Applied Simulation Technology [Raj Raghuram], Norio Matsui,
                               Fred Balistreri
Avanti (Chen Hongyu)
Cadence Design [Ian Dodd], Patrick Dos Santos, Heiko Dudek,
                               Lynne Green*, Lance Wang*
Cisco Systems Syed Huq, Lungfu Chen
Cypress Semiconductor (Rajesh Manapat)
EMC Corporation Brian Arsenault, Jinhua Chen
Fairchild Semiconductor Adam Tambone
Huawei Technologies Rachild Chen
IBM Michael Cohen, Greg Edlund*, Wes Martin,
                               Yeon-Chang Hahm, Bill DeVey, Pravin Patel*
Innoveda (& HyperLynx) Guy de Burgh*, John Angulo*, Cary Mandel,
                               Matthew Flora, Steve Kaufer
Intel Corporation Stephen Peters*, Arpad Muranyi*,
                               Dave Lorang, Michael Mirmak*, Qinglun Chen,
                               Will Hobbs, Wei-hsing Huang
LSI Logic Larry Barnes
Mentor Graphics Bob Ross*, Tom Dagostino*, Chris Reid,
                               Mike Donnelly, Hazem Hegazy, Tony Dunbar,
                               Griff Derryberry, Dan Lake, Sherif Hammad,
                               Mohammed Korany, Weston Beal, Chris Swaim,
                               Ali Samii, Eric Ronger, Karine Loudet,
                               Daisaku Shiga, Kenji Kushima, Ian Dodd*
Micron Technology Randy Wolff*, Yong Phan*
Mitsubishi Pat Hefferan
Molex Incorporated Gus Panella, Brian O'Malley
National Semiconductor Milt Schwartz
North East Systems Associates Edward Sayre
Philips Semiconductor Zack Ciccone, Rob Mataheroe
Quantic EMC (Mike Ventham)
Signal Integrity Software Douglas Burns, Barry Katz, Walter Katz
Sigrity Raj Raghuram*
SiQual Scott McMorrow, Rob Hinz, Bernard Voss,
                               Chris Brewster
Texas Instruments Thomas Fisher, Stephen Nolan, Ramzi Ammar,
                               Jean Claude Perrin, Moshiul Haque
Time Domain Analysis Systems Dima Smolyansky, Steve Corey
Tyco Electronics (Russell Moser)
Via Technologies (Weber Chuang)
Zuken (& Incases) John Berrie, Ralf Bruening

OTHER PARTICIPANTS IN 2001:
Actel Corporation Silvia Montoya
Acuson Kim Helliwell
AMCC Jeff Smith
ASIS Ltd David Wright
Brocade Communications Robert Badal
BMW Friedrich Hasinger
Cereva Networks Bob Haller
Compaq [Peter LaFlamme], Ron Bellomio, Quang Dam,
                               Bill Ham
EADS Airbus Industry Claude Huet
  (Aerospatiale)
EFM Ekkehard Miersch, Horle Raines
EIA Cecilia Fleming
Ericsson Radio Systems Anders Ekholm
FCI Sercu Stefaan
Foundary Networks Bertram Chan
Framatom Conectors Danny Morlion
Fraunhofer Institute Mariusz Faferko, Peter Kralicek
  Reliability and
  Integration
Fujitsu Ltd Tadashi Arai, Takeshi Murakami
Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt
Hyundai Electronics Jongho Kang
Idaho State University Al Davis
Infineon Technologies Christian Sporrer
Intrinsix Corporation Steven Chin
Motorola (Rick Kingen)
National Institute of Applied Etienne Sicard
  Science (INSA)
Nokia Tapani von Ravner, Mika Castren,
                               Janne Uusitalo
Nortel Networks Calvin Trowell
Oak Technology Darmin Jin
Plexus Technology Group Joseph Socha
Siemens (& Automotive) AG Bernhard Unger, Helmut Katzier,
                               Katja Koller, Wolfram Meyer, Eckhard Lenski,

                               Gerald Bannert, Burkhard Muller,
                               Christian Marot, Manfred Maurer,
                               Amir Motamedi, Hans Pichlmaier
Sintecs Hans Klos
STMicroelectronics Peter Hirt, Fabrice Boissieres
Sun Adrian Udenze
Toshiba Corp. Hirokaza Kato, Yuichi Koga, Toshio Sudo
Xilinx Susan Wu

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings: The bridge numbers for future IBIS teleconferences are
as follows:

  Date Bridge Number Reservation # Passcode
  Thursday, September 13, 2001 IBIS Summit Meeting, No Phone Bridge

All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after. When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES
- -----------------------------------

INTRODUCTIONS AND MEETING QUORUM
No new participants

MEMBERSHIP UPDATE AND TREASURER'S REPORT
Stephen Peters reported that we have 31 new members, with one more
prospect. We had projected 30 members for the year, so we are ahead of
budget.

REVIEW OF MINUTES AND AR'S
The August 10, 2001 IBIS Minutes were approved without change.

The ARs were discussed during the meeting.

MISCELLANY/ANNOUNCEMENTS
None

PRESS AND WEB PAGE UPDATES
Bob Ross noted that Syed Huq and Cecilia Fleming did several Web updates
(Roster, Upcoming Events).

A top-level "Ver 4.0 Work In Progress" link on the web site has been
updated
with the latest Ver 4.0 draft. This unofficial draft includes the recently
passed Birds 70.5 and 71.

Bob reported that Zuken is offering a free "ibisinf" utility that works on
several platforms and can be downloaded from:

  http://www.zuken.com/ibis/ or

  http://www.zuken.com/solutions_board_ibis.asp

Stephen Peters asked what it produces. Bob responded that it provides model

information including subparameter values (e.g., Vinh, Vmeas), I-V and V-T
table informations (e.g, R_fixture value of each table). It also provides
component information including how many pins are modeled.

Bob reported that Syed added a link to this under the FREE Tools section
of the IBIS Home page.

Bob reported that Roy Leventhal is checking and updating the links on the
Models page.

Stephen added that he has invited a newly formed Signal Integrity Technical

Committee within the EMC Society (and announced on the SI reflector) to
inform the IBIS community of its activities.

NEW MODELS AVAILABLE, LIBRARY UPDATE
No new models or library updates were reported.

OPENS FOR NEW ISSUES
None

INTERNATIONAL/EXTERNAL PROGRESS
- - JEITA ED-5302 Standard for I/O Interface Model for Integrated Circuits
  (IMIC) - No report.

- - IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal
  (formerly, IEC 93/67/NP IBIS and EMC Simulation) - Stephen Peters
reported
  the Jean-Claude Perrin sent him an email stating that the document is
  now officially stored as an IEC technical document. Bob Ross will ask
  Cecilia Fleming if she can find the link.

- - JEDEC JC-16 - Modeling and Testing - No report.

- - T10, Project 1414-DT - SCSI Signal Modeling (a Technical Committee of the

  National Committee for Information Technology (NCITS)) - No report.

PCB CONFERENCE EAST 2001 IBIS SUMMIT MEETING PLANS
Stephen Peters reported that an IBIS Summit Meeting is planned for
Thursday,
September 13, 2001 in Worcester, Massachusetts at the Crowne Plaza Hotel
near the PCB Conference East 2001 show. The meeting follows the day after
the trade show portion of the show. The Upcoming events link of the IBIS
home page already contains the sign-up information and hotel information.
Free lunch and refreshments are included.

The third announcement has been sent out. Bob Ross reports that we still
expect about 20 people. Some local people have not signed up yet, and
Stephen urged those that have not signed up to do so.

To date, four presentations are planned (titles may change):

  "Modeling the Radiated Emission of Micro-controllers", Etienne Sicard,
     National Institute of Applied Science (INSA) in France

  "A Proposal for s2ibis3", Michael Steer, North Carolina State University

  "Power/Ground Simulation with IBIS Models and Pin Mapping Issues",
     Raj Raghuram, Sigrity, Inc.

  "From Model Creator to Model User", Bob Haller, Cereva Networks

Stephen added these presentations from the Working Groups:

  "Progress and Update in the Connector Specification",
     Stephen Peters, Intel

  "Progress and Issues in IBIS-X", Stephen Peters, Intel

  "IBIS-X Primitives and Example", Lynne Green, Cadence Design

Bob added later that we will work with Stephen and Kathy Breda and send
out an agenda on Thursday, September 6, 2001. He will also work with the
presenters to get the presentations in by Friday, September 7 for copying.
Otherwise the presenters should expect to bring 30 copies.

Bob also added that the sponsors to date are Mentor Graphics, NESA, the
IBIS Users Group, and the IBIS Open Forum.

DESIGNCON 2002 IBIS SUMMIT MEETING
Stephen Peters reported on the plans for the IBIS Summit Meeting scheduled
on Monday, January 28, 2002 associated with DesignCon 2002 in Santa Clara,
California. We will an Associate Sponsor. A large meeting room and
refreshments will be provided. We will also plan on a booth, and Guy de
Burgh will be handling the arrangements. Innoveda will be providing
the backdrop.

Stephen reported that National Semiconductor will sponsor the lunch, as
before. We might require a signup for lunch this time to keep the costs
reasonable.

Most of the initial plans are complete. We will be sending out the
meeting announcements and call for presentations later this year.

IBIS MODEL REVIEW COMMITTEE DISCUSSION
John Angulo reported that Texas Instrument model has been sent out for
review. Another model has been received and John will forward it to
Bob Ross. Bob also stated that he will update the IBIS home page
email link with his email address. John also mentioned that Jon Powell of
Innoveda has expressed an interest in taking on the IBIS Model Review
function. John Angulo will follow up.

MAJORDOMO UPDATE
John Angulo reported that the [email-masked] list is now propagating fully.
Stephen Peters asked if posters still need to copy the ibis-users reflector

when they post to the main IBIS relector. After a short discussion we
agreed that this procedure was no longer needed. John took the AR to issue
a note that effect to the reflector.

John then reported that we still have some archive difficulties linking
to *.txt attachments (this needs to done manually) and with ASCII formatted

data (the white space information is hard to restore). We are working on
these issues. Bob Ross added that we have been moving the location under
the IBIS FTP site and plan to open up another archive that currently only
the system administrators can read. That may help resolve the white space
archive problem.

John added that Majordomo subscriptions require his approval, but
unsubscribe requests are handled automatically.

When this is accomplished we will plan to move the ibis-users list under
Majordomo as well. This may possibly occur next week.

CONNECTOR PROPOSAL REPORT
Stephen Peters reported that connector meetings were held August 14, 21 and

the 28, with the next one scheduled for Sept 4. The major topic at these
meetings have been understanding the three different ways a connector can
be described and which keywords apply in which cases. In the course of
these discussions we simplified some keywords and eliminated some others.
The connector committee also uncovered an issue with extracting cascaded
matrixes that effects pin order to matrix row mapping. This will require
additional work to solve.

No connector meeting is scheduled for September 11.

IBIS FUTURES REPORT
Stephen Peters reported that the IBIS Futures group meet on August 16, 23
and 30 with the next meeting scheduled for Sept. 6. The Futures group has
been concentrating on transmission line matrix format as well as some
documentation issues. Stephen also reported that a proposal has been made
to the IBIS Futures group to incorporate the IBIS-X 'define' functionality
directly into the current IBIS data template via a BIRD, thus creating a
relatively straightforward path for adoption of IBIS-X and the macro
language into current IBIS. This BIRD would be issued sometime after
IBIS 4.0 was voted on by the IBIS Open Forum (i.e. it would not effect the
current progress towards IBIS 4.0). The Futures committee accepted the
proposal as the best way to move forward with IBIS-X.

Because of the IBIS east summit, no futures committee meeting is scheduled
for September 13.

BIRD72 - ACCOMMODATING PMOS AND NMOS//PMOS SERIES FET MODELS
Tom Dagostino introduced BIRD72 by reporting that he has created Switch
models from measurement. IBIS Version 3.2 assumes that the Series MOSFET
is an N channel device. Tom has observed P channel and parallel P/N
channel paths. Warning and Error messages are now generated for I-V
tables for such devices.

BIRD72 contains some changes in the notation and equations that allow for
describing these additional I-V tables. The ibischk3 parser would be
revised so that Error messages are not issued for decreasing currents.

Stephen Peters wanted some clarification regarding the Vgs and Voltage.
Tom responded that for P/N MOSFET configurations, the gate voltage was
ambiguous. So Voltage is used in the table, and the Vgs reference is
removed. Lynne Green wanted to know if a different I-V table was needed,
and Tom responded that the same I-V table is used. Raj Raghuram questioned
whether the tables worked for enhanced and depletion mode FETs. Tom
thought that the I-V tables should still represent the data. Bob Ross
noted that there were a few editorial corrections needed.

Stephen stated that with some clarifications, a revised BIRD72.1 might be
ready for a vote in October, 2001.

AR - Tom Dagostino will issue BIRD72.1 with the discussed editorial changes

and clarifications.

BIRD73 - FALL BACK SUBMODEL
Bob Ross introduced BIRD73 by noting that IBIS Version 3.2 does not cover
the AVC technology devices offered by about four manufacturers. This
technology has a stage turn off during the transition to weaken the overall

driver at the end. This weaker driver may have an output resistance that
provides a better match to the transmission line load.

Bob stated that the existing Bus Hold submodel works in the opposite
manner.
It can be triggered to provide a stronger drive. So a new Fall Back
submodel is introduced. One complication is that the state changes for
turning off a device are more difficult to describe. The SIMULATOR RISING
CYCLE: and SIMULATOR FALLING CYCLE: tables in the documentation attempts to

do this. Both a rising or falling edge transition and a voltage trigger
may cause a buffer state change. The table attempts to characterize what
the model will do under all conditions including an ambiguous initial
state.

Bob indicated that the example really illustrates an application with ideal

50 Ohm submodels configured as Open_drain and Open_source models. This
assures that the off state is also a high-Z state that provides no load.
He also noted that the V_trigger_* values can be sent out of range to
assure no unwanted triggering can occur. Unlike the Bus Hold submodel, the
Off_delay subparameter is not defined.

Stephen Peters noted that BIRD73 incorrectly copied the Fall Back example
as
the existing Bus Hold example. Bob will correct this. He will also make
a correction to an Off_delay example. Bob also noted that BIRD73 is a
candidate for prototyping in the macro language.

Stephen also suggested adding a "state" table to the Bus hold example.

AR - Bob Ross will issue BIRD73.1 with the discussed corrections and
changes.

IBISCHK3 BUG TRACKING STATUS
Bob Ross reported that Atul Agarwal has started work on fixing BUGs 48 -
56.
Bob has provided more information on BUG54. The expectation is that
ibischk3 Version 3.2.8 will be available by the end of September 2001.

BUG59 - Crash with Decimal Points for [Package] Subparameters
Per the discussion at the last meeting, Bob Ross reported that John Angulo
validated that the parser did crash under Windows 2000.

Bob proposed that we upgrade the classification from ANNOYING, LOW, OPEN to

MODERATE, LOW, OPEN.

We still may need Innoveda to help identify the problem and provide a
solution based on several Windows specific issues. Assuming that Atul
does not have access to a Windows 2000 system, John Angulo took the AR to
contact Matt Flora to see if he can help identify the fix.

BUG60 - Incorrect Series Function Table Order Dependency
Bob Ross introduced BUG60. An incorrect warning message is issued for
[Series Switch Groups] entries that are not in the same sequence as the
function_table_group entries. For example, a line

  On 1 2 3 4 /

works, but

  On 2 1 3 4 /

causes incorrect Warning messages related to undefined switch functions.
The IBIS Version 3.2 specification does not require that the entries follow

the same sequence.

Bob proposed classifying this as MODERATE, MEDIUM, OPEN since the parser
gives an incorrect Warning on a legal IBIS model. The short term work
around is to carefully order the [Series Switch Groups] entries. After
some discussion the group agreed with this classification.

NEXT MEETING:
The next meeting will be the IBIS Summit Meeting on Thursday, September 13,

2001 from 8:30 AM to 5:00 PM. No teleconference connection is planned.

============================================================================

                                      NOTES

IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
            [email-masked]
            Senior Hardware Engineer, Intel Corporation
            M/S JF4-215
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

VICE CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            [email-masked]
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN: Roy Leventhal (837) 797-2152, Fax: (847) 222-2799
            [email-masked]
            Senior Engineer, CommWorks Corp. (a wholly owned 3Com
            subsidiary)
            1800 W. Central Rd.
            Mt. Prospect, IL 60056-2293

WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
            [email-masked]
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
            [email-masked]
            Development Engineer, Innoveda
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  [email-masked]
      In the body, for the IBIS Open Forum Reflector:
      subscribe ibis <your e-mail address>

      In the body, for the IBIS Users' Group Reflector:
      subscribe ibis-users <your e-mail address>

      Help and other commands:
      help

  [email-masked]
      To join, change, or drop from either the IBIS Open Forum Reflector
      ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
      or both. State your request.

  [email-masked]
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  [email-masked]
      To send a message to the general IBIS Open Forum Reflector. This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements. Job posting information is not permitted.

  [email-masked]
      To send a message to the IBIS Users' Group Reflector. This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns. Job posting information is not permitted.

  [email-masked]
      To report ibischk2/3 parser bugs. The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported
      bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, and
      /pub/ibis/bugs/s2iplt/bugsplt.txt respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results. You can get on via FTP anonymous.

============================================================================

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Subject: Ibis_model
From: yoked erlich ([email-masked])
Date: Thu Sep 06 2001 - 08:13:40 PDT

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  --------------------------------------------------------------------

Hi ,

I've got the next warning about [falling Waveform] simulation,

WARNING - Model ipad6wd: The [Falling Waveform]
      with [R_fixture]=50 Ohms and [V_fixture_min]=3V
      has MIN column DC endpoints of 1.29V and 3.00v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 1.27V and 2.94V),
      a difference of 1.64% and 2.18%, respectively.

I understood the first part of the warning , but I can't figure out how
does the checker find the second voltage range
(as it appear in the warning the range is yields from the I/V tables and
I couldn't find any sign to this voltage in I/V tables)

- --
With regards,
Yoked.
_____________________________________
E-mail:           [email-masked]
Tel: 972-9-9522482 Fax: 972-9-9522888
WIRELESS     CIRCUIT  - IO      GROUP
MOTOROLA     SEMICONDUCTOR     ISRAEL

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Subject: IBIS SUMMIT MEETING AGENDA 9/13/01
From: Ross, Bob ([email-masked])
Date: Thu Sep 06 2001 - 10:47:13 PDT

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  --------------------------------------------------------------------

To IBIS Participants:

Here is the Agenda for the IBIS Summit Meeting. We do expect
interactive discussions and some possible Ad Hoc presentations
to fill out the day.

If you plan to come, but have not notified anyone, please let
Kathy Breda know to help us plan the refreshment and free lunch
participation. E-mail is [email-masked].

We am looking forward to seeing you in Worcester and having a
productive meeting.

Bob Ross
Mentor Graphics

************************************************************

I B I S S U M M I T M E E T I N G A G E N D A

Time/Date: 8:30 AM - 5:00 PM, Thursday, September 13, 2001

Location: The Crowne Plaza Hotel
                10 Lincoln Square
                Worcester, Massachusetts
                Tel: (508) 791-1600
                Fax: (508) 791-1796

Content: IBIS Presentations and Discussions

Purpose: Solicit and Exchange IBIS Model Related Information and
                Ideas.

Sponsors: Mentor Graphics
                North East Systems Associates, Inc.
                IBIS Open Forum
                IBIS Users Group

PCB Conference: September 10-14, 2001
East Worcester's Centrum Centre
                Worcester, Massachusetts
                See http://www.pcbeast.com/ for more information.

************************************************************

IBIS SUMMIT AGENDA

8:30 AM MORNING REFRESHMENTS

9:00 AM Introductions and Business
          Stephen Peters, Intel

9:15 AM Keynote Remarks
          Ed Sayre, North East Systems Associates (NESA)

9:30 AM From Model Creator to Model User
          Bob Haller, Cereva Networks

10:00 AM A Proposal for s2ibis3
          Paul Franzon, North Carolina State University

10:30 AM BREAK AND REFRESHMENTS

10:45 AM Modeling the Radiated Emission of Micro-controllers
          Etienne Sicard, National Institute of Applied Science (INSA)

11:30 AM Power/Ground Simulation with IBIS Models and Pin Mapping
          Issues
          Raj Raghuram, Sigrity, Inc.

12:00 PM LUNCH (Free to Attendees)

1:00 PM Progress and Update in the Connector Specification
          Stephen Peters, Intel Corporation

1:30 PM Progress and Issues in IBIS-X
          Stephen Peters, Intel Corporation

2:00 PM IBIS-X Primitives and Example
          Lynne Green, Cadence Design Systems

2:30 PM BREAK AND REFRESHMENTS

2:45 PM Unscheduled Ad Hoc Topics

3:15 PM Roundtable - Other Topics
          Stephen Peters, Intel, Ed Sayre, NESA

5:00 PM FINAL BUSINESS AND ADJOURN

************************************************************

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Subject: Changes to IBIS East Summit
From: Peters, Stephen ([email-masked])
Date: Tue Sep 11 2001 - 15:24:53 PDT

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  --------------------------------------------------------------------

Greetings:

  Due to the disruption in air travel, many of the officers and presenters
will not be able attend Thursday's IBIS East summit in person.
Nevertheless, the IBIS Summit and Users Group meeting WILL be held, albeit
in a scaled down fashion. Ed Sayer (NESA) has agreed to host a Users Group
meeting with the attendees already at PCB East. As for the IBIS Summit
itself, Intel has arranged for a teleconference connection to the Users
Group meeting. The teleconference will be from 6:00am - 9:00am Pacific time

(9:00am - 12:00pm Eastern). We will conduct whatever IBIS business required

and then work thru the presentations, especially Paul Fanzon's S2IBIS3
presentation and Mr. Sicard's EMI work with IBIS. We can extend the
teleconference if folks desire and there are topics to discuss. The dial in

number, bridge number and passcode are as follows:

Dial in number: 1-916-356-2663
Bridge number: Bridge 3
Passcode: 5127881

Presenters, if you have not already done so please mail your presentation
(electronic format) to [email-masked] for placement on the IBIS web
site.

Thanks everyone for you patience and understanding.

  Regards,
  Stephen Peters
  Intel Corp.
  Chair, EIA/IBIS Open Forum

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Subject: EIA IBIS Open Forum Meeting Minutes
From: Guy de Burgh ([email-masked])
Date: Tue Sep 18 2001 - 18:16:05 PDT

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  --------------------------------------------------------------------

DATE: 9/18/01

SUBJECT: September 13, 2001 EIA IBIS Summit Meeting Minutes

VOTING MEMBERS AND 2001 PARTICIPANTS LIST:
3Com (& CommWorks) Roy Leventhal
Ansoft Corporation (Eric Bracken)
Apple Computer John Figueroa
Applied Simulation Technology [Raj Raghuram], Norio Matsui,
                               Fred Balistreri
Avanti (Chen Hongyu)
Cadence Design [Ian Dodd], Patrick Dos Santos, Heiko Dudek,
                               Lynne Green*, Lance Wang*
Cisco Systems Syed Huq, Lungfu Chen
Cypress Semiconductor (Rajesh Manapat)
EMC Corporation Brian Arsenault, Jinhua Chen
Fairchild Semiconductor Adam Tambone
Huawei Technologies Rachild Chen
IBM Michael Cohen, Greg Edlund, Wes Martin,
                               Yeon-Chang Hahm, Bill DeVey, Pravin Patel
Innoveda (& HyperLynx) Guy de Burgh, John Angulo, Cary Mandel,
                               Matthew Flora, Steve Kaufer
Intel Corporation Stephen Peters**, Arpad Muranyi*,
                               Dave Lorang, Michael Mirmak, Qinglun Chen,
                               Will Hobbs, Wei-hsing Huang
LSI Logic Larry Barnes
Mentor Graphics Bob Ross**, Tom Dagostino, Chris Reid,
                               Mike Donnelly, Hazem Hegazy, Tony Dunbar,
                               Griff Derryberry, Dan Lake, Sherif Hammad,
                               Mohammed Korany, Weston Beal, Chris Swaim*,
                               Ali Samii, Eric Ronger, Karine Loudet,
                               Daisaku Shiga, Kenji Kushima, Ian Dodd
Micron Technology Randy Wolff, Yong Phan
Mitsubishi Pat Hefferan
Molex Incorporated Gus Panella, Brian O'Malley
National Semiconductor Milt Schwartz
North East Systems Associates Edward Sayre*
Philips Semiconductor Zack Ciccone, Rob Mataheroe
Quantic EMC (Mike Ventham)
Signal Integrity Software Douglas Burns, Barry Katz, Walter Katz
Sigrity Raj Raghuram*, Winson Yu*
SiQual Scott McMorrow*, Rob Hinz, Bernard Voss,
                               Chris Brewster
Texas Instruments Thomas Fisher, Stephen Nolan, Ramzi Ammar,
                               Jean Claude Perrin, Moshiul Haque
Time Domain Analysis Systems Dima Smolyansky, Steve Corey
Tyco Electronics (Russell Moser)
Via Technologies (Weber Chuang)
Zuken (& Incases) John Berrie, Ralf Bruening

OTHER PARTICIPANTS IN 2001:
Actel Corporation Silvia Montoya
Acuson Kim Helliwell
AMCC Jeff Smith
ASIS Ltd David Wright
Brocade Communications Robert Badal
BMW Friedrich Hasinger
Cereva Networks Bob Haller*
Compaq [Peter LaFlamme], Ron Bellomio, Quang Dam,
                               Bill Ham
EADS Airbus Industry Claude Huet
  (Aerospatiale)
EFM Ekkehard Miersch, Horle Raines
EIA Cecilia Fleming
Ericsson Radio Systems Anders Ekholm
FCI Sercu Stefaan
Foundary Networks Bertram Chan
Framatom Conectors Danny Morlion
Fraunhofer Institute Mariusz Faferko, Peter Kralicek
  Reliability and
  Integration
Fujitsu Ltd Tadashi Arai, Takeshi Murakami
Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt
Hyundai Electronics Jongho Kang
Idaho State University Al Davis
Infineon Technologies Christian Sporrer
Intrinsix Corporation Steven Chin
KAW/USA Shinichi Maeda*
Motorola (Rick Kingen)
National Institute of Applied Etienne Sicard**
  Science (INSA)
Nokia Tapani von Ravner, Mika Castren,
                               Janne Uusitalo
North Carolina State U. Paul Franzon**
Nortel Networks Calvin Trowell
Oak Technology Darmin Jin
Plexus Technology Group Joseph Socha
Siemens (& Automotive) AG Bernhard Unger, Helmut Katzier,
                               Katja Koller, Wolfram Meyer, Eckhard Lenski,

                               Gerald Bannert, Burkhard Muller,
                               Christian Marot, Manfred Maurer,
                               Amir Motamedi, Hans Pichlmaier
Sintecs Hans Klos
STMicroelectronics Peter Hirt, Fabrice Boissieres
Sun Adrian Udenze
Toshiba Corp. Hirokaza Kato, Yuichi Koga, Toshio Sudo
Xilinx Susan Wu

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings: The bridge numbers for future IBIS teleconferences are
as follows:

  Date Bridge Number Reservation # Passcode
  October 5, 2001 1-888-316-5901 none 6159969
  October 26, 2001 1-916-356-2663 3 0776283

All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after. When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.

Four people who attended by teleconference are designate by **.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES
- -----------------------------------

                  IBIS SUMMIT MEETING LOGISTICS NOTE
The IBIS Summit meeting was held on Thursday, September 13, 2001 in the
Crowne Plaza Hotel located in Worcester, Massachusetts at the same time as
the PCB Conference East 2001. Because of the tragic attack on America on
September 11, 2001, the arrangements needed to be adjusted. Several people
were already attending the PCB Conference East, but others could not travel

to the site. After some consultation, we decided to hold the meeting as a
combined on-site/teleconference meeting. Intel provided the phone bridge.
A total of 14 people representing 11 organizations participated and 4 of
these people participated by telephone. Four of the presentations were
delivered by telephone and copies were available on-site.

INTRODUCTIONS AND BUSINESS
Stephen Peters welcomed the participants and thanked the co-sponsors Mentor

Graphics, North East Systems Associates, the IBIS Users Group and IBIS Open

Forum. Stephen also thanked Kathy Breda and North East Systems Associates
for the arrangements and for the last minute logistical adjustments. All
of the meeting presentation slides were available at the meeting and had
also been uploaded at the site:

  http://www.eda.org/pub/ibis/summits/sep01/

Stephen stated that there were no business issues. Stephen asked for any
open topics. None were offered at that time, but at the end of the
meeting Arpad Muranyi gave a brief presentation:

Arpad Muranyi - Correlation Study for DDR Style Terminations with IBIS
                Models

KEYNOTE REMARKS
Stephen Peters introduced Ed Sayre, Chair of the IBIS Users Group for some
keynote remarks.

After thanking Intel for the bridge, Ed expressed concern that the IBIS
specification was becoming too complex for the middle ground user and
becoming too hard to use. A tutorial is needed to understand the
specification, and a paper or presentation detailing the theoretical basis
behind IBIS behavioral modeling would be helpful. He also felt that while
the model developer needs to be concerned about the syntactical issues, the

user needs more graphical information content. In short, the basic concepts

need to be communicated better. Ed suggested that money and resources be
set
aside for IBIS training.

The group commented and discussed Ed's remarks. Arpad Muranyi state that
complexity was added in Version 3.2 to deal with new technologies beyond
the
original scope of IBIS. Bob Haller stated that the IBIS Cookbook (which
needs to be updated) has some graphical representations. Lynne Green
commented
that users buy tools to do the work and engineers are more software
literate,
and the participants agreed that most IBIS models are created by junior
level
engineers. Raj Raghuram suggested that a university professor could write a

book or produce more information on IBIS. Bob Ross noted that EDA Vendors
and
other commercial vendors often provide model training and model development

support and also stated that Arpad Muranyi has a four hour Real-Time video
IBIS
tutorial that is available. Stephen Peters did acknowledge that the IBIS
Specification could be clearer.

                  PRESENTATIONS AND DISCUSSION TOPICS
The rest of the meeting consisted of presentations and discussions. These
notes capture some of the content and discussion. See the uploaded
documents
for more detail.

FROM MODEL CREATOR TO MODEL USER
Bob Haller, Cereva Networks
Bob Haller started by showing that some public IBIS models still have a
large number of errors. Bob showed an AC termination simulation where IBIS
produced good results quickly. He also showed a simulation result where
the Spice model was appropriate.

Moving from model creator to model user, Bob now sees good and bad models.
He commented that he can identify and fix models and provide some vendor
feedback. Bob noted that given today's short design cycles one has to
request
models early. Market forces are generally driving model quality, but he
still
recommends verifying IBIS models in the lab.

Bob then went on to give examples of typical model problems. He noted that
the additional PCI loads will be handled in IBIS Version 4.0. However,
there are improvements and vendors are more responsive. Bob stated that
work
is continuing on advances (Connector Specification, IBIS-X), and pointed to
a
number of resources. These includes Syed Huq's DesignCon 2000 paper as well

as friends and colleagues.

Bob Ross commented that some good models are produced by EDA and commercial

vendors, and some of these vendor also help semiconductor vendors produce
models.

A PROPOSAL FOR s2ibis3
Paul Franzon and Michael Steer, North Carolina State University (NCSU)
Paul Franzon via teleconference gave some background showing strong
industrial connections and support for analog, RF and mixed mode research
based on federal funding. Paul is proud of the earlier NCSU s2ibis and
s2ibis2 contributions to IBIS and industry. A multi-university DARPA
project covers a number of advanced modeling and simulation abstractions:

  Global Environment, Michael Steer, NCSU
  Digital Behavioral Modeling and SSN Macromodeling, Paul Franzon, NCSU
  Parasitic Extraction and Full Wave Modeling of Interconnect, Andreas
    Cangellaris, U. of Illinois
  Optoelectronic Modeling, Mark Neifeld, University of Arizona

Paul gave an overview of the other activities. Regarding his topic, he
planned a macromodeling tool for automatic accurate reduced-order SSN
modeling of on-chip digital structures from full circuit descriptions. Its
unique feature is a macromodel production tool similar to Spice2IBIS and
a complete SSN macromodel conversion tool.

Paul then covered point-by-point the s2ibis3 project requirements that were

issued by the IBIS sub-committee. Some notable points include:

  C++ based, JAVA for graphics
  Flex and Bison and portability through GNU and Cygwin in MS Windows
  A separate IBIS parser may be developed
  Improved algorithms and configuration options.
  Improved Spice controls for improved convergence (e.g., Vdd ramping,
    more .options, fixing some clamping problems, data point and time,
    voltage step options, etc.)

In addition, the goals are to support:

  GNU public license
  Class structures to support digital and analog macromodeling with IBIS
    as a subset
  Be applicable for board level modeling and modeling of segments of mixed
    signal chips

The research agenda includes support of IBIS-X with SSN macromodeling, 3-D
models, and testing and validating against Spice and measurement. Paul
intends to have industrial collaborators. This 3-year DARPA effort will
produce a spice2ibis3 and have strong industrial collaboration.

Several questions and suggestions were discussed during the presentation.
Ed Sayre and Lynne Green commented that the s2ibis3 utility should handle
differential models and models with strong feedback (such as those having
gate modulation). Numerical stability presents a challenge, and there was
a long discussion regarding the utility of models and simulators supporting

VDD ramping. Several people stated that they would investigate providing
some industrial support.

PROGRESS AND UPDATE ON THE CONNECTOR SPECIFICATION
Stephen Peters, Intel Corporation
Because of a conflicting meeting, Stephen Peters' two presentations
were moved up to this position in the meeting.

Stephen, via teleconference, stated that the IBIS Connector header and
about three-fourths of the technical description have been reviewed.
The Working Group plans to add the conductance matrix (G Matrix) for
losses and also frequency dependent simulations. Both the LRGC and
S-parameter formats are being considered. We expect a specification
completion by the end of January 2002 if there are no unexpected
technical issues.

Stephen gave some more detail on changes including even_mode, odd_mode,
and quiescent model types and Fork and Endfork under a [Path Description]
keyword. Electrical matrix "row" order can be random, so a pin number
to matrix map has been added.

Stephen and others then discussed the advantages of using
S-parameters versus RLGC matrices. S-parameters are more natural for
frequency domain simulations while RLGC are more natural and familiar to
engineers for time domain simulations. Ed asked if the inductance
matrix was for partial or loop inductances. Bob Ross indicated that
for full matrix the inductance is partial, however, there was some
discussion on whether loop inductances are appropriate for single
line models. After much discussion Stephen agreed to make sure that
the connector specification fully documents partial vs. loop inductances
and when each are used.

PROGRESS AND ISSUES IN IBIS-X
Stephen Peters, Intel Corporation
Stephen Peters stated that a simpler path into IBIS is being pursued.
Shortly after IBIS Version 4.0 is approved, the Working Group intends to
issue a BIRD to add the [Define 'class name'] concept. The work is now
focusing on the macro-language reference manual (IBIS-ML). This is being
reviewed and should be available in January 2002.

Stephen listed some technical milestones that have been met or are being
tracked. Then Stephen described the [Define "class name"] keyword. He
showed the syntax. It can be used in the IBIS file itself. Defines can
be collected in a library file. Once an object is defined, it can be
customized in the IBIS file.

Ed Sayre asked about backward compatibility with IBIS Version 3.2, and
Stephen said that IBIS Version 3.2 (and 4.0) will be supported by being
defined in the macro language.

MODELING THE RADIATED EMISSION OF MICRO-CONTROLLERS
Christian Marot, Siemens, Andre Peyre Lavigne, Motorola, Claud Huet, Eads
Airbus, Etienne Sicard, National Institute of Applied Science (INSA)
After lunch, Etienne Sicard, via teleconference, introduced the need for
EMC
modeling of ICs. The industry is working with 0.12u, 6 metal technology
with up to 200,000,000 devices and CPU frequencies of 1 GHz. The dI/dt
switching speeds have become faster causing increased EMC problems. Etienne

showed identical devices from different vendors. One device designed
without
considering radiation showed to be out of compliance by 20 to 40 dB
compared
to other chip. Currently EMC problems are found after the fact and
require costly design iterations to correct.

The IERSET (a European research institution for research in transportation)

EMC project for ICs is co-sponsored by EADS Airbus, Siemens Automotive,
Motorola, Alcatel, INSA, and IERSET. The objectives are to define and
validate a model for PCB CAD tools to guarantee the EMC of electronic
systems. Its focus is on a model from 1 MHz to 1 GHz for conducted and
radiated emission. The French standards organization UTE has issued a
draft Integrated Circuit Electromagnetic compatibility Model (ICEM) and
forwarded it to IEC as a Committee Draft for Voting 62014-3. An ICEM
Cookbook Version 1c is available. ICEM presentations and papers are
planned at conferences, at company sites and at IBIS Summit meetings.

Etienne described the core emission model and its basic parameters Cd and
core noise generator Ib and advanced parameters for secondary resonance
Rvdd, Lvdd, Rvss, Lvss and Cb. He gave typical values and showed some
good measurement and simulation comparisons. In response to a question
by Raj Raghuram, Etienne clarified that the measurements and simulations
were for near field emissions. Scott McMorrow and others commented on the
resonance terminology since the since all resonances including the
"primary" resonance were many multiples above the 8 MHz fundamental clock
frequency. In response to Lynne Green's question some typical values of
all parameters were given (Cd - 300 pF to 20 nF, Cb - 1 nF, Lvdd and Lvss -

15 nH).

The equivalent current generator was extracted through Verilog gate level
simulation and simple statistical considerations. Spice and interpolated
transistor level methods had either size or number of device limitations.

The core emission model can be extended with an IBIS I/O model. An I/O
buffer is added along with a Cio decoupling capacitor and a substrate
resistance Zsub (typically 1 to 10 ohms). Etienne showed good simulation
predictions with TEM cell measurements up to 300 MHz with the core emission

model alone, and improved correlation up to 800 MHz when the I/O model was
added.

Etienne stressed that this is a relatively simple model that can be used
for
predicting parasitic emission of complex chips. Bob Ross added that a link
to Etienne's work that includes several presentations and draft documents
exists under:

  http://intrage.insa-tlse.fr/~etienne/Emc/index.html

POWER/GND SIMULATION USING IBIS MODELS AND PIN MAPPING ISSUES
Raj Raghuram, Sigrity, Inc.
In introducing the subject Raj Raghuram stated that analysis based on ideal

planes are no longer sufficient. Routing of traces through multiple layers
and with vias is now common. Advanced signal and power integrity now
combines the circuit along with trace transmission lines the pin RLC and
non-ideal ground and power plane simulation. This can take care of power
ground noise (SSN or Delta-I or ground bounce), effects of vias and return
path discontinuity, effects of decoupling capacitors, and edge radiation
from boards due to SSN.

The approach he takes is to do combined circuit/transmission line/power/
ground simulation with IBIS models in the time domain (in contrast to a
separate frequency domain power/ground analysis). He does need the [Pin
Mapping] keyword for the IBIS models. Raj showed some topologies and some
results. Full analysis distorts the signal, but well-placed decoupling
capacitors can produce a nearly ideal response since return path and
other discontinuities are bypassed. Raj provided plots illustrating the
improvement provided by decoupling capacitors.

Raj also illustrated some several types of devices with unique pin mapping
requirements. These included separating different supplies and possible
different clamp references from the buffer, core and I/O parts of the IC,
and separating analog and digital ground pins.

Raj stressed that [Pin Mapping] is essential and is a zeroth order effect
in simulation that includes more accurate ground and power effects.

Lynne Green asked if the decoupling capacitors had parasitic elements. Raj
responded that they did not, but the RL information was available form the
manufacturers and easy to add.

IBIS-X PRIMITIVES AND EXAMPLE
Lynne Green, Cadence Design Systems
Lynne Green introduced IBIS Version 3.2 as having a fixed topology with
some flexibility regarding values and allowable IBIS setups.

She listed some usages of "model" in IBIS as a "circuit" model for a
predefined topology, a "component" model for pins and packages and a
"buffer" model for numbers, vectors, and data tables. IBIS-X retains the
last two usages, but introduces a "behavioral" model where the model maker
defines the topology.

Lynne then used some examples to show some of the IBIS-X capability. The
simple model under [Define Model] inherited an existing IBIS Version 3.2
buffer model as a "model_base", but added voltage and temperature dependent

capacitor and resistor elements. Another example showed how resistor and
capacitor tables could be specified. As second buffer had the same tables
with different data.

IBIS-X "behavioral" models add components that model effects (such as
vsource), has symbolic values such as C_comp, has tables and equations for
components, and can deal with other variables such as time and temperature.

Lynne showed some primitives (resistor, capacitor, inductor, voltage and
current sources, voltage controlled voltage and current sources, and
transmission lines. She illustrated variations of the resistor primitive.

The model maker provides the model behavior, the model data, and pin list.
The users may provide pin lists (such as for FPGAs) and model selector
information.

Much discussion occurred during the presentation. Ed Sayre and others did
feel that the syntax and terminology was confusing and did not relate to
what engineers already know and use. We should use words with a common
context. This should be raised as an issue for the Futures committee.
It was not clear whether the set of primitives does or should include
current and voltage controlled current sources. Engineers are already
familiar with the set of four controlled sources. Options regarding coupled

transmission line modeling were discussed. One suggestion was to have
local temperature controlled resistors modeling thermal hot spots. IBIS-X
will continue to support MKS units. There was some concern over how EDA
vendors would support IBIS-X.

Lynne concluded that IBIS-X should be regarded as an extension of IBIS.

CORRELATION STUDY FOR DDR STYLE TERMINATIONS WITH IBIS MODELS
(Unscheduled Presentation)
Arpad Muranyi, Intel Corporation
Arpad Muranyi investigated the accuracy of the recommended waveform loads
with respect to the DDR style terminations such as 50 ohms to Vdd/2.

He showed two sets of results:

  (1) V_fixture = 0, 5 V and R_fixture = 50 ohms
  (2) V_fixture = 2.5 V, R_fixture = 50 ohms

Arpad's concern was that the results for (1) did not overlay for the
DDR termination. Also the results for (2) overlayed for the DDR termination

(same as the load), but gave bad results for 50 ohms to ground and Vdd for
both the rising and falling edges. His results were based on the HSPICE
B-element.

Scott McMorrow suggested a larger load resistance such as 100 ohms for (1)
because the voltages of the existing waveforms did not overlap center
region. Bob Ross suggested exploring Vdd/2 and 2Vdd/3 voltages with 50 ohm
loads to center the four waveform loads.

Arpad plans to send the ibis model to EDA vendors to test in their own
tools
since they may have different algorithms.

[Added note, the uploaded presentations show that Scott's and Bob's
suggestions did not produce improved results]

FINAL BUSINESS
Bob Ross reported that the next IBIS Summit Meeting is scheduled on January

28, 2002 at DesignCon2002 in Santa Clara, California. We are also working
on arrangements for an IBIS Summit Meeting on March 8, 2002 at Date 2002 in

Paris, France. The weekly IBIS Working Groups on the Connector
Specification
and on IBIS-X will continue next week.

Ed Sayre offered space at NESA to those who needed working facilities while

waiting for their return trips.

NEXT MEETING:
The next teleconference meeting will be on Friday October 5, 2001

============================================================================

                                      NOTES

IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
            [email-masked]
            Senior Hardware Engineer, Intel Corporation
            M/S JF4-215
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

VICE CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            [email-masked]
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN: Roy Leventhal (837) 797-2152, Fax: (847) 222-2799
            [email-masked]
            Senior Engineer, CommWorks Corp. (a wholly owned 3Com
            subsidiary)
            1800 W. Central Rd.
            Mt. Prospect, IL 60056-2293

WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
            [email-masked]
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
            [email-masked]
            Development Engineer, Innoveda
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  [email-masked]
      In the body, for the IBIS Open Forum Reflector:
      subscribe ibis <your e-mail address>

      In the body, for the IBIS Users' Group Reflector:
      subscribe ibis-users <your e-mail address>

      Help and other commands:
      help

  [email-masked]
      To join, change, or drop from either the IBIS Open Forum Reflector
      ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
      or both. State your request.

  [email-masked]
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  [email-masked]
      To send a message to the general IBIS Open Forum Reflector. This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements. Job posting information is not permitted.

  [email-masked]
      To send a message to the IBIS Users' Group Reflector. This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns. Job posting information is not permitted.

  [email-masked]
      To report ibischk2/3 parser bugs. The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported
      bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, and
      /pub/ibis/bugs/s2iplt/bugsplt.txt respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results. You can get on via FTP anonymous.

============================================================================

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Subject: EIA IBIS Open Forum Meeting Minutes for 9/13/01
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Date: Wed Sep 19 2001 - 15:01:18 PDT

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9/19/01

A number of members were lost from the [email-masked] list.
The problem has been corrected and they have been resubscribed.
The minutes are being resent to everyone on the list so that
those who did not get a copy the first time have a copy now.
I apologize if you have already received these minutes.

Guy de Burgh
Secretary.

DATE: 9/18/01

SUBJECT: September 13, 2001 EIA IBIS Summit Meeting Minutes

VOTING MEMBERS AND 2001 PARTICIPANTS LIST:
3Com (& CommWorks) Roy Leventhal
Ansoft Corporation (Eric Bracken)
Apple Computer John Figueroa
Applied Simulation Technology [Raj Raghuram], Norio Matsui,
                               Fred Balistreri
Avanti (Chen Hongyu)
Cadence Design [Ian Dodd], Patrick Dos Santos, Heiko Dudek,
                               Lynne Green*, Lance Wang*
Cisco Systems Syed Huq, Lungfu Chen
Cypress Semiconductor (Rajesh Manapat)
EMC Corporation Brian Arsenault, Jinhua Chen
Fairchild Semiconductor Adam Tambone
Huawei Technologies Rachild Chen
IBM Michael Cohen, Greg Edlund, Wes Martin,
                               Yeon-Chang Hahm, Bill DeVey, Pravin Patel
Innoveda (& HyperLynx) Guy de Burgh, John Angulo, Cary Mandel,
                               Matthew Flora, Steve Kaufer
Intel Corporation Stephen Peters**, Arpad Muranyi*,
                               Dave Lorang, Michael Mirmak, Qinglun Chen,
                               Will Hobbs, Wei-hsing Huang
LSI Logic Larry Barnes
Mentor Graphics Bob Ross**, Tom Dagostino, Chris Reid,
                               Mike Donnelly, Hazem Hegazy, Tony Dunbar,
                               Griff Derryberry, Dan Lake, Sherif Hammad,
                               Mohammed Korany, Weston Beal, Chris Swaim*,
                               Ali Samii, Eric Ronger, Karine Loudet,
                               Daisaku Shiga, Kenji Kushima, Ian Dodd
Micron Technology Randy Wolff, Yong Phan
Mitsubishi Pat Hefferan
Molex Incorporated Gus Panella, Brian O'Malley
National Semiconductor Milt Schwartz
North East Systems Associates Edward Sayre*
Philips Semiconductor Zack Ciccone, Rob Mataheroe
Quantic EMC (Mike Ventham)
Signal Integrity Software Douglas Burns, Barry Katz, Walter Katz
Sigrity Raj Raghuram*, Winson Yu*
SiQual Scott McMorrow*, Rob Hinz, Bernard Voss,
                               Chris Brewster
Texas Instruments Thomas Fisher, Stephen Nolan, Ramzi Ammar,
                               Jean Claude Perrin, Moshiul Haque
Time Domain Analysis Systems Dima Smolyansky, Steve Corey
Tyco Electronics (Russell Moser)
Via Technologies (Weber Chuang)
Zuken (& Incases) John Berrie, Ralf Bruening

OTHER PARTICIPANTS IN 2001:
Actel Corporation Silvia Montoya
Acuson Kim Helliwell
AMCC Jeff Smith
ASIS Ltd David Wright
Brocade Communications Robert Badal
BMW Friedrich Hasinger
Cereva Networks Bob Haller*
Compaq [Peter LaFlamme], Ron Bellomio, Quang Dam,
                               Bill Ham
EADS Airbus Industry Claude Huet
  (Aerospatiale)
EFM Ekkehard Miersch, Horle Raines
EIA Cecilia Fleming
Ericsson Radio Systems Anders Ekholm
FCI Sercu Stefaan
Foundary Networks Bertram Chan
Framatom Conectors Danny Morlion
Fraunhofer Institute Mariusz Faferko, Peter Kralicek
  Reliability and
  Integration
Fujitsu Ltd Tadashi Arai, Takeshi Murakami
Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt
Hyundai Electronics Jongho Kang
Idaho State University Al Davis
Infineon Technologies Christian Sporrer
Intrinsix Corporation Steven Chin
KAW/USA Shinichi Maeda*
Motorola (Rick Kingen)
National Institute of Applied Etienne Sicard**
  Science (INSA)
Nokia Tapani von Ravner, Mika Castren,
                               Janne Uusitalo
North Carolina State U. Paul Franzon**
Nortel Networks Calvin Trowell
Oak Technology Darmin Jin
Plexus Technology Group Joseph Socha
Siemens (& Automotive) AG Bernhard Unger, Helmut Katzier,
                               Katja Koller, Wolfram Meyer, Eckhard Lenski,

                               Gerald Bannert, Burkhard Muller,
                               Christian Marot, Manfred Maurer,
                               Amir Motamedi, Hans Pichlmaier
Sintecs Hans Klos
STMicroelectronics Peter Hirt, Fabrice Boissieres
Sun Adrian Udenze
Toshiba Corp. Hirokaza Kato, Yuichi Koga, Toshio Sudo
Xilinx Susan Wu

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings: The bridge numbers for future IBIS teleconferences are
as follows:

  Date Bridge Number Reservation # Passcode
  October 5, 2001 1-888-316-5901 none 6159969
  October 26, 2001 1-916-356-2663 3 0776283

All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after. When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.

Four people who attended by teleconference are designate by **.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES
- -----------------------------------

                  IBIS SUMMIT MEETING LOGISTICS NOTE
The IBIS Summit meeting was held on Thursday, September 13, 2001 in the
Crowne Plaza Hotel located in Worcester, Massachusetts at the same time as
the PCB Conference East 2001. Because of the tragic attack on America on
September 11, 2001, the arrangements needed to be adjusted. Several people
were already attending the PCB Conference East, but others could not travel

to the site. After some consultation, we decided to hold the meeting as a
combined on-site/teleconference meeting. Intel provided the phone bridge.
A total of 14 people representing 11 organizations participated and 4 of
these people participated by telephone. Four of the presentations were
delivered by telephone and copies were available on-site.

INTRODUCTIONS AND BUSINESS
Stephen Peters welcomed the participants and thanked the co-sponsors Mentor

Graphics, North East Systems Associates, the IBIS Users Group and IBIS Open

Forum. Stephen also thanked Kathy Breda and North East Systems Associates
for the arrangements and for the last minute logistical adjustments. All
of the meeting presentation slides were available at the meeting and had
also been uploaded at the site:

  http://www.eda.org/pub/ibis/summits/sep01/

Stephen stated that there were no business issues. Stephen asked for any
open topics. None were offered at that time, but at the end of the
meeting Arpad Muranyi gave a brief presentation:

Arpad Muranyi - Correlation Study for DDR Style Terminations with IBIS
                Models

KEYNOTE REMARKS
Stephen Peters introduced Ed Sayre, Chair of the IBIS Users Group for some
keynote remarks.

After thanking Intel for the bridge, Ed expressed concern that the IBIS
specification was becoming too complex for the middle ground user and
becoming too hard to use. A tutorial is needed to understand the
specification, and a paper or presentation detailing the theoretical basis
behind IBIS behavioral modeling would be helpful. He also felt that while
the model developer needs to be concerned about the syntactical issues, the

user needs more graphical information content. In short, the basic concepts

need to be communicated better. Ed suggested that money and resources be
set
aside for IBIS training.

The group commented and discussed Ed's remarks. Arpad Muranyi state that
complexity was added in Version 3.2 to deal with new technologies beyond
the
original scope of IBIS. Bob Haller stated that the IBIS Cookbook (which
needs to be updated) has some graphical representations. Lynne Green
commented
that users buy tools to do the work and engineers are more software
literate,
and the participants agreed that most IBIS models are created by junior
level
engineers. Raj Raghuram suggested that a university professor could write a

book or produce more information on IBIS. Bob Ross noted that EDA Vendors
and
other commercial vendors often provide model training and model development

support and also stated that Arpad Muranyi has a four hour Real-Time video
IBIS
tutorial that is available. Stephen Peters did acknowledge that the IBIS
Specification could be clearer.

                  PRESENTATIONS AND DISCUSSION TOPICS
The rest of the meeting consisted of presentations and discussions. These
notes capture some of the content and discussion. See the uploaded
documents
for more detail.

FROM MODEL CREATOR TO MODEL USER
Bob Haller, Cereva Networks
Bob Haller started by showing that some public IBIS models still have a
large number of errors. Bob showed an AC termination simulation where IBIS
produced good results quickly. He also showed a simulation result where
the Spice model was appropriate.

Moving from model creator to model user, Bob now sees good and bad models.
He commented that he can identify and fix models and provide some vendor
feedback. Bob noted that given today's short design cycles one has to
request
models early. Market forces are generally driving model quality, but he
still
recommends verifying IBIS models in the lab.

Bob then went on to give examples of typical model problems. He noted that
the additional PCI loads will be handled in IBIS Version 4.0. However,
there are improvements and vendors are more responsive. Bob stated that
work
is continuing on advances (Connector Specification, IBIS-X), and pointed to
a
number of resources. These includes Syed Huq's DesignCon 2000 paper as well

as friends and colleagues.

Bob Ross commented that some good models are produced by EDA and commercial

vendors, and some of these vendor also help semiconductor vendors produce
models.

A PROPOSAL FOR s2ibis3
Paul Franzon and Michael Steer, North Carolina State University (NCSU)
Paul Franzon via teleconference gave some background showing strong
industrial connections and support for analog, RF and mixed mode research
based on federal funding. Paul is proud of the earlier NCSU s2ibis and
s2ibis2 contributions to IBIS and industry. A multi-university DARPA
project covers a number of advanced modeling and simulation abstractions:

  Global Environment, Michael Steer, NCSU
  Digital Behavioral Modeling and SSN Macromodeling, Paul Franzon, NCSU
  Parasitic Extraction and Full Wave Modeling of Interconnect, Andreas
    Cangellaris, U. of Illinois
  Optoelectronic Modeling, Mark Neifeld, University of Arizona

Paul gave an overview of the other activities. Regarding his topic, he
planned a macromodeling tool for automatic accurate reduced-order SSN
modeling of on-chip digital structures from full circuit descriptions. Its
unique feature is a macromodel production tool similar to Spice2IBIS and
a complete SSN macromodel conversion tool.

Paul then covered point-by-point the s2ibis3 project requirements that were

issued by the IBIS sub-committee. Some notable points include:

  C++ based, JAVA for graphics
  Flex and Bison and portability through GNU and Cygwin in MS Windows
  A separate IBIS parser may be developed
  Improved algorithms and configuration options.
  Improved Spice controls for improved convergence (e.g., Vdd ramping,
    more .options, fixing some clamping problems, data point and time,
    voltage step options, etc.)

In addition, the goals are to support:

  GNU public license
  Class structures to support digital and analog macromodeling with IBIS
    as a subset
  Be applicable for board level modeling and modeling of segments of mixed
    signal chips

The research agenda includes support of IBIS-X with SSN macromodeling, 3-D
models, and testing and validating against Spice and measurement. Paul
intends to have industrial collaborators. This 3-year DARPA effort will
produce a spice2ibis3 and have strong industrial collaboration.

Several questions and suggestions were discussed during the presentation.
Ed Sayre and Lynne Green commented that the s2ibis3 utility should handle
differential models and models with strong feedback (such as those having
gate modulation). Numerical stability presents a challenge, and there was
a long discussion regarding the utility of models and simulators supporting

VDD ramping. Several people stated that they would investigate providing
some industrial support.

PROGRESS AND UPDATE ON THE CONNECTOR SPECIFICATION
Stephen Peters, Intel Corporation
Because of a conflicting meeting, Stephen Peters' two presentations
were moved up to this position in the meeting.

Stephen, via teleconference, stated that the IBIS Connector header and
about three-fourths of the technical description have been reviewed.
The Working Group plans to add the conductance matrix (G Matrix) for
losses and also frequency dependent simulations. Both the LRGC and
S-parameter formats are being considered. We expect a specification
completion by the end of January 2002 if there are no unexpected
technical issues.

Stephen gave some more detail on changes including even_mode, odd_mode,
and quiescent model types and Fork and Endfork under a [Path Description]
keyword. Electrical matrix "row" order can be random, so a pin number
to matrix map has been added.

Stephen and others then discussed the advantages of using
S-parameters versus RLGC matrices. S-parameters are more natural for
frequency domain simulations while RLGC are more natural and familiar to
engineers for time domain simulations. Ed asked if the inductance
matrix was for partial or loop inductances. Bob Ross indicated that
for full matrix the inductance is partial, however, there was some
discussion on whether loop inductances are appropriate for single
line models. After much discussion Stephen agreed to make sure that
the connector specification fully documents partial vs. loop inductances
and when each are used.

PROGRESS AND ISSUES IN IBIS-X
Stephen Peters, Intel Corporation
Stephen Peters stated that a simpler path into IBIS is being pursued.
Shortly after IBIS Version 4.0 is approved, the Working Group intends to
issue a BIRD to add the [Define 'class name'] concept. The work is now
focusing on the macro-language reference manual (IBIS-ML). This is being
reviewed and should be available in January 2002.

Stephen listed some technical milestones that have been met or are being
tracked. Then Stephen described the [Define "class name"] keyword. He
showed the syntax. It can be used in the IBIS file itself. Defines can
be collected in a library file. Once an object is defined, it can be
customized in the IBIS file.

Ed Sayre asked about backward compatibility with IBIS Version 3.2, and
Stephen said that IBIS Version 3.2 (and 4.0) will be supported by being
defined in the macro language.

MODELING THE RADIATED EMISSION OF MICRO-CONTROLLERS
Christian Marot, Siemens, Andre Peyre Lavigne, Motorola, Claud Huet, Eads
Airbus, Etienne Sicard, National Institute of Applied Science (INSA)
After lunch, Etienne Sicard, via teleconference, introduced the need for
EMC
modeling of ICs. The industry is working with 0.12u, 6 metal technology
with up to 200,000,000 devices and CPU frequencies of 1 GHz. The dI/dt
switching speeds have become faster causing increased EMC problems. Etienne

showed identical devices from different vendors. One device designed
without
considering radiation showed to be out of compliance by 20 to 40 dB
compared
to other chip. Currently EMC problems are found after the fact and
require costly design iterations to correct.

The IERSET (a European research institution for research in transportation)

EMC project for ICs is co-sponsored by EADS Airbus, Siemens Automotive,
Motorola, Alcatel, INSA, and IERSET. The objectives are to define and
validate a model for PCB CAD tools to guarantee the EMC of electronic
systems. Its focus is on a model from 1 MHz to 1 GHz for conducted and
radiated emission. The French standards organization UTE has issued a
draft Integrated Circuit Electromagnetic compatibility Model (ICEM) and
forwarded it to IEC as a Committee Draft for Voting 62014-3. An ICEM
Cookbook Version 1c is available. ICEM presentations and papers are
planned at conferences, at company sites and at IBIS Summit meetings.

Etienne described the core emission model and its basic parameters Cd and
core noise generator Ib and advanced parameters for secondary resonance
Rvdd, Lvdd, Rvss, Lvss and Cb. He gave typical values and showed some
good measurement and simulation comparisons. In response to a question
by Raj Raghuram, Etienne clarified that the measurements and simulations
were for near field emissions. Scott McMorrow and others commented on the
resonance terminology since the since all resonances including the
"primary" resonance were many multiples above the 8 MHz fundamental clock
frequency. In response to Lynne Green's question some typical values of
all parameters were given (Cd - 300 pF to 20 nF, Cb - 1 nF, Lvdd and Lvss -

15 nH).

The equivalent current generator was extracted through Verilog gate level
simulation and simple statistical considerations. Spice and interpolated
transistor level methods had either size or number of device limitations.

The core emission model can be extended with an IBIS I/O model. An I/O
buffer is added along with a Cio decoupling capacitor and a substrate
resistance Zsub (typically 1 to 10 ohms). Etienne showed good simulation
predictions with TEM cell measurements up to 300 MHz with the core emission

model alone, and improved correlation up to 800 MHz when the I/O model was
added.

Etienne stressed that this is a relatively simple model that can be used
for
predicting parasitic emission of complex chips. Bob Ross added that a link
to Etienne's work that includes several presentations and draft documents
exists under:

  http://intrage.insa-tlse.fr/~etienne/Emc/index.html

POWER/GND SIMULATION USING IBIS MODELS AND PIN MAPPING ISSUES
Raj Raghuram, Sigrity, Inc.
In introducing the subject Raj Raghuram stated that analysis based on ideal

planes are no longer sufficient. Routing of traces through multiple layers
and with vias is now common. Advanced signal and power integrity now
combines the circuit along with trace transmission lines the pin RLC and
non-ideal ground and power plane simulation. This can take care of power
ground noise (SSN or Delta-I or ground bounce), effects of vias and return
path discontinuity, effects of decoupling capacitors, and edge radiation
from boards due to SSN.

The approach he takes is to do combined circuit/transmission line/power/
ground simulation with IBIS models in the time domain (in contrast to a
separate frequency domain power/ground analysis). He does need the [Pin
Mapping] keyword for the IBIS models. Raj showed some topologies and some
results. Full analysis distorts the signal, but well-placed decoupling
capacitors can produce a nearly ideal response since return path and
other discontinuities are bypassed. Raj provided plots illustrating the
improvement provided by decoupling capacitors.

Raj also illustrated some several types of devices with unique pin mapping
requirements. These included separating different supplies and possible
different clamp references from the buffer, core and I/O parts of the IC,
and separating analog and digital ground pins.

Raj stressed that [Pin Mapping] is essential and is a zeroth order effect
in simulation that includes more accurate ground and power effects.

Lynne Green asked if the decoupling capacitors had parasitic elements. Raj
responded that they did not, but the RL information was available form the
manufacturers and easy to add.

IBIS-X PRIMITIVES AND EXAMPLE
Lynne Green, Cadence Design Systems
Lynne Green introduced IBIS Version 3.2 as having a fixed topology with
some flexibility regarding values and allowable IBIS setups.

She listed some usages of "model" in IBIS as a "circuit" model for a
predefined topology, a "component" model for pins and packages and a
"buffer" model for numbers, vectors, and data tables. IBIS-X retains the
last two usages, but introduces a "behavioral" model where the model maker
defines the topology.

Lynne then used some examples to show some of the IBIS-X capability. The
simple model under [Define Model] inherited an existing IBIS Version 3.2
buffer model as a "model_base", but added voltage and temperature dependent

capacitor and resistor elements. Another example showed how resistor and
capacitor tables could be specified. As second buffer had the same tables
with different data.

IBIS-X "behavioral" models add components that model effects (such as
vsource), has symbolic values such as C_comp, has tables and equations for
components, and can deal with other variables such as time and temperature.

Lynne showed some primitives (resistor, capacitor, inductor, voltage and
current sources, voltage controlled voltage and current sources, and
transmission lines. She illustrated variations of the resistor primitive.

The model maker provides the model behavior, the model data, and pin list.
The users may provide pin lists (such as for FPGAs) and model selector
information.

Much discussion occurred during the presentation. Ed Sayre and others did
feel that the syntax and terminology was confusing and did not relate to
what engineers already know and use. We should use words with a common
context. This should be raised as an issue for the Futures committee.
It was not clear whether the set of primitives does or should include
current and voltage controlled current sources. Engineers are already
familiar with the set of four controlled sources. Options regarding coupled

transmission line modeling were discussed. One suggestion was to have
local temperature controlled resistors modeling thermal hot spots. IBIS-X
will continue to support MKS units. There was some concern over how EDA
vendors would support IBIS-X.

Lynne concluded that IBIS-X should be regarded as an extension of IBIS.

CORRELATION STUDY FOR DDR STYLE TERMINATIONS WITH IBIS MODELS
(Unscheduled Presentation)
Arpad Muranyi, Intel Corporation
Arpad Muranyi investigated the accuracy of the recommended waveform loads
with respect to the DDR style terminations such as 50 ohms to Vdd/2.

He showed two sets of results:

  (1) V_fixture = 0, 5 V and R_fixture = 50 ohms
  (2) V_fixture = 2.5 V, R_fixture = 50 ohms

Arpad's concern was that the results for (1) did not overlay for the
DDR termination. Also the results for (2) overlayed for the DDR termination

(same as the load), but gave bad results for 50 ohms to ground and Vdd for
both the rising and falling edges. His results were based on the HSPICE
B-element.

Scott McMorrow suggested a larger load resistance such as 100 ohms for (1)
because the voltages of the existing waveforms did not overlap center
region. Bob Ross suggested exploring Vdd/2 and 2Vdd/3 voltages with 50 ohm
loads to center the four waveform loads.

Arpad plans to send the ibis model to EDA vendors to test in their own
tools
since they may have different algorithms.

[Added note, the uploaded presentations show that Scott's and Bob's
suggestions did not produce improved results]

FINAL BUSINESS
Bob Ross reported that the next IBIS Summit Meeting is scheduled on January

28, 2002 at DesignCon2002 in Santa Clara, California. We are also working
on arrangements for an IBIS Summit Meeting on March 8, 2002 at Date 2002 in

Paris, France. The weekly IBIS Working Groups on the Connector
Specification
and on IBIS-X will continue next week.

Ed Sayre offered space at NESA to those who needed working facilities while

waiting for their return trips.

NEXT MEETING:
The next teleconference meeting will be on Friday October 5, 2001

============================================================================

                                      NOTES

IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
            [email-masked]
            Senior Hardware Engineer, Intel Corporation
            M/S JF4-215
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

VICE CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            [email-masked]
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN: Roy Leventhal (837) 797-2152, Fax: (847) 222-2799
            [email-masked]
            Senior Engineer, CommWorks Corp. (a wholly owned 3Com
            subsidiary)
            1800 W. Central Rd.
            Mt. Prospect, IL 60056-2293

WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
            [email-masked]
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
            [email-masked]
            Development Engineer, Innoveda
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  [email-masked]
      In the body, for the IBIS Open Forum Reflector:
      subscribe ibis <your e-mail address>

      In the body, for the IBIS Users' Group Reflector:
      subscribe ibis-users <your e-mail address>

      Help and other commands:
      help

  [email-masked]
      To join, change, or drop from either the IBIS Open Forum Reflector
      ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
      or both. State your request.

  [email-masked]
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  [email-masked]
      To send a message to the general IBIS Open Forum Reflector. This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements. Job posting information is not permitted.

  [email-masked]
      To send a message to the IBIS Users' Group Reflector. This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns. Job posting information is not permitted.

  [email-masked]
      To report ibischk2/3 parser bugs. The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported
      bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, and
      /pub/ibis/bugs/s2iplt/bugsplt.txt respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results. You can get on via FTP anonymous.

============================================================================

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Subject: Re: Archives
From: Ross, Bob ([email-masked])
Date: Mon Sep 24 2001 - 08:33:36 PDT

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John:

Current email archives are available under:

  http://www.eda.org/pub/ibis/users_archive

and

  http://www.eda.org/pub/ibis/email_archive

Older email archives since 1993 for the IBIS
reflector and ibis-users reflectors are under:

  http://www.eda.org/pub/ibis/email/

Bob Ross
Mentor Graphics

john austin wrote:
>
> Is there archives for the questions and responses of
> this list?
>
> Thanks
>
> __________________________________________________
> Do You Yahoo!?
> Get email alerts & NEW webcam video instant messaging with Yahoo!
Messenger. http://im.yahoo.com

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Subject: Re: Archives
From: john austin ([email-masked])
Date: Mon Sep 24 2001 - 14:37:47 PDT

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Thank You.
- --- "Ross, Bob" <[email-masked]> wrote:
> John:
>
> Current email archives are available under:
>
> http://www.eda.org/pub/ibis/users_archive
>
> and
>
> http://www.eda.org/pub/ibis/email_archive
>
>
> Older email archives since 1993 for the IBIS
> reflector and ibis-users reflectors are under:
>
> http://www.eda.org/pub/ibis/email/
>
> Bob Ross
> Mentor Graphics
>
>
>
>
> john austin wrote:
> >
> > Is there archives for the questions and responses
> of
> > this list?
> >
> > Thanks
> >
> > __________________________________________________
> > Do You Yahoo!?
> > Get email alerts & NEW webcam video instant
> messaging with Yahoo!
> Messenger. http://im.yahoo.com
>

__________________________________________________
Do You Yahoo!?
Get email alerts & NEW webcam video instant messaging with Yahoo!
Messenger. http://im.yahoo.com

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Subject: Thank you messages?
From: Muranyi, Arpad ([email-masked])
Date: Wed Sep 26 2001 - 11:13:34 PDT

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While it is a nice gesture to thank someone for the response
they wrote, it is also annoying to have to open a bunch of
meaningless messages on these reflectors (which are quite
active already as it is).

I would suggest that if someone really wants to say thanks for
the answers they got they should ONLY send it to the person
they got it from. This could reduce unnecessary network traffic
and could save some time for the rest of us...

Thanks,

Arpad Muranyi
Itel Corporation
================================================================

- -----Original Message-----
From: john austin [mailto:[email-masked]]
Sent: Monday, September 24, 2001 2:38 PM
To: Ross, Bob
Cc: [email-masked]; [email-masked]
Subject: Re: Archives

Thank You.
- --- "Ross, Bob" <[email-masked]> wrote:
> John:
>
> Current email archives are available under:
>
> http://www.eda.org/pub/ibis/users_archive
>
> and
>
> http://www.eda.org/pub/ibis/email_archive
>
>
> Older email archives since 1993 for the IBIS
> reflector and ibis-users reflectors are under:
>
> http://www.eda.org/pub/ibis/email/
>
> Bob Ross
> Mentor Graphics

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Date: Fri Sep 28 2001 - 09:13:48 PDT

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Subject: IBIS Meeting Agenda 10/5/01
From: Bob Ross ([email-masked])
Date: Fri Sep 28 2001 - 11:26:23 PDT

   * Next message: Mohanasankar Sivaprakasam: "Some clarifications reg
     IBIS3.2"
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                     IBIS Open Forum Meeting Agenda
                              for 10/5/01

                 Bridge Number Reservation # Passcode
                 1-888-316-5901 None 6159969

All meetings are 8:00 AM to 9:55 AM Pacific Time. When you call into the
meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements Peters

     - Intros of New IBIS Participants, Meeting Quorum Peters
     - Membership Update and Treasurers Report Fleming/Ross
     - Review of Previous Meeting's Minutes (and ARs) Peters
     - Miscellany/Announcements All
     - Press & Web Page Updates Huq, All
     - New Models Available, Library Update Leventhal, All
     - Opens for New Issues All

8:15 Administrative and Project Discussions

     International/External Progress
     - pr EIAJ ED-5302 Standard for I/O Interface Model
          for Integrated Circuits (IMIC) Peters
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters
     - JEDEC JC-16 Modeling and Testing Sessions
     - T10, Project 1414-DT - SCSI Signal Modeling Barnes

     PCBEAST 2001 IBIS Summit Meeting Feedback Peters/Ross

     Other Summit Meeting Plans Peters/Ross
     - DesignCon2002
     - Date2002

     IBIS Model Review Committee Ross

     Majordomo Update Angulo

     New Administrative Issues All

8:45 Technical Discussion

     Connector Proposal Report Peters/Ross

     IBIS Futures Group Report Peters/Green

     BIRD72.1 - Accommodating PMOS and NMOS/PMOS Series FET Dagostino/Ross
                Models

     BIRD73.1 - Fall Back Submodel Ross

     ibischk3 Status Ross

     XML for IBIS Ross

     New Technical Issues All

9:50 Wrap Up and Next Meetings Plans Peters

9:55 Sign Off

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Subject: Some clarifications reg IBIS3.2
From: Mohanasankar Sivaprakasam ([email-masked])
Date: Sat Sep 29 2001 - 13:29:00 PDT

   * Next message: Bob Ross: "IBIS BIRD73.1 Fall Back Submodel"
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  --------------------------------------------------------------------

Hello,
I am Mohanasankar, student at North Carolina State
University.
Can some body help me with the following:

1.What is the difference between Vinl/Vinh in [Model]
keyword and Vinl/Vinh in [Model Spec] keyword?

What different purposes do they serve?

2.I got confused with [Add Submodel]..
Is it a way of reusing models. that is using some
charcteristics of a model into another??

3.Are there any examples of models conforming to
IBIS3.2 Specifications which would cover all the
syntaxes??

Thanks for you cooperation.

Mohanasankar.

=====
"There are new problems to solve.
Engineers who can solve these problems will define the future"
Mohanasankar Sivaprakasam,
Research Assistant,
Electrical Engineering,
North Carolina State University,
Raleigh, NC,USA.

__________________________________________________
Do You Yahoo!?
Listen to your Yahoo! Mail messages from any phone.
http://phone.yahoo.com

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Subject: IBIS BIRD73.1 Fall Back Submodel
From: Bob Ross ([email-masked])
Date: Mon Oct 01 2001 - 16:55:13 PDT

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To IBIS Committee:

BIRD73.1 proposes a new Submodel_type to handle the electrical
operation of techologies which have the driver strength
reduced during a transition.

Per the AR of the August 31, 2001 IBIS Meeting, BIRD73.1 is issued
with these major revisions indicated by |** comments:

(1) An original Bus Hold example that got corrupted buy editing
    has been restored in an "unchanged section".

(2) Some miscellaneous editorial and spelling corrections were made.

In the existing Bus Hold Section:

(3) A state table has been added in the Bus Hold Section similar to the
    state table in the Fall back model section. The rule was changed to
    remove an ambiguous case.

(4) The Off_delay example has been modified to correspond to the
    Specification. The entries are by magnitude.

Bob Ross
Mentor Graphics

******************************************************************************

******************************************************************************

BIRD ID#: 73.1
ISSUE TITLE: Fall Back Submodel
REQUESTER: Bob Ross, Mentor Graphics
DATE SUBMITTED: 8-2-01, 10-1-01
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

******************************************************************************

******************************************************************************

STATEMENT OF THE ISSUE:

Existing submodels have a trigger for turning on functions. This works for
Bus_hold (and corresponding active terminators) and Dynamic_clamp
functions.

However another mechanism to turn off the submodels is needed for AVC type
devices which have the overall driver strength reduced after the output
passes through a voltage threshold value.

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

This BIRD proposes a new Submodel_type: Fall_back. The new submodel
operates
similar to the Bus_hold submodel, but with opposite action. The trigger
turns off a submodel (presumed on) when the output die voltage passes
through a trigger threshold.

Additions are noted in the relevant sections below by |* lines:

Subsequent additions which include some corrections and clarifications
in the Bus Hold section are designated by |** lines.

Comments for a new section or for unchanged sections are shown using
|**** lines.

|=============================================================================

|=============================================================================

|
| Section 6a
|
| A D D S U B M O D E L D E S C R I P T I O N
|
|=============================================================================

|=============================================================================

|
| The [Add Submodel] keyword can be used under a top-level [Model] keyword
to
| to add special-purpose functionality to the existing top-level model.
This
| section describes the structure of the top-level model and the submodel.
|
| TOP-LEVEL MODEL:
|
| When special-purpose functional detail is needed, the top-level model can

| call one or more submodels. The [Add Submodel] keyword is positioned
| after the initial set of required and optional subparameters of the
[Model]
| keyword and among the keywords under [Model].
|
| The [Add Submodel] keyword lists of name of each submodel and the
permitted
| mode (Driving, Non-Driving or All) under which each added submodel is
used.
|
| SUBMODEL:
|
| A submodel is defined using the [Submodel] keyword. It contains a subset
| of keywords and subparameters used for the [Model] keyword along with
other
| keywords and subparameters that are needed for the added functionality.
|
| The [Submodel] and [Submodel Spec] keywords are defined first since they
| are used for all submodels
|
| The only required subparameter in [Submodel] is Submodel_type to define
the
| list of submodel types. No subparameters under [Model] are permitted
under
| the [Submodel] keyword.
|
| The following set of keywords that are defined under the [Model] keyword
are
| supported by the [Submodel] keyword:
|
| [Pulldown]
| [Pullup]
| [GND Clamp]
| [POWER Clamp]
| [Ramp]
| [Rising Waveform]
| [Falling Waveform]
|
| The [Voltage Range], [Pullup Reference], [Pulldown Reference], [GND Clamp

| Reference], and [POWER Clamp Reference] keywords are not permitted. The
| voltage settings are inherited from the top-level model.
|
| These additional keywords are used only for the [Submodel] are documented

| in this section:
|
| [Submodel Spec]
| [GND Pulse Table]
| [POWER Pulse Table]
|
| The application of these keywords depends upon the Submodel_type entries
| listed below:
|
| Dynamic_clamp
| Bus_hold
|* Fall_back
|
| Permitted keywords that are not defined for any of these submodel types
are
| ignored. The rules for what set of keywords are required are found under
| the Dynamic Clamp and Bus Hold headings of this section.
|
|=============================================================================

| Keyword: [Submodel]
| Required: No
| Description: Used to define a submodel, and its attributes.
| Sub-Params: Submodel_type
| Usage Rules: Each submodel must begin with the keyword [Submodel]. The
| submodel name must match the one that is listed under an
| [Add Submodel] keyword and must not contain more than 20
| characters. A .ibs file must contain enough [Submodel]
| keywords to cover all of the model names specified under the
| [Add Submodel] keyword.
|
| Submodel_type subparameter is required and must be one of the
| following:
|
|* Dynamic_clamp, Bus_hold, Fall_back
|
| The C_comp subparameter is not permitted under the [Submodel]
| keyword. The total effective die capacitance including the
| submodel contributions are provided in the top-level model.
|
| Other Notes: The following list of keywords that are defined under the
| [Model] keyword can be used under [Submodel]: [Pulldown],
| [Pullup], [GND Clamp], [POWER Clamp], [Ramp], [Rising
| Waveform], and [Falling Waveform].
|
| The following list of additional keywords can be used:
| [Submodel Spec], [GND Pulse Table], and [POWER Pulse Table].
|-----------------------------------------------------------------------------

[Submodel] Dynamic_clamp1
Submodel_type Dynamic_clamp
|

|**** The next two section, originally shown for reference, now have some
| changes

|=============================================================================

| Keyword: [Submodel Spec]
| Required: No
| Description: The [Submodel Spec] keyword defines four columns under which

| specification and information subparameters are defined for
| submodels.
| Sub-Params: V_trigger_r, V_trigger_f, Off_delay
| Usage Rules: The [Submodel Spec] is to be used only with submodels.
|
| The following subparameters are used:
| V_trigger_r Rising edge trigger voltage
| V_trigger_f Falling edge trigger voltage
| Off_delay Turn-off delay from V_trigger_r or
| V_trigger_f
|
| For each subparameter contained in the first column, the
| remaining three hold its typical, minimum and maximum values.
| The entries of typical, minimum and maximum be must be placed
| on a single line and must be separated by at least one white
| space. All four columns are required under the [Submodel
| Spec] keyword. However, data is required only in the typical
| column. If minimum and/or maximum values are not available,
| the reserved word "NA" must be used to indicate the typical
| value by default.
|
| The values in the minimum and maximum columns usually
| correspond to the values in the same columns for the inherited
| top-level voltage range or reference voltages in the top-level
| model. The V_trigger_r and V_trigger_f subparameters should
| hold values in the minimum and maximum columns that correspond
| to the voltage range or reference voltages of the top-level
| model. The Off_delay subparameter, however, is an exception
| to this rule because in some cases it may be completely or
| or partially independent from supply voltages and/or
| manufacturing process variations. Therefore the minimum and
| maximum entries for the Off_delay subparameter should be
| ordered simply by their magnitude.
|
| Unless noted, each [Submodel Spec] subparameter is independent
| of any other subparameter.
|
| V_trigger_r, V_trigger_f rules:
|
| The voltage trigger values for the rising and falling edges
| provide the starting time when an action is initiated.
|
| Off_delay rules:
|
| The functionality of the Off_delay subparameter is to provide
| an additional time related mechanism to turn off circuit
| elements.
|
|-----------------------------------------------------------------------------

| Dynamic Clamp Example:
|
[Submodel Spec]
| Subparameter typ min max
|
V_trigger_r 3.6 2.9 4.3 | Starts power pulse table
V_trigger_f 1.4 1.2 1.6 | Starts gnd pulse table
|
| Bus Hold Example:
|
[Submodel Spec]
| Subparameter typ min max
V_trigger_r 3.1 2.4 3.7 | Starts low to high
                                                    | bus hold transition
V_trigger_f 1.8 1.6 2.0 | Starts high to low
                                                    | bus hold transition
|
| Bus_hold application with pullup structure triggered on and then clocked
off:
|
[Submodel Spec]
| Subparameter typ min max
V_trigger_r 3.1 2.4 3.7 | Low to high transition
                                                    | triggers the turn on
                                                    | process of the pullup

V_trigger_f -10.0 -10.0 -10.0 | Not used, so trigger
                                                    | voltages are set out
                                                    | of range

|** Off_delay entries are by value since they do not correlate with
process.
|** This example is corrected.

Off_delay 5n 4n 6n | Time from rising edge
                                                    | trigger at which the
                                                    | pullup turned off

|**** The Dynamic Clamp section is omitted here

|
|=============================================================================

|=============================================================================

|
| Bus Hold:
|
| When the Submodel_type subparameter under the [Submodel] keyword is set
to
| Bus_hold, the added model describes the bus hold functionality. However,
| while described in terms of bus hold functionality, active terminators
| can also be modeled.
|
| Existing keywords and subparameters are used to describe bus hold models.

| The [Pullup] and [Pulldown] tables both are used to define an internal
| buffer that is triggered switch to its opposite state. This switching
| transition is specified by a [Ramp] keyword or by the [Rising Waveform]
and
| [Falling Waveform] keywords. The usage rules for these keywords are the
| same as under the [Model] keyword. In particular, at least either the
| [Pullup] or [Pulldown] keyword is required. Also, the [Ramp] keyword is
| required, even if the [Rising Waveform] and [Falling Waveform] tables
exist.
| However, the voltage ranges and reference voltages are inherited from the

| top-level model.
|
| For bus hold submodels, the [Submodel Spec] keyword, V_trigger_r, and
| V_trigger_f are required. The Off_delay subparameter is optional, but can

| only be used if the submodel consists of a pullup or a pulldown structure

| only, and not both. Devices which have both pullup and pulldown
structures
| controlled in this fashion can be modeled using two submodels, one for
each
| half of the circuit.
|
| The transition is triggered by action at the die using the [Submodel
Spec]
| V_trigger_r and V_trigger_f subparameters as follows:
|

|** Delete this paragraph and replace with the paragraph below:

| If the starting voltage is below V_trigger_f, then the bus hold model is
set
| to the low state causing additional pulldown current. If the starting
| voltage is above V_trigger_r, the bus hold model is set to the high state

| for additional pullup current. When the input passes though V_trigger_f
| during a high-to-low transition at the die, the bus hold output switches
to
| the low state. Similarly, when the input passes though V_trigger_r during

| a low-to-high transition at the die, the bus hold output switches to the
| high state.
|
|** End of Deleted Paragraph and begin of replacement paragraph:

| The starting state for each submodel that does not have the Off_delay
| subparameter is determined by the starting state of the driver in the
| circuit being analyzed. If the driver state is low, then all bus hold
| submodels in the circuit are set to low. If the driver state is high,
then
| all bus hold submodels in the circuit are set to high. Normally, the bus
| hold submodel adds current in a direction that holds the circuit at the
| given state. When the input passes though V_trigger_f
| during a high-to-low transition at the die, the bus hold output switches
to
| the low state. Similarly, when the input passes though V_trigger_r during

| a low-to-high transition at the die, the bus hold output switches to the
| high state.

|** End of replacement paragraph

| If the bus hold submodel has a pullup structure only, V_trigger_r
provides
| the time when its pullup is turned on and V_trigger_f or Off_delay
provides
| the time when it is turned off, whichever occurs first. Similarly, if the

| submodel has a pulldown structure only, V_trigger_f provides the time
when
| its pulldown is turned on and V_trigger_r or Off_delay provides the time
| when it is turned off, whichever occurs first. The required V_trigger_r
| and V_trigger_f voltage entries can be set to values outside of the input

| signal range if the pullup or pulldown structures are to be held on until

| the Off_delay turns them off.
|
| The starting mode for each of the submodels which include the Off_delay
| subparameter of the [Submodel Spec] keyword is the off state. Also, while

| two submodels provide the desired operation, either of the submodels may
| exist without the other to simulate turning on and off only a pullup or a

| pulldown current.
|

|** The following Tables are added:

| The following tables summarizes the bus hold initial and switching
| transitions:
|
| BUS HOLD WITHOUT OFF_DELAY:
|
| Initialization:
|
| Initial Driving Initial Bus Hold
| Buffer State Submodel State
| --------------- ----------------
| low low
| high high
|
| Transitions:
|
| Prior Bus Hold Vdie transition Bus Hold
| Submodel State through Transition
| V_trigger_r/f
| -------------- --------------- -----------
| low V_trigger_r low-to-high
| low V_trigger_f no change
| high V_trigger_r no change
| high V_trigger_f high-to-low
|
| BUS HOLD WITH OFF_DELAY (REQUIRES EITHER [PULLUP] or [PULLDOWN] ONLY):
|
| Initialization:
|
| [Pullup] or Initial Bus Hold
| [Pulldown] Submodel State (Off mode)
| Driver Table
| ------------ -------------------------
| [Pullup] high
| [Pulldown] low
|
| Transitions:
|
| Prior Bus Hold Vdie transition Bus Hold Off_delay
| Submodel State through Transition Transition
| V_trigger_r/f
| -------------- --------------- ----------- -----------
| low V_trigger_r low-to-high high-to-low
| low V_trigger_f no change no change
| high V_trigger_r no change no change
| high V_trigger_f high-to-low low-to-high
|
| Note, if Vdie passes again through the V_trigger_r/f thresholds
| before the Off_delay time is reached, the Bus hold state follows the
| change documented in the first table, overriding the Off_delay
| transition
|

|** End of Added Tables

| No additional keywords are needed for this functionality.
|-----------------------------------------------------------------------------

|
| Complete Bus Hold Model Example:
|
[Submodel] Bus_hold_1
Submodel_type Bus_hold
|
[Submodel Spec]
| Subparameter typ min max
|
V_trigger_f 1.3 1.2 1.4 | Falling edge trigger
V_trigger_r 3.1 2.6 4.6 | Rising edge trigger
|
| typ min max
| [Voltage Range] 5.0 4.5 5.5
| Note, the actual voltage range and reference voltages are inherited from
| the top-level model.
|
[Pulldown]
|
- -5V -100uA -80uA -120uA
- -1V -30uA -25uA -40uA
0V 0 0 0
1V 30uA 25uA 40uA
3V 50uA 45uA 50uA
5V 100uA 80uA 120uA
10v 120uA 90uA 150uA
|
[Pullup]
|
- -5V 100uA 80uA 120uA
- -1V 30uA 25uA 40uA
0V 0 0 0
1V -30uA -25uA -40uA
3V -50uA -45uA -50uA
5V -100uA -80uA -120uA
10v -120uA -90uA -150uA
|
|-----------------------------------------------------------------------------

|
[Ramp]
| typ min max
dV/dt_r 2.0/0.50n 2.0/0.75n 2.0/0.35n
dV/dt_f 2.0/0.50n 2.0/0.75n 2.0/0.35n
R_load = 500
|
|-----------------------------------------------------------------------------

|** This example was corrupted in BIRD73 and has been restored to the
|** original Version 3.2 form

|
| Complete Pullup Timed Latch Example:
|
[Submodel] Timed_pullup_latch
Submodel_type Bus_hold
|
[Submodel Spec]
| Subparameter typ min max
|
V_trigger_r 3.1 2.6 4.6 | Rising edge trigger
                                                     | Values could be set
out
                                                     | of range to disable
the
                                                     | trigger
V_trigger_f 1.3 1.2 1.4 | Falling edge trigger

|** Off_delay entries are by value since they do not correlate with
process.
|** This example is corrected.

Off_delay 3n 2n 5n | Delay to turn off the
                                                     | pullup table
|
| Note that if the input signal goes above the V_trigger_r value, the
| pulldown structure will turn off even if the timer didn't expire yet.
|
| typ min max
| [Voltage Range] 5.0 4.5 5.5
| Note, the actual voltage range and reference voltages are inherited from
| the top-level model.
|
[Pulldown]
|
- -5V -100uA -80uA -120uA
- -1V -30uA -25uA -40uA
0V 0 0 0
1V 30uA 25uA 40uA
3V 50uA 45uA 50uA
5V 100uA 80uA 120uA
10v 120uA 90uA 150uA
|
| [Pullup] table is omitted to signal Open_source functionality
|
|-----------------------------------------------------------------------------

|
[Ramp]
| typ min max
dV/dt_r 2.0/0.50n 2.0/0.75n 2.0/0.35n
dV/dt_f 2.0/0.50n 2.0/0.75n 2.0/0.35n
R_load = 500
|
|=============================================================================

|**** End of existing Sections that now have some changes

|**** This section is added:

|=============================================================================

|=============================================================================

|
| Fall Back:
|
| When the Submodel_type subparameter under the [Submodel] keyword is set
to
| Fall_back, the added model describes the fall back functionality. This
| submodel can be used to model drivers that reduce their strengths and
| increase their output impedances during their transitions. The fall back
| function can be considered opposite of the bus hold function, but there
|** are some details that are unique.
|
| Existing keywords and subparameters are used to describe fall back
models.
| The [Pullup] and [Pulldown] tables both are used to define an internal
| buffer that is triggered switch to its opposite state. This switching
| transition is specified by a [Ramp] keyword or by the [Rising Waveform]
and
| [Falling Waveform] keywords. The usage rules for these keywords are the
| same as under the [Model] keyword. In particular, at least either the
| [Pullup] or [Pulldown] keyword is required. Also, the [Ramp] keyword is
| required, even if the [Rising Waveform] and [Falling Waveform] tables
exist.
| However, the voltage ranges and reference voltages are inherited from the

| top-level model.
|
| For fallback submodels, the [Submodel Spec] keyword, V_trigger_r, and
| V_trigger_f are required. Unlike the bus hold model, the Off_delay
| subparameter is not permitted. Devices which have both pullup and
pulldown
| structures can be modeled using two submodels, one for the rising cycle
| and one for the falling cycle.
|
| The transition is triggered by action at the die using the [Submodel
Spec]
| V_trigger_r and V_trigger_f subparameters as follows:
|
| SIMULATOR RISING CYCLE:
|
| Prior Vdie Rising Edge Vdie > V_trigger_r
| State Transition Transition
|** ----------- ------------- ------------- ------------------
| low/initial <= V_trigger_r low-to-high high-to-low
| > V_trigger_r set/stays low stays low
|
| high <= V_trigger_r stays high high-to-low
| > V_trigger_r high-to-low stays low
|
| SIMULATOR FALLING CYCLE:
|
| Prior Vdie Falling Edge Vdie < V_trigger_f
| State Transition Transition
|** ----------- ------------- ------------- ------------------
| high/initial => V_trigger_f high-to-low low-to-high
| < V_trigger_f set/stays high stays high
|
| low <= V_trigger_f stays low high-to-low
| > V_trigger_f low-to-high stays high
|
|** The prior state of "initial" describes the initial setting for the
first
| simulator edge encountered, either RISING or FALLING. After that the
| prior state is tracked.
|
|** One application is to configure the submodel with only one pullup
    structure.
| At the beginning of the rising edge cycle, the pullup is turned on to the

| high state. When the die voltage passes V_trigger_r, the pullup structure

| is turned off. Because only the pullup structure is used, the off state
is
| the same as a high-Z state. During the falling transition, the pullup
| remains in the high-Z state. The V_trigger_f is set out of range, so no
|** further change of state occurs. With this approach, the overall rising
| transition starts by turning the fall back submodel turned on. This
| submodel is triggered to drop out after the output die voltage passes a
| trigger voltage, and it remains off until the next rising transition is
| initiated.
|
| A similar submodel consisting of only a pulldown structure could be
| constructed to provide added drive strength only at the beginning of the
| falling cycle. The complete IBIS model would have both submodels to give
| added drive strength for both the start of the rising and the start of
the
| falling cycles.
|
| No additional keywords are needed for this functionality.
|-----------------------------------------------------------------------------

|
| Complete Dynamic Output Model Example Using Two Submodels:
|
[Submodel] Dynamic_Output_r
Submodel_type Fall_back
|
[Submodel Spec]
| Subparameter typ min max
|
V_trigger_f -10.0 -10.0 -10.0 | Falling edge trigger
                                                     | set out of range to
                                                     | disable trigger
V_trigger_r 3.1 2.6 4.6 | Rising edge trigger
|
| typ min max
| [Voltage Range] 5.0 4.5 5.5
| Note, the actual voltage range and reference voltages are inherited from
| the top-level model.
|
[Pullup]
|
- -5V 100mA 80mA 120mA
0V 0 0 0
10v -200mA -160mA -240mA
|
| [Pulldown] table omitted to signify an Open_source Submodel.
|
|-----------------------------------------------------------------------------

|
[Ramp]
| typ min max
dV/dt_r 1.5/0.50n 1.43/0.75n 1.58/0.35n
dV/dt_f 1.5/0.50n 1.43/0.75n 1.58/0.35n
R_load = 50
|
|-----------------------------------------------------------------------------

|
[Submodel] Dynamic_Output_f
Submodel_type Fall_back
|
[Submodel Spec]
| Subparameter typ min max
|
V_trigger_r 10.0 10.0 10.0 | Rising edge trigger
                                                     | set out of range to
                                                     | disable trigger
V_trigger_f 1.3 1.2 1.4 | Falling edge trigger
|
| typ min max
| [Voltage Range] 5.0 4.5 5.5
| Note, the actual voltage range and reference voltages are inherited from
| the top-level model.
|
[Pulldown]
|
- -5V -100mA -80mA -120mA
0V 0 0 0
10v 200mA 160mA 240mA
|
| [Pullup] table omitted to signify an Open_drain Submodel.
|
|-----------------------------------------------------------------------------

|
[Ramp]
| typ min max
dV/dt_r 1.5/0.50n 1.43/0.75n 1.58/0.35n
dV/dt_f 1.5/0.50n 1.43/0.75n 1.58/0.35n
R_load = 50
|
|-----------------------------------------------------------------------------

******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

The AVC technology is structured using various trade marked terms such as
Dynamic Output Control(tm), Dynamic Control Output(tm), etc. They are
designed to operate by starting at full strength, but finishing at a
reduced
strength (higher impedance) when the output voltage passes through a
trigger
voltage. The final higher impedance usually matches better the load (such
as
a transmission line equivalent circuit of the printed circuit board trace)
to
produce better signal integrity matching conditions.

The operation is opposite of the Bus_hold submodel which is triggered to
turn on when the die voltage passes a threshold voltage. So a bus hold
structure cannot be configured or modified to produce this "fall back"
effect.

BIRD73 proposes a new submodel which mimics the opposite effect. The main
idea is that when the output voltage passes a trigger voltage, a rising
transition buffer changed to a falling transition, and a falling transition

buffer is changed to a rising transition. The two existing [Submodel]
subparameters V_trigger_r and V_trigger_f are used for the fall back
operation.

Unlike the bus hold submodel, the rules for setting the initial state are
more complicated. Furthermore, prior history or conditions could already
nullify some transitions. Within a simulator rising edge cycle, 0, 1 or 2
transitions are possible. One can be initiated at the start of the cycle,
and the other initiated when the output voltage passes V_trigger_r. Several

initialization and switching conditions exist, and a table is used to
document the allowable fixed and transition states:

SIMULATOR RISING CYCLE:

  Prior Vdie Rising Edge Vdie > V_trigger_r
  State Transition Transition

  low/none <= V_trigger_r low-to-high high-to-low
> V_trigger_r Set/stays low Stays low

  high <= V_trigger_r Stays high high-to-low
> V_trigger_r high-to-low Stays low

SIMULATOR FALLING CYCLE:

  Prior Vdie Falling Edge Vdie < V_trigger_f
  State Transition Transition

  high/none => V_trigger_f high-to-low low-to-high
                < V_trigger_f Set/stays high Stays high

  low <= V_trigger_f Stays low high-to-low
> V_trigger_f low-to-high Stays high

The prior state of "none" describes the initial setting for the first
simulator edge encountered, either RISING or FALLING. After that the
prior state is tracked.

The number of transitions for each simulator cycle is limited to two or
less.
It might be possible to connect several fall back and bus hold submodels in

a manner and with different V_trigger_r and V_trigger_f values to work
against each other to cause the Vdie to move above and below the
V_trigger_*
values several times within a cycle. There does not appear to be any
practical reason to make the above state and transition tables more
complicated to account for opposite direction movement (or oscillation)
around V_trigger_*. So after the RISING or FALLLING transitions are
initiated, some states are simply held constant regardless of potential
oscillations. Such fixed stated are defined by "Stays high" or "Stays low".

The rules are set to work in a manner consistent with the bus hold
submodel.
However, Off_delay subparameter is not supported here. Nor is the opposite
acting subparameter proposed that might be called "Off_delay" that might
add one more transition reversal after a V_trigger_* transition. There does

not appear to be any practical need for such an extension which would add
complication to the state and transition conditions above.

While a complete set of states and transitions are defined, the most
practical implementation for AVC technology is intended to be done with
adding two submodels, one with only a [Pullup] table for rising edge
impedance control, and one with only a [Pulldown] table for falling edge
impedance control. With this setup, the corresponding "off" states will
be high-Z making each submodel function independently for each edge only
to increase the impedance of the final state of the buffer. As in other
submodels, letting the V_trigger_* values to be set out of range is used
to keep the off state of the submodel in the high-Z mode. This is shown
in an example.

The need for providing the new functionality currently exists and is
proposed
for IBIS Version 4.0 as a shorter term solution. BIRD73 also provides the
basis for considering a more advanced solution that could be achieved using

a proposed IBIS-X Macro language. This later solution could also provide
more
detail and a superset of what is currently practical for Version 4.0.

BIRD73.1 has the following corrections based on the August 31, 2001
meeting.

(1) An original Bus Hold example that got corrupted buy editing
    has been restored in an "unchanged section".

(2) Some miscellaneous editorial and spelling corrections were made.

In the existing Bus Hold Section:

(3) A state table has been added in the Bus Hold Section similar to the
    state table in the Fall back model section. The rule was changed to
    remove an ambiguous case.

(4) The Off_delay example has been modified to correspond to the
    Specification. The entries are by magnitude.

The original rule regarding (3) did not take into account that it is
possible
for the initial voltage to not be above V_trigger_r or below V_trigger_f
under some terminated nets. The initial voltage could fall in between these

two trigger thresholds. This left an ambiguous initial condition setting.
The rule was changed to simply set the bus hold submodels to be the same as

the initial setting of the driver of the circuit. This rule is consistent
with the original rule, but now clarifies what happens for the ambiguous
condition.

The formatting of the tables was changed for clarity. The initial state
"none" in BIRD73 was changed to "initial" in the added section for fall
back
submodels.

******************************************************************************

ANY OTHER BACKGROUND INFORMATION:

******************************************************************************

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