Subject: ibis V1 #3
From: owner-ibis@ (ibis)
To: [email-masked]

ibis             Friday, October 19 2001             Volume 01 : Number 003

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Subject: Re: Some clarifications reg IBIS3.2
From: Bob Ross ([email-masked])
Date: Mon Oct 01 2001 - 17:50:56 PDT

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Hello:

Some brief responses are in your text.

Bob Ross
Mentor Graphics

Mohanasankar Sivaprakasam wrote:
>
> Hello,
> I am Mohanasankar, student at North Carolina State
> University.
> Can some body help me with the following:
>
> 1.What is the difference between Vinl/Vinh in [Model]
> keyword and Vinl/Vinh in [Model Spec] keyword?>
> What different purposes do they serve?
>

The [Model Spec] Vinh/l subparamters allow you to specify min
and max values that may change with [Voltage Range] or some
other reference voltage. PECL technology is an example
where this would be important. Vinh/l subparameter of
[Model] only allows fixed values over the entire range.

The [Model Spec] values always override the [Model]
subparameter specification.

> 2.I got confused with [Add Submodel]..
> Is it a way of reusing models. that is using some
> charcteristics of a model into another??

Some technologies add some functional details to
the buffer. The [Add Submodel] and [Submodel]
keywords provide a way to "add" on some detail
that is of practical interest.

>
> 3.Are there any examples of models conforming to
> IBIS3.2 Specifications which would cover all the
> syntaxes??

There exists some examples that demonostrate some
of the Version 3.2 syntax under

  http://www.eda.org/pub/ibis/samples/

for subdirectories ver3.0 and above.

Bob Ross
Mentor Graphics

>
> Thanks for you cooperation.
>
> Mohanasankar.
>
> =====
> "There are new problems to solve.
> Engineers who can solve these problems will define the future"
> Mohanasankar Sivaprakasam,
> Research Assistant,
> Electrical Engineering,
> North Carolina State University,
> Raleigh, NC,USA.
>
> __________________________________________________
> Do You Yahoo!?
> Listen to your Yahoo! Mail messages from any phone.
> http://phone.yahoo.com

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Subject: IBIS BIRD72.1 ... Series FET Models
From: Bob Ross ([email-masked])
Date: Wed Oct 03 2001 - 09:39:52 PDT

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To IBIS Committee

BIRD72.1 by Tom Dagostino is issued with some corrections suggested at
the August 31, 2001 IBIS meeting.

Some corrections are editorial and reorganization. The new corrections
are noted by |** lines.

An example taken from real measurements are added.

Bob Ross

******************************************************************************

******************************************************************************

BIRD ID#: 72.1
ISSUE TITLE: Accommodating PMOS and NMOS//PMOS Series FET Models
REQUESTER: Tom Dagostino, Mentor Graphics
DATE SUBMITTED: 7-26-01, 10-3-01
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

******************************************************************************

******************************************************************************

STATEMENT OF THE ISSUE:

The IBIS FET Bus Switch model assumes a series NMOS FET which has its gate
tied to Vdd. We have come across two other topologies for the FET switches,

specifically:

1. What appears to be a PMOS device with it's gate tied to ground
2. Parallel NMOS and PMOS devices with gates respectively tied to Vdd and
   ground.

The IBIS Golden Parser produces warnings and errors with models that
describe
this behavior.

******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

These models cause issues with the IBIS Golden Parser and, depending on
assumptions in the simulator's implementations that support the bus switch,

analysis issues.

For the single PMOS case:

The parser is set up to see increasing current as Vgs increase where Vgs is

defined as Vcc - Vsource. Given this definition for Vgs the current Id will

decrease as 'Vgs' increases for the PMOS device with its gate to ground.
The
parser gives an error of decreasing current as 'Vgs' increases.

Simulators may make the assumption the FET is a NMOS device and may not
handle
the characteristics properly if the model gets parsed in.

For the dual PMOS/NMOS case:

In the case of the dual PMOS/NMOS topology the currents through the
parallel
FET's will sum and produce an Id curve that:

- -- starts with significant current at 'Vgs' = 0 (current is flowing through

the PMOS device)

- -- decreases by 10 to 90% at about 40% of 'Vgs' range where both the PMOS
and
NMOS devices are both on

- -- increases to a larger value at 'Vgs' = Vdd than at 'Vgs" = 0. This is
where the NMOS device is fully on

This characteristic has been observed in several devices. This will cause a

non-monotonic warning from the parser.

It is not known how all simulators will handle this non-monotonic behavior.

In general the simulators should be able to handle these characteristics.
The IV curves define the device's characteristics and the simulator should
just work with that definition.

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

The following changes are proposed:

The definition of Voltage in the IV table changes. Vgs has been Vcc -
Vsource
assuming the gate was tied to Vcc. IBIS should now assume the voltage in
the
IV table is really Vcc minus the FET's source voltage (Voltage = Vcc -
Vsource). This makes old models compatible and no change in the model
format
is required.

Decreasing current vs. Voltage are allowed.

Non-monotonic currents in the table are expected in the parallel case but
warnings can still be issued. It may be useful to have the modeler note the

type of switch in the model so the user can better understand any
non-monotonic issues.

******************************************************************************

Changes and additions to the IBIS Specification are shown by the |* lines

|=============================================================================

| Keyword: [Series MOSFET]
| Required: Yes, for series MOSFET switches
| Description: The data points under this keyword define the I-V tables for

| voltages measured at Pin 2 for a given Vds setting. Currents
| are considered positive if they flow into Pin 1. Pins 1 and
| 2 are listed under the [Series Pin Mapping] keyword under
| [Series Pin Mapping] and pin_2 columns, respectively.
| Sub-Params: Vds
| Usage Rules: The first column contains the voltage value, and the three
| remaining columns hold the typical, minimum, and maximum
| current values. The four entries, Voltage, I(typ), I(min),
| and I(max) must be placed on a single line and must be
| separated by at least one white space.
|
| All four columns are required under these keywords. However,
| data is only required in the typical column. If minimum
| and/or maximum current values are not available, the reserved
| word "NA" must be used. "NA" can be used for currents in the
| typical column, but numeric values MUST be specified for the
| first and last voltage points on any I-V table. Each I-V
| table must have at least 2, but not more than 100, voltage
| points.
|
| Other Notes: There is no monotonicity requirement. However the model
| supplier should realize that it may not be possible to derive
| a behavioral model from non-monotonic data.
|
|** Delete this Diagram

| The model is:
|
| Table Current
| ------->
| + Vds -
| Pin 1 Pin 2
| <---| |---> +
| d |_____| - s
| --+-- Vgs Vs
| | g +
| -
| Vg = [Voltage Range] = Vcc
| Vgs = Table Voltage = Vtable = Vcc - Vs
| Ids = Table Current for a given Vcc and Vds
|

|** Replace with this Diagram and Text:

|*
|* Table Current
|* -------> Ids
|* + Vds -
|*
|* Vcc
|* | g
|* * --+--
|* ------- NMOS
|* Pin 1 | | Pin 2
|** <---| |---> + Voltage = Vcc - Vs
|* d |_____| s
|** PMOS --+-- Vs
|* | g
|** GND -
|*
|** Either of the FET's could be removed (or have zero current
|** contribution. Thus this model covers all four conditions, off,
|** single NMOS, single PMOS and parallel NMOS/PMOS.
|*
|* Voltage = Table Voltage = Vtable = Vcc - Vs
|* Ids = Table Current for a given Vcc and Vds
|
|** End of Addition

|** Delete these Sentences:
|**
| Internal logic that is generally referenced to the power rail
| is used to set the MOSFET switch to its 'On' state. Thus the
| [Voltage Range] settings provide the assumed gate voltages.
| If the [POWER Clamp Reference] exists, it overrides the
| [Voltage Range] value. The table entries are actually the Vgs
| values referenced to the power rail. The polarity conventions
|

|** Add these Sentences:

|* Internal Logic that is generally referenced to the power rail
|* is used to set the NMOS MOSFET switch to its 'ON' state.
|* Internal logic likewise referenced to ground is used to set the
|* PMOS device to its 'ON' state if the PMOS device is present.
|* Thus the [Voltage Range] settings provide the assumed
|* gate voltages. If the [POWER Clamp Reference] exists, it
|* overrides the [Voltage Range] value. The table entries are
|* actually Vgs of the NMOS device and Vcc - Vgs of the PMOS
!* device if present. The polarity conventions

|** End of Addition

| are identical with those used for other tables that are
| referenced to power rails. Thus the voltage column can be
| viewed as a table defining the source voltages Vs according to
| the convention: Vtable = Vcc - Vs.
|
| If the switch is used in an application such as interfacing
| between 3.3 V and 5.0 V logic, the Vcc may be biased at a
| voltage (such as 4.3 V) that is different from a power rail
| voltage (such as 5.0 V) used to create the model. Just
| readjust the [Voltage Range] entries (or [POWER Clamp
| Reference] entries).
|
| One fundamental assumption in the MOSFET switch model is that
| it operates in a symmetrical manner. The tables and
| expressions are given assuming that Vd >= Vs. If Vd < Vs,
| then apply the same relationships under the assumption that
| the source and drain nodes are interchanged. A consequence of
| this assumption is that the Vds subparameter is constrained to
| values Vds > 0. It is assumed that with Vds = 0 the currents
| will be 0 mA. A further consequence of this assumption that
| would be embedded in the analysis process is that the voltage
| table is based on the side of the model with the lowest
| voltage (and that side is defined as the source). Thus the
| analysis must allow current to flow in both directions, as
| would occur due to reflections when the switch is connected in
| series with an unterminated transmission line.
|
| The model data is used to create an On state relationship
| between the actual drain to source current, ids, and the
| actual drain to source voltage, vds:
|
| ids = f(vds).
|
| This functional relationship depends on the actual source
| voltage Vs and can be expressed in terms of the corresponding
| table currents associated with Vs (and expressed as a function
| of Vgs).
|
| If only one [Series MOSFET] table is supplied (as a first
| order approximation), the functional relationship is assumed
| to be linearly related to the table drain to source current,
| Ids, for the given Vds subparameter value and located at the
| existing gate to source voltage value Vgs. This table current
| is denoted as Ids(Vgs, Vds). The functional relationship
| becomes:
|

|** Delete this Equation
| ids = Ids(Vgs, Vds) * vds / Vds.
|*

|** Add This Equation:

|** ids = Idsn(Vtable, Vds) * vds/Vds +
|** Idsp((Vcc - Vtable), Vds) * vds/Vds
|
|** End of Addition

| More than one [Series MOSFET] table is permitted, but it is
| simulator dependent how the data will be used. Each
| successive [Series MOSFET] table must have a different
| subparameter value for Vds. The number of tables must not
| exceed 100.
|
| C_comp values are ignored for [Series MOSFET] models.
|-----------------------------------------------------------------------------

|** An NMOS Example
|**
[On]
[Series MOSFET]
Vds = 1.0
| Voltage I(typ) I(min) I(max)
    5.0V 257.9m 153.3m 399.5m | Defines the Ids current as a
    4.0V 203.0m 119.4m 317.3m | function of Vgs, for Vds = 1.0
    3.0V 129.8m 74.7m 205.6m
    2.0V 31.2m 16.6m 51.0m
    1.0V 52.7p 46.7p 56.7p
    0.0V 0.0p 0.0p 0.0p
|

|** A PMOS/NMOS Example
|**
[On]
[Series MOSFET]
Vds = 0.5
| Voltage I(typ) I(min) I(max)
0.0 48.6ma NA NA
0.1 47.7ma NA NA
0.2 46.5ma NA NA
0.3 46.1ma NA NA
0.4 45.3ma NA NA
0.5 44.4ma NA NA
0.6 42.9ma NA NA
0.7 42.3ma NA NA
0.8 41.2ma NA NA
0.9 39.7ma NA NA
1.0 38.6ma NA NA
1.1 38.1ma NA NA
1.2 38.6ma NA NA
1.3 40.7ma NA NA
1.4 45.0ma NA NA
1.5 49.2ma NA NA
1.6 52.3ma NA NA
1.7 55.1ma NA NA
1.8 57.7ma NA NA
1.9 58.8ma NA NA
2.0 58.9ma NA NA
2.1 59.2ma NA NA
2.2 59.3ma NA NA
2.3 59.4ma NA NA
2.4 59.8ma NA NA
2.5 60.1ma NA NA
2.6 61.8ma NA NA
2.7 62.3ma NA NA
2.8 63.4ma NA NA
2.9 64.4ma NA NA
3.0 65.3ma NA NA
3.1 66.0ma NA NA
3.2 66.8ma NA NA
3.3 68.2ma NA NA
|
|=============================================================================

******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

These models cause issues with the IBIS Golden Parser and, depending on
assumptions in the simulator's implementations that support the bus switch,

analysis issues.

For the single PMOS case:

The parser is set up to see increasing current as Vgs increase where Vgs is

defined as Vcc - Vsource. Given this definition for Vgs the current Id will

decrease as 'Vgs' increases for the PMOS device with its gate to ground.
The
parser gives an error of decreasing current as 'Vgs' increases.

Simulators may make the assumption the FET is a NMOS device and may not
handle
the characteristics properly if the model gets parsed in.

For the dual PMOS/NMOS case:

In the case of the dual PMOS/NMOS topology the currents through the
parallel
FET's will sum and produce an Id curve that:

- -- starts with significant current at 'Vgs' = 0 (current is flowing through

the PMOS device)

- -- decreases by 10 to 90% at about 40% of 'Vgs' range where both the PMOS
and
NMOS devices are both on

- -- increases to a larger value at 'Vgs' = Vdd than at 'Vgs" = 0. This is
where the NMOS device is fully on

This characteristic has been observed in several devices. This will cause a

non-monotonic warning from the parser.

It is not known how all simulators will handle this non-monotonic behavior.

In general the simulators should be able to handle these characteristics.
The IV curves define the device's characteristics and the simulator should
just work with that definition.

BIRD72.1 has some editorial revisions including moving this section from
the
beginning to this location. A new example is added showing PMOS//NMOS
data.

******************************************************************************

ANY OTHER BACKGROUND INFORMATION:

An Ad Hoc presentation on this topic was initially presented at the IBIS
Summit Meeting on June 21, 2001.

******************************************************************************

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Subject: IBIS BIRD73.1 Correction for Fall Back Submodel
From: Bob Ross ([email-masked])
Date: Wed Oct 03 2001 - 09:49:59 PDT

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To All:

One table in BIRD73.1 for BUS HOLD should be corrected as shown
below (low and high changed):

| BUS HOLD WITH OFF_DELAY (REQUIRES EITHER [PULLUP] or [PULLDOWN] ONLY):
|
| Initialization:
|
| [Pullup] or Initial Bus Hold
| [Pulldown] Submodel State (Off mode)
| Driver Table
| ------------ -------------------------
| [Pullup] low
| [Pulldown] high
|

Bob Ross
Mentor Graphics

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Subject: EIA IBIS Open Forum Meeting Minutes
From: Guy de Burgh ([email-masked])
Date: Mon Oct 08 2001 - 17:42:56 PDT

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DATE: 10/8/01

SUBJECT: October 5, 2001 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2001 PARTICIPANTS LIST:
3Com (& CommWorks) Roy Leventhal
Ansoft Corporation (Eric Bracken)
Apple Computer John Figueroa
Applied Simulation Technology [Raj Raghuram], Norio Matsui,
                               Fred Balistreri
Avanti (Chen Hongyu)
Cadence Design [Ian Dodd], Patrick Dos Santos, Heiko Dudek,
                               Lynne Green*, Lance Wang
Cisco Systems Syed Huq, Lungfu Chen
Cypress Semiconductor (Rajesh Manapat)
EMC Corporation Brian Arsenault, Jinhua Chen
Fairchild Semiconductor Adam Tambone
Huawei Technologies Rachild Chen
IBM Michael Cohen, Greg Edlund, Wes Martin,
                               Yeon-Chang Hahm, Bill DeVey, Pravin Patel
Innoveda (& HyperLynx) Guy de Burgh*, John Angulo*, Cary Mandel,
                               Matthew Flora, Steve Kaufer
Intel Corporation Stephen Peters*, Arpad Muranyi*,
                               Dave Lorang, Michael Mirmak, Qinglun Chen,
                               Will Hobbs, Wei-hsing Huang
LSI Logic Larry Barnes
Mentor Graphics Bob Ross*, Tom Dagostino*, Chris Reid,
                               Mike Donnelly*, Hazem Hegazy, Tony Dunbar,
                               Griff Derryberry, Dan Lake, Sherif Hammad,
                               Mohammed Korany, Weston Beal, Chris Swaim,
                               Ali Samii, Eric Ronger, Karine Loudet,
                               Daisaku Shiga, Kenji Kushima, Ian Dodd
Micron Technology Randy Wolff*, Yong Phan*, Tim Wells*
Mitsubishi Pat Hefferan
Molex Incorporated Gus Panella, Brian O'Malley
Motorola (Rick Kingen)
National Semiconductor Milt Schwartz*
NEC Corporation (Akimoto Tetsuya)
North East Systems Associates Edward Sayre
Philips Semiconductor Zack Ciccone, Rob Mataheroe
Quantic EMC (Mike Ventham)
Siemens (& Automotive) AG Bernhard Unger, Helmut Katzier,
                               Katja Koller, Wolfram Meyer, Eckhard Lenski,

                               Gerald Bannert, Burkhard Muller,
                               Christian Marot, Manfred Maurer,
                               Amir Motamedi, Hans Pichlmaier
Signal Integrity Software Douglas Burns, Barry Katz, Walter Katz
Sigrity Raj Raghuram, Winson Yu
SiQual Scott McMorrow, Rob Hinz, Bernard Voss,
                               Chris Brewster
Texas Instruments Thomas Fisher, Stephen Nolan, Ramzi Ammar,
                               Jean Claude Perrin, Moshiul Haque
Time Domain Analysis Systems Dima Smolyansky, Steve Corey
Tyco Electronics (Russell Moser)
Via Technologies (Weber Chuang)
Zuken (& Incases) John Berrie, Ralf Bruening

OTHER PARTICIPANTS IN 2001:
Actel Corporation Silvia Montoya
Acuson Kim Helliwell
AMCC Jeff Smith
ASIS Ltd David Wright
Brocade Communications Robert Badal
BMW Friedrich Hasinger
Cereva Networks Bob Haller
Compaq [Peter LaFlamme], Ron Bellomio, Quang Dam,
                               Bill Ham
EADS Airbus Industry Claude Huet
  (Aerospatiale)
EFM Ekkehard Miersch, Horle Raines
EIA Cecilia Fleming
Ericsson Radio Systems Anders Ekholm
FCI Sercu Stefaan
Foundary Networks Bertram Chan
Framatom Conectors Danny Morlion
Fraunhofer Institute Mariusz Faferko, Peter Kralicek
  Reliability and
  Integration
Fujitsu Ltd Tadashi Arai, Takeshi Murakami
Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt
Hyundai Electronics Jongho Kang
Idaho State University Al Davis
Infineon Technologies Christian Sporrer
Intrinsix Corporation Steven Chin
KAW/USA Shinichi Maeda
National Institute of Applied Etienne Sicard
  Science (INSA)
Nokia Tapani von Ravner, Mika Castren,
                               Janne Uusitalo
North Carolina State U. Paul Franzon
Nortel Networks Calvin Trowell
Oak Technology Darmin Jin
Plexus Technology Group Joseph Socha
Sintecs Hans Klos
STMicroelectronics Peter Hirt, Fabrice Boissieres
Sun Adrian Udenze
Toshiba Corp. Hirokaza Kato, Yuichi Koga, Toshio Sudo
Xilinx Susan Wu

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings: The bridge numbers for future IBIS teleconferences are
as follows:

  Date Bridge Number Reservation # Passcode
  October 26, 2001 1-916-356-2663 3 0776283

All meetings are 8:00 AM to 9:55 AM Pacific Time. We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after. When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES
- -----------------------------------

INTRODUCTIONS AND MEETING QUORUM
Tim Wells from Micron Technology is developing IBIS, EBD and Spice models
and is interested in learning more about IBIS.

MEMBERSHIP UPDATE AND TREASURER'S REPORT
Stephen Peters reported that Motorola and Siemens have rejoined and NEC has

joined the IBIS Open Forum. This increases the voting membership to 34.

Stephen reported that we are reviewing the budget for 2002.

REVIEW OF MINUTES AND AR'S
The August 31, 2001 IBIS Minutes were approved without change. The
September 13, 2001 IBIS Summit Meeting Minutes were approved without
change.

The ARs were discussed during the meeting.

MISCELLANY/ANNOUNCEMENTS
None

PRESS AND WEB PAGE UPDATES
Stephen Peters reported that Roy Leventhal updated the IBIS Models page as
of September 6 and 12, 2001.

Bob Ross noted that Syed Huq and Cecilia Fleming updated the Support link
for the IBIS Model Review Committee, the Roster link and will update the
Upcoming Events Link.

NEW MODELS AVAILABLE, LIBRARY UPDATE
Bob Ross reported that IBIS models can be found by searching for IBIS under

PLX Technology:

  http://www.plxtech.com

Several IBIS models now exist for Galileo Technologies under:

  http://www.galileot.com/products/internetworking/catalog.html

OPENS FOR NEW ISSUES
Milt Swartz asked about the number of participants expected at the
January IBIS summit meeting. This was covered under the agenda
item "Other Summit Meeting Plans".

INTERNATIONAL/EXTERNAL PROGRESS
- - JEITA ED-5302 Standard for I/O Interface Model for Integrated Circuits
  (IMIC) - Bob Ross reported that the IMIC Link now has the published
  standard ED-5302 of March 2001 under:

    http://tsc.jeita.or.jp/eds/IOPG.htm

- - IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal
  (formerly, IEC 93/67/NP IBIS and EMC Simulation) - Stephen Peters
reported
  that a link to ICEM documentation including a preliminary ICEM Cookbook
  now exists under

    http://intrage.insa-tlse.fr/~etienne/Emc/index.html

  Bob Ross and Stephen participated by teleconference in a meeting held
  in Paris on Thursday, October 4, 2001. The ICEM working group reported
  that they now have a committee draft for vote (CDV) ready to send to
  the IEC for international approval. Stephen and Bob offered to review
  the ICEM proposal and provide feedback on syntax and IBIS compatibility.
  We expect a presentation on the ICEM progress at the January IBIS Summit.

  Bob also reported that EMC material including a more recent version of
the
  ICEM documentation exists under

    http://www.eda.org/pub/ibis/emc/

- - JEDEC JC-16 - Modeling and Testing - No report.

- - T10, Project 1414-DT - SCSI Signal Modeling (a Technical Committee of the

  National Committee for Information Technology (NCITS)) - No report.

PCB CONFERENCE EAST 2001 IBIS SUMMIT MEETING FEEDBACK
Stephen Peters requested feedback on the IBIS Summit Meeting on September
13, 2001 in Worcester, Massachusetts. Stephen noted that teleconferencing
had its disadvantages including not being on site and subject to other
meetings and interruptions. It is much better to be on-site and away from
the office.

Bob Ross stated that a number of presentations were successfully delivered
by teleconference. However, he missed being on site with the rest of the
group for more interaction.

Everyone felt that the meeting did go well. Stephen asked, and Bob
responded that all of the presentations including an Ad Hoc one by Arpad
Muranyi are now uploaded under:

  http://www.eda.org/pub/ibis/summits/sep01/

OTHER SUMMIT MEETINGS PLANS
Stephen Peters reported on the plans for the IBIS Summit Meeting scheduled
on Monday, January 28, 2002 associated with DesignCon 2002 in Santa Clara,
California. We will an Associate Sponsor. A large meeting room and
refreshments will be provided. We will also plan on a booth, and Guy de
Burgh will be handling the arrangements. Innoveda will be providing
the backdrop. Milt Schwartz is handling the local arrangements and National

Semiconductor is sponsoring the lunch. Initial notices about the meeting
will be issued in early December 2001.

Milt asked for a preliminary head count of who will attend. All the IBIS
officers plan to attend. Milt expects about 40 people based on the current
economy.

Bob Ross reported that plans are underway for a European IBIS Summit
Meeting
on Friday, March 8, 2002 associated with DATE2002 in Paris France. So far,
Mentor Graphics and Zuken are co-sponsors. More co-sponsors are requested.
As before, there will probably be a strong emphasis on EMC/EMI issues.

Bob added that we might consider teleconference connections at these
meetings because of the travel restriction uncertainty.

IBIS MODEL REVIEW COMMITTEE DISCUSSION
John Angulo still has not had a response regarding someone chairing the
IBIS
Model Review Committee.

Bob Ross reported no new models, and John also has no models left to
review.

MAJORDOMO UPDATE
John Angulo reported that IBIS Users activated in September. The email
archives are available under HTML formats with sorting through the
following
symbolic links:

  http://www.eda.org/pub/ibis/email_archive
  http://www.eda.org/pub/ibis/users_archive

The actual archives are under:

  http://www.eda.org/pub/ibis/email/email/
  http://www.eda.org/pub/ibis/email/users/

We are still working on cleaning up unnecessary soft links and on archiving

some IBIS reflector e-mail. Actual text archives should be available under
the above directories as email.archive and users.archive. The text versions

preserve the original text white spaces that are lost under the HTML
formats.

John Angulo reported that he is still dealing with mail archive issues.
IBIS reflector traffic is being archived into the HTML archives, but no
traffic have been entered into the parallel .txt archive since September
11. John noted that the ibis-users reflector archive is OK, and that a
permission problem with the IBIS reflector .txt archives was fixed. John
plans a further follow-up with the machine administrators.

John mentioned that the proper way to subscribe is by sending a message to
[email-masked] and include in the body the text "subscribe ibis" or
"subscribe ibis-users". An e-mail address is optional, but would be added
if it is different from the sending address. The [email-masked] still

works, but may be phased out in the future.

CONNECTOR PROPOSAL REPORT
Stephen Peters reported that meetings were held September 4, then
again on Monday September 17 and Oct 1. There was no meeting on
Sept. 24. The committee has almost completed its initial review
of the connector specification, and a proposal has been put forth
regarding supporting both RLGC and S-parameter matrixes. Stephen
stated that the committee is still on track to release the .icm
specification for IBIS Open Forum review in the first quarter of
2002.

IBIS FUTURES REPORT
Stephen Peters reported that meetings were held on Sept 6, 20, 27,
and Oct 4. The committee has been focused on creating the IBIS-ML
language reference manual (LRM), and an updated draft version of
the LRM was issued Wednesday. The committee is currently reviewing
the syntax rules and guidelines chapter as well as simulation
primitives.

Stephen also reported that Al Davis has withdrawn from the IBIS
Futures committee. While the committee will miss his input, the
spec is still on schedule to be ready for general review by the
IBIS Open Forum at the end of January 2002.

BIRD72.1 - ACCOMMODATING PMOS AND NMOS//PMOS SERIES FET MODELS
Tom Dagostio stated that there were just editorial changes. The intent
of BIRD72.1 is to document that [Series MOSFET] devices for switches do
consist of NMOS and also NMOS in parallel with PMOS devices. There may
also be PMOS only devices. The writeup needs to be changed so that is
not NMOS specific. Furthermore the PMOS in parallel with NMOS devices
have non-monotonic I-V tables, so the related ibischk parser needs to
have the warning messages changed.

Bob Ross added that some of the text had been cleaned up. Also a sample
I-V table for a real device is added. It show some of the non-monotonic
behavior that Tom described.

Stephen Peters did not understand the new equation in the document. Tom
stated that both the PMOS and NMOS currents needed to be added. Bob noted
that the terms Idsp and Idsn were not defined. Also there still exists some

references to Vgs which need to be changed to Vtable since the discussion
also apples to NMOS in parallel with PMOS devices (with two gates).

AR - Tom Dagostino issue BIRD72.2 with further editorial changes by October

12, 2001 so that it can be considered for a vote at the next IBIS meeting.

BIRD73.1 - FALL BACK SUBMODEL
Bob Ross discussed revisions in the recently issued BIRD73.1. Bob spoke
first about the suggested changes to the Bus_hold portion. Based on the
August 31, 2001 meeting comments, the corrupted Bus_hold examples were
restored. The Off_delay entries in the example were changed to be in
alignment with the text. In particular, the Off_delay subparameter has
typ/min/max table entries by value since there is no process/temperature/
voltage correlation to changes. Finally the suggested state table showing
initial conditions and transitions was entered.

Bob discussed the new state table. He noted that in the original bus_hold
writeup the initial submodel state of low or high is based on Vdie voltage
values with respect to V_trigger_r and V_trigger_f. This left an ambiguous
gap if the Vdie value fell in between these values due to, for example, a
Thevenin terminator. So Bob made the initial submodel state to be set to
the state of the driver in the net being analyzed. This is usually
consistent with the original writeup, but also gives a known simulator
setting in the case where the Vdie voltage makes the submodel state
unknown.

Bob also noted that one application would use Off_delay and only a [Pullup]

up table for a temporary rising edge "kicker" or Off_delay and only a
temporary [Pulldown] "kicker". A different initial state method is
documented. The submodel always is initialized in the "off" or High-Z
state. A [Pullup] would be initialize low, and a [Pulldown] would be
initialized high. BIRD73.1 is incorrect, and this needs to be fixed in
BIRD73.2.

A normal application might include switchable terminations (stronger than
just bus hold circuits). Usually two separate submodels would be
constructed so that each is initialized in the High-Z state for overall
bus low and high states. Lynne Green asked if the multiple output stages
that switch on and off can be modeled. Bob responded with yes by using more

submodels.

Bob stated that the Fall_back submodel changes had just a few editorial
changes for clarity. The submodel is initialized in the same state as the
driver in the net. This needs to be clarified. Bob will make more
editorial corrections and possibly review the technical writeup further.

AR - Bob Ross issue BIRD73.2 with editorial changes and with the Driver
restriction for further review and discussion.

IBISCHK3 BUG TRACKING STATUS
Bob Ross reported that Atul Agarwal has nearly completed the works for
fixing BUGs 48 - 56. He may not fix BUG55, but possibly fix BUG59. Bob
stated that Matthew Flora has a fix to BUG55 and also possibly BUG59.

We expect the ibischk3.2.8 to be available in October 2001. Bob described
that the executables need to be generated and uploaded and the source code
needs to be distributed to the companies that have source code licenses.

Lynne Green volunteered to produce a Linux executable. Bob suggested that
one also be produced for ibischk3.2.7.

XML FOR IBIS
Bob Ross introduced some work by Atul Agarwal regarding XML coding of IBIS.

This work will be uploaded in the future under:

  http://www.eda.org/pub/ibis/xml/

Bob is waiting for a generic IBIS model example that can be uploaded with
the other material. The material will contain a work in progress
syntactical description of IBIS called ibis.dtd. An ibis.html file will
show the IBIS structure graphically.

Bob noted that the work differs from what Mike LaBonte presented at
the June 8, 2000 IBIS Summit Meeting. Atul's format stores all min/typ/max
data are all in the same data base, whereas Mike's proposal had them
separated.

Comments will be requested when the information is uploaded.

NEXT MEETING:
The next teleconference meeting will be on Friday, October 27, 2001 from
8:00 A.M. to 10:00 AM Pacific time. BIRD72.2 is scheduled for a vote.

============================================================================

                                      NOTES

IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
            [email-masked]
            Senior Hardware Engineer, Intel Corporation
            M/S JF4-215
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

VICE CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            [email-masked]
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

SECRETARY: Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN: Roy Leventhal (837) 797-2152, Fax: (847) 222-2799
            [email-masked]
            Senior Engineer, CommWorks Corp. (a wholly owned 3Com
            subsidiary)
            1800 W. Central Rd.
            Mt. Prospect, IL 60056-2293

WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504
            [email-masked]
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
            [email-masked]
            Development Engineer, Innoveda
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  [email-masked]
      In the body, for the IBIS Open Forum Reflector:
      subscribe ibis <your e-mail address>

      In the body, for the IBIS Users' Group Reflector:
      subscribe ibis-users <your e-mail address>

      Help and other commands:
      help

  [email-masked]
      To join, change, or drop from either the IBIS Open Forum Reflector
      ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
      or both. State your request.

  [email-masked]
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  [email-masked]
      To send a message to the general IBIS Open Forum Reflector. This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements. Job posting information is not permitted.

  [email-masked]
      To send a message to the IBIS Users' Group Reflector. This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns. Job posting information is not permitted.

  [email-masked]
      To report ibischk2/3 parser bugs. The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported
      bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, and
      /pub/ibis/bugs/s2iplt/bugsplt.txt respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results. You can get on via FTP anonymous.

============================================================================

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------------------------------

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From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: IBIS BIRD72.2 ... Series FET Models
From: Bob Ross ([email-masked])
Date: Mon Oct 08 2001 - 17:49:29 PDT

   * Next message: Jim Bell: "IBISCHK3 bug report"
   * Previous message: Guy de Burgh: "EIA IBIS Open Forum Meeting Minutes"
   * Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

  --------------------------------------------------------------------

To IBIS Committee:

BIRD72.2 by Tom Dagostino is issued with some corrections suggested at
the October 5, 2001 IBIS meeting.

The new corrections are noted by |*** lines.

BIRD72.2 is scheduled for a vote at the October 26, 2001 meeting.

Bob Ross
Mentor Graphics

******************************************************************************

******************************************************************************

BIRD ID#: 72.2
ISSUE TITLE: Accommodating PMOS and NMOS//PMOS Series FET Models
REQUESTER: Tom Dagostino, Mentor Graphics
DATE SUBMITTED: 7-26-01, 10-3-01, 10-8-01
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

******************************************************************************

******************************************************************************

STATEMENT OF THE ISSUE:

The IBIS FET Bus Switch model assumes a series NMOS FET which has its gate
tied to Vdd. We have come across two other topologies for the FET switches,

specifically:

1. What appears to be a PMOS device with it's gate tied to ground
2. Parallel NMOS and PMOS devices with gates respectively tied to Vdd and
   ground.

The IBIS Golden Parser produces warnings and errors with models that
describe
this behavior.

******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

These models cause issues with the IBIS Golden Parser and, depending on
assumptions in the simulator's implementations that support the bus switch,

analysis issues.

For the single PMOS case:

The parser is set up to see increasing current as Vgs increase where Vgs is

defined as Vcc - Vsource. Given this definition for Vgs the current Id will

decrease as 'Vgs' increases for the PMOS device with its gate to ground.
The
parser gives an error of decreasing current as 'Vgs' increases.

Simulators may make the assumption the FET is a NMOS device and may not
handle
the characteristics properly if the model gets parsed in.

For the dual PMOS/NMOS case:

In the case of the dual PMOS/NMOS topology the currents through the
parallel
FET's will sum and produce an Id curve that:

- -- starts with significant current at 'Vgs' = 0 (current is flowing through

the PMOS device)

- -- decreases by 10 to 90% at about 40% of 'Vgs' range where both the PMOS
and
NMOS devices are both on

- -- increases to a larger value at 'Vgs' = Vdd than at 'Vgs" = 0. This is
where the NMOS device is fully on

This characteristic has been observed in several devices. This will cause a

non-monotonic warning from the parser.

It is not known how all simulators will handle this non-monotonic behavior.

In general the simulators should be able to handle these characteristics.
The IV curves define the device's characteristics and the simulator should
just work with that definition.

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

The following changes are proposed:

The definition of Voltage in the IV table changes. Vgs has been Vcc -
Vsource
assuming the gate was tied to Vcc. IBIS should now assume the voltage in
the
IV table is really Vcc minus the FET's source voltage (Voltage = Vcc -
Vsource). This makes old models compatible and no change in the model
format
is required.

Decreasing current vs. Voltage are allowed.

Non-monotonic currents in the table are expected in the parallel case but
warnings can still be issued. It may be useful to have the modeler note the

type of switch in the model so the user can better understand any
non-monotonic issues.

******************************************************************************

Changes and additions to the IBIS Specification are shown by the |* lines
More changes are documented by |** and |*** lines.

|=============================================================================

| Keyword: [Series MOSFET]
| Required: Yes, for series MOSFET switches
| Description: The data points under this keyword define the I-V tables for

| voltages measured at Pin 2 for a given Vds setting. Currents
| are considered positive if they flow into Pin 1. Pins 1 and
| 2 are listed under the [Series Pin Mapping] keyword under
| [Series Pin Mapping] and pin_2 columns, respectively.
| Sub-Params: Vds
| Usage Rules: The first column contains the voltage value, and the three
| remaining columns hold the typical, minimum, and maximum
| current values. The four entries, Voltage, I(typ), I(min),
| and I(max) must be placed on a single line and must be
| separated by at least one white space.
|
| All four columns are required under these keywords. However,
| data is only required in the typical column. If minimum
| and/or maximum current values are not available, the reserved
| word "NA" must be used. "NA" can be used for currents in the
| typical column, but numeric values MUST be specified for the
| first and last voltage points on any I-V table. Each I-V
| table must have at least 2, but not more than 100, voltage
| points.
|
| Other Notes: There is no monotonicity requirement. However the model
| supplier should realize that it may not be possible to derive
| a behavioral model from non-monotonic data.
|
|** Delete this Diagram

| The model is:
|
| Table Current
| ------->
| + Vds -
| Pin 1 Pin 2
| <---| |---> +
| d |_____| - s
| --+-- Vgs Vs
| | g +
| -
| Vg = [Voltage Range] = Vcc
| Vgs = Table Voltage = Vtable = Vcc - Vs
| Ids = Table Current for a given Vcc and Vds
|

|** Replace with this Diagram and Text:

|*
|* Table Current
|* -------> Ids
|* + Vds -
|*
|* Vcc
|* | g
|** --+--
|* ------- NMOS
|* Pin 1 | | Pin 2
|** <---| |---> + Voltage = Vcc - Vs
|* d |_____| s
|** PMOS --+-- Vs
|* | g
|** GND -
|*
|** Either of the FET's could be removed (or have zero current
|** contribution. Thus this model covers all four conditions, off,
|** single NMOS, single PMOS and parallel NMOS/PMOS.
|*
|* Voltage = Table Voltage = Vtable = Vcc - Vs
|* Ids = Table Current for a given Vcc and Vds
|
|** End of Addition

|** Delete these Sentences:
|**
| Internal logic that is generally referenced to the power rail
| is used to set the MOSFET switch to its 'On' state. Thus the
| [Voltage Range] settings provide the assumed gate voltages.
| If the [POWER Clamp Reference] exists, it overrides the
| [Voltage Range] value. The table entries are actually the Vgs
| values referenced to the power rail. The polarity conventions
|

|** Add these Sentences:

|* Internal Logic that is generally referenced to the power rail
|* is used to set the NMOS MOSFET switch to its 'ON' state.
|* Internal logic likewise referenced to ground is used to set the
|* PMOS device to its 'ON' state if the PMOS device is present.
|* Thus the [Voltage Range] settings provide the assumed
|* gate voltages. If the [POWER Clamp Reference] exists, it
|* overrides the [Voltage Range] value. The table entries are
|* actually Vgs of the NMOS device and Vcc - Vgs of the PMOS
!* device, if present. The polarity conventions

|** End of Addition

| are identical with those used for other tables that are
| referenced to power rails. Thus the voltage column can be
| viewed as a table defining the source voltages Vs according to
|*** the convention: Vtable = Vcc - Vs. This convention remains
|*** even without the NMOS device.
|
| If the switch is used in an application such as interfacing
| between 3.3 V and 5.0 V logic, the Vcc may be biased at a
| voltage (such as 4.3 V) that is different from a power rail
| voltage (such as 5.0 V) used to create the model. Just
| readjust the [Voltage Range] entries (or [POWER Clamp
| Reference] entries).
|
| One fundamental assumption in the MOSFET switch model is that
| it operates in a symmetrical manner. The tables and
| expressions are given assuming that Vd >= Vs. If Vd < Vs,
| then apply the same relationships under the assumption that
| the source and drain nodes are interchanged. A consequence of
| this assumption is that the Vds subparameter is constrained to
| values Vds > 0. It is assumed that with Vds = 0 the currents
| will be 0 mA. A further consequence of this assumption that
| would be embedded in the analysis process is that the voltage
| table is based on the side of the model with the lowest
| voltage (and that side is defined as the source). Thus the
| analysis must allow current to flow in both directions, as
| would occur due to reflections when the switch is connected in
| series with an unterminated transmission line.
|
| The model data is used to create an On state relationship
| between the actual drain to source current, ids, and the
| actual drain to source voltage, vds:
|
| ids = f(vds).
|
| This functional relationship depends on the actual source
| voltage Vs and can be expressed in terms of the corresponding
| table currents associated with Vs (and expressed as a function
|*** of Vtable).
|
| If only one [Series MOSFET] table is supplied (as a first
| order approximation), the functional relationship is assumed
| to be linearly related to the table drain to source current,
| Ids, for the given Vds subparameter value and located at the
|*** existing gate to source voltage value Vtable. This table
|*** current is denoted as Ids(Vtable, Vds). The functional
|*** relationship becomes:
|

|** Delete this Equation
| ids = Ids(Vgs, Vds) * vds / Vds.
|*

|**** Delete this Equation
|** Add This Equation:

|** ids = Idsn(Vtable, Vds) * vds/Vds +
|** Idsp(Vcc - Vtable, Vds) * vds/Vds
|

|*** Add This Equation:
|*** ids = Ids(Vtable, Vds) * vds/Vds.

|** End of Addition

| More than one [Series MOSFET] table is permitted, but it is
| simulator dependent how the data will be used. Each
| successive [Series MOSFET] table must have a different
| subparameter value for Vds. The number of tables must not
| exceed 100.
|
| C_comp values are ignored for [Series MOSFET] models.
|-----------------------------------------------------------------------------

|** An NMOS Example
|**
[On]
[Series MOSFET]
Vds = 1.0
| Voltage I(typ) I(min) I(max)
    5.0V 257.9m 153.3m 399.5m | Defines the Ids current as a
    4.0V 203.0m 119.4m 317.3m |*** function of Vtable, for Vds = 1.0
    3.0V 129.8m 74.7m 205.6m
    2.0V 31.2m 16.6m 51.0m
    1.0V 52.7p 46.7p 56.7p
    0.0V 0.0p 0.0p 0.0p
|

|** A PMOS/NMOS Example
|**
[On]
[Series MOSFET]
Vds = 0.5
| Voltage I(typ) I(min) I(max)
0.0 48.6ma NA NA
0.1 47.7ma NA NA
0.2 46.5ma NA NA
0.3 46.1ma NA NA
0.4 45.3ma NA NA
0.5 44.4ma NA NA
0.6 42.9ma NA NA
0.7 42.3ma NA NA
0.8 41.2ma NA NA
0.9 39.7ma NA NA
1.0 38.6ma NA NA
1.1 38.1ma NA NA
1.2 38.6ma NA NA
1.3 40.7ma NA NA
1.4 45.0ma NA NA
1.5 49.2ma NA NA
1.6 52.3ma NA NA
1.7 55.1ma NA NA
1.8 57.7ma NA NA
1.9 58.8ma NA NA
2.0 58.9ma NA NA
2.1 59.2ma NA NA
2.2 59.3ma NA NA
2.3 59.4ma NA NA
2.4 59.8ma NA NA
2.5 60.1ma NA NA
2.6 61.8ma NA NA
2.7 62.3ma NA NA
2.8 63.4ma NA NA
2.9 64.4ma NA NA
3.0 65.3ma NA NA
3.1 66.0ma NA NA
3.2 66.8ma NA NA
3.3 68.2ma NA NA
|
|=============================================================================

******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

These models cause issues with the IBIS Golden Parser and, depending on
assumptions in the simulator's implementations that support the bus switch,

analysis issues.

For the single PMOS case:

The parser is set up to see increasing current as Vgs increase where Vgs is

defined as Vcc - Vsource. Given this definition for Vgs the current Id will

decrease as 'Vgs' increases for the PMOS device with its gate to ground.
The
parser gives an error of decreasing current as 'Vgs' increases.

Simulators may make the assumption the FET is a NMOS device and may not
handle
the characteristics properly if the model gets parsed in.

For the dual PMOS/NMOS case:

In the case of the dual PMOS/NMOS topology the currents through the
parallel
FET's will sum and produce an Id curve that:

- -- starts with significant current at 'Vgs' = 0 (current is flowing through

the PMOS device)

- -- decreases by 10 to 90% at about 40% of 'Vgs' range where both the PMOS
and
NMOS devices are both on

- -- increases to a larger value at 'Vgs' = Vdd than at 'Vgs" = 0. This is
where the NMOS device is fully on

This characteristic has been observed in several devices. This will cause a

non-monotonic warning from the parser.

It is not known how all simulators will handle this non-monotonic behavior.

In general the simulators should be able to handle these characteristics.
The IV curves define the device's characteristics and the simulator should
just work with that definition.

Changes and additions are noted by |* lines.

BIRD72.1 has some editorial revisions including moving this section from
the
beginning to this location. A new example is added showing PMOS//NMOS
data. Changes are noted by |** lines

BIRD72.2 has more editorial revision and a correction to an equation which
used Idsn and Idsp. It turns out that the functional scaling relationship
is
retained in terms of the over Ids parameter. The need to decompose to Idsn
and Idsp only introduced some sign notation confusion and table reference
confusion. The actual psuedo "gate" is the NMOS gate, even if the NMOS
device does not exist. So the Vtable could still be considered as only the
NMOS as in IBIS Version 3.2.

New changes are noted by |*** lines.

******************************************************************************

ANY OTHER BACKGROUND INFORMATION:

An Ad Hoc presentation on this topic was initially presented at the IBIS
Summit Meeting on June 21, 2001.

******************************************************************************

  --------------------------------------------------------------------

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This archive was generated by hypermail 2b28 : Mon Oct 08 2001 - 18:09:24
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------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: IBISCHK3 bug report
From: Jim Bell ([email-masked])
Date: Wed Oct 10 2001 - 16:48:44 PDT

   * Next message: Peters, Stephen: "RE: IBISCHK3 bug report"
   * Previous message: Bob Ross: "IBIS BIRD72.2 ... Series FET Models"
   * Next in thread: Peters, Stephen: "RE: IBISCHK3 bug report"
   * Reply: Peters, Stephen: "RE: IBISCHK3 bug report"
   * Reply: Ross, Bob: "Re: IBISCHK3 bug report"
   * Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

  --------------------------------------------------------------------

PLATFORM: PC

OS AND VERSION: Windows 2000 Version 5.0

REPORTED BY: James C. Bell, SiQual Inc.

DATE: 10/10/01

DESCRIPTION OF BUG:

The IBISCHK3 message

     "ERROR - Component '%1': [Series Pin Mapping] Pin2 '%a': model type
cannot be Series or Series_switch."

should be

     "...model name cannot be Series or Series_switch."

INSERT IBIS FILE DEMONSTRATING THE BUG:

Not necessary.

===
Jim Bell
SiQual, A division of Stilwell Baker
[email-masked]
phone (503)885-1231
fax (503)885-0550
http://www.siqual.com/

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This archive was generated by hypermail 2b28 : Wed Oct 10 2001 - 17:17:54
PDT

------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: RE: IBISCHK3 bug report
From: Peters, Stephen ([email-masked])
Date: Thu Oct 11 2001 - 11:58:33 PDT

   * Next message: Ross, Bob: "Re: IBISCHK3 bug report"
   * Previous message: Jim Bell: "IBISCHK3 bug report"
   * Maybe in reply to: Jim Bell: "IBISCHK3 bug report"
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  --------------------------------------------------------------------

Hi James:

  Thanks for the bug report. Discussion of this bug report will be on the
agenda at the next IBIS teleconference.

  (Note: for future reference, IBISCHK bug reports should be mailed to
[email-masked] <mailto:[email-masked]> .)

 Regards,
 Stephen Peters
 Intel Corp.

 -----Original Message-----
From: Jim Bell [mailto:[email-masked]]
Sent: Wednesday, October 10, 2001 4:49 PM
To: [email-masked]
Subject: IBISCHK3 bug report

PLATFORM: PC

OS AND VERSION: Windows 2000 Version 5.0

REPORTED BY: James C. Bell, SiQual Inc.

DATE: 10/10/01

DESCRIPTION OF BUG:

The IBISCHK3 message

    "ERROR - Component '%1': [Series Pin Mapping] Pin2 '%a': model type
cannot be Series or Series_switch."

should be

    "...model name cannot be Series or Series_switch."

INSERT IBIS FILE DEMONSTRATING THE BUG:

Not necessary.

===
Jim Bell
SiQual, A division of Stilwell Baker
[email-masked]
phone (503)885-1231
fax (503)885-0550
http://www.siqual.com/ <http://www.siqual.com/>

  --------------------------------------------------------------------

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  --------------------------------------------------------------------

This archive was generated by hypermail 2b28 : Thu Oct 11 2001 - 12:24:24
PDT

------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: Re: IBISCHK3 bug report
From: Ross, Bob ([email-masked])
Date: Thu Oct 11 2001 - 15:47:39 PDT

   * Next message: Jim Bell: "Re: IBISCHK3 bug report"
   * Previous message: Peters, Stephen: "RE: IBISCHK3 bug report"
   * Maybe in reply to: Jim Bell: "IBISCHK3 bug report"
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   * Reply: Jim Bell: "Re: IBISCHK3 bug report"
   * Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

  --------------------------------------------------------------------

Jim:

I looked at the example sent privately and also noted that
you used ibischk3 Version 3.2.5.

The ERROR did not appear in ibischk3 Version 3.2.7. It may
have gone away because of resolving some other problem. In
fact, I am not sure how I could reproduce this "Error" under
the current parser.

Your file still has a number of serious problems even though
it now passes the parser. These problems would need to be
isolated with specific examples.

Bob Ross
Mentor Graphics

Jim Bell wrote:
>
> PLATFORM: PC
>
> OS AND VERSION: Windows 2000 Version 5.0
>
> REPORTED BY: James C. Bell, SiQual Inc.
>
> DATE: 10/10/01
>
> DESCRIPTION OF BUG:
>
> The IBISCHK3 message
>
> "ERROR - Component '%1': [Series Pin Mapping] Pin2 '%a': model type
cannot be Series or Series_switch."
>
> should be
>
> "...model name cannot be Series or Series_switch."
>
> INSERT IBIS FILE DEMONSTRATING THE BUG:
>
> Not necessary.
>
> ===
> Jim Bell
> SiQual, A division of Stilwell Baker
> [email-masked]
> phone (503)885-1231
> fax (503)885-0550
> http://www.siqual.com/ <http://www.siqual.com/>

  --------------------------------------------------------------------

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  --------------------------------------------------------------------

This archive was generated by hypermail 2b28 : Thu Oct 11 2001 - 16:08:00
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------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: Re: IBISCHK3 bug report
From: Jim Bell ([email-masked])
Date: Thu Oct 11 2001 - 17:35:02 PDT

   * Previous message: Ross, Bob: "Re: IBISCHK3 bug report"
   * In reply to: Ross, Bob: "Re: IBISCHK3 bug report"
   * Reply: Jim Bell: "Re: IBISCHK3 bug report"
   * Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

  --------------------------------------------------------------------

Bob,

No need to go any further. The bug has been fixed in Version 3.2.7.

Thank you for looking at this.

- - Jim

At 03:47 PM 10/11/2001 -0700, Ross, Bob wrote:
>Jim:
>
>I looked at the example sent privately and also noted that
>you used ibischk3 Version 3.2.5.
>
>The ERROR did not appear in ibischk3 Version 3.2.7. It may
>have gone away because of resolving some other problem. In
>fact, I am not sure how I could reproduce this "Error" under
>the current parser.
>
>Your file still has a number of serious problems even though
>it now passes the parser. These problems would need to be
>isolated with specific examples.
>
>Bob Ross
>Mentor Graphics
>
>
>Jim Bell wrote:
> >
> > PLATFORM: PC
> >
> > OS AND VERSION: Windows 2000 Version 5.0
> >
> > REPORTED BY: James C. Bell, SiQual Inc.
> >
> > DATE: 10/10/01
> >
> > DESCRIPTION OF BUG:
> >
> > The IBISCHK3 message
> >
> > "ERROR - Component '%1': [Series Pin Mapping] Pin2 '%a': model type
> cannot be Series or Series_switch."
> >
> > should be
> >
> > "...model name cannot be Series or Series_switch."
> >
> > INSERT IBIS FILE DEMONSTRATING THE BUG:
> >
> > Not necessary.
> >
> > ===
> > Jim Bell
> > SiQual, A division of Stilwell Baker
> > [email-masked]
> > phone (503)885-1231
> > fax (503)885-0550
> > http://www.siqual.com/ <http://www.siqual.com/>

===
Jim Bell
SiQual, A division of Stilwell Baker
[email-masked]
phone (503)885-1231
fax (503)885-0550
http://www.siqual.com/

  --------------------------------------------------------------------

   * Previous message: Ross, Bob: "Re: IBISCHK3 bug report"
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  --------------------------------------------------------------------

This archive was generated by hypermail 2b28 : Thu Oct 11 2001 - 17:54:59
PDT

------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: power plane inductance
From: Anthony Moulds ([email-masked])
Date: Mon Oct 15 2001 - 07:36:35 PDT

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  --------------------------------------------------------------------

Sorry if this is a little off-topic but is there a formula
for determining the inductance between two points on a power
plane in a multi-layer pcb (pH/inch2) ?

[I need to check (quantitatively) the max placement distance of decoupling
caps to fast logic when both are via-ing down to the power/gnd planes.]

Thanks.

Anthony Moulds

  --------------------------------------------------------------------

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  --------------------------------------------------------------------

This archive was generated by hypermail 2b28 : Mon Oct 15 2001 - 07:56:14
PDT

------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: RE: power plane inductance
From: Peters, Stephen ([email-masked])
Date: Mon Oct 15 2001 - 09:06:14 PDT

   * Next message: Yeshwant Mehta: "IBIS model from encrypted spice"
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  --------------------------------------------------------------------

Hi Anthony:

   You many want to post this question on the si_list -- I bet someone will

have an answer for you there.

  [email-masked]

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: Anthony Moulds [mailto:[email-masked]]
Sent: Monday, October 15, 2001 7:37 AM
To: [email-masked]
Subject: power plane inductance
Importance: High
Sensitivity: Private

Sorry if this is a little off-topic but is there a formula
for determining the inductance between two points on a power
plane in a multi-layer pcb (pH/inch2) ?

[I need to check (quantitatively) the max placement distance of decoupling
caps to fast logic when both are via-ing down to the power/gnd planes.]

Thanks.

Anthony Moulds

  --------------------------------------------------------------------

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  --------------------------------------------------------------------

This archive was generated by hypermail 2b28 : Mon Oct 15 2001 - 09:29:56
PDT

------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: IBIS model from encrypted spice
From: Yeshwant Mehta ([email-masked])
Date: Mon Oct 15 2001 - 15:09:54 PDT

   * Next message: Peters, Stephen: "RE: IBIS model from encrypted spice"
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   * Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

  --------------------------------------------------------------------

Can I create a IBIS model from encrypted spice netlist?

Any consultant aavailable to generate IBIS models for some I/Os and build
the
IBIS model for the chip?

Yeshwnat Mehta

  --------------------------------------------------------------------

   * application/ms-tnef attachment: winmail.dat

  --------------------------------------------------------------------

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  --------------------------------------------------------------------

This archive was generated by hypermail 2b28 : Mon Oct 15 2001 - 15:37:44
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------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: RE: IBIS model from encrypted spice
From: Peters, Stephen ([email-masked])
Date: Mon Oct 15 2001 - 16:15:52 PDT

   * Next message: Syed Huq: "Re: IBIS model from encrypted spice"
   * Previous message: Yeshwant Mehta: "IBIS model from encrypted spice"
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   * Maybe reply: Peters, Stephen: "RE: IBIS model from encrypted spice"
   * Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

  --------------------------------------------------------------------

Hi Mehta:

  Assuming that you have enough information about the SPICE model to hook
power up, identify input and output ports, etc. I believe the spice2ibis
program can be used to extract the relevant behavioral data. Consultants
and companies are available and they should reply to you privately.

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: Yeshwant Mehta [mailto:[email-masked]]
Sent: Monday, October 15, 2001 3:10 PM
To: [email-masked]
Cc: Yeshwant Mehta
Subject: IBIS model from encrypted spice

Can I create a IBIS model from encrypted spice netlist?

Any consultant aavailable to generate IBIS models for some I/Os and build
the
IBIS model for the chip?

Yeshwnat Mehta

  --------------------------------------------------------------------

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  --------------------------------------------------------------------

This archive was generated by hypermail 2b28 : Mon Oct 15 2001 - 16:33:37
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------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: Re: IBIS model from encrypted spice
From: Syed Huq ([email-masked])
Date: Mon Oct 15 2001 - 17:03:02 PDT

   * Next message: Bob Ross: "IBIS BIRD73.2 - Fall Back Submodel"
   * Previous message: Peters, Stephen: "RE: IBIS model from encrypted
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   * Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

  --------------------------------------------------------------------

s2ibis2 can handle encrypted spice models.

Syed

> From: "Yeshwant Mehta" <[email-masked]>
> To: <[email-masked]>
> Cc: "Yeshwant Mehta" <[email-masked]>
> Subject: IBIS model from encrypted spice
> Date: Mon, 15 Oct 2001 15:09:54 -0700
> MIME-Version: 1.0
> X-Priority: 3 (Normal)
> X-MSMail-Priority: Normal
> Importance: Normal
> X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4522.1200
> X-MS-TNEF-Correlator: <[email-masked]>
>
> Can I create a IBIS model from encrypted spice netlist?
>
> Any consultant aavailable to generate IBIS models for some I/Os and build

> the
> IBIS model for the chip?
>
> Yeshwnat Mehta
>

  --------------------------------------------------------------------

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  --------------------------------------------------------------------

This archive was generated by hypermail 2b28 : Mon Oct 15 2001 - 17:28:49
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------------------------------

Date: Tue Oct 16 2001 - 16:45:10 PDT
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 * Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]
 --------------------------------------------------------------------
 To IBIS Committee:
 BIRD73.2 contains substantial revision in technical content
From: Bob Ross ([email-masked])
Subject: [none]

------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: ibis question
From: Sonny Tang ([email-masked])
Date: Tue Oct 16 2001 - 17:02:46 PDT

   * Next message: Scott McMorrow: "Re: ibis question"
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  --------------------------------------------------------------------

Dear sir:
           I am making an ibis model for an IO. After I run ibischk3, I
got some warnings about VT curves and VI curves are not matching within
2%. Actually, I follow the ibis cookbook to run hspice and make my ibis
file. I don't know what cause this kind warning and how to fix it.
Also, how does ibis checker calculate data for check VT,VI curve. The
following are my ibis file and error message. Thanks

Regards,

Sonny

  --------------------------------------------------------------------
[abc.ibs]

  --------------------------------------------------------------------
[warn]

  --------------------------------------------------------------------

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  --------------------------------------------------------------------

This archive was generated by hypermail 2b28 : Tue Oct 16 2001 - 17:34:04
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------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: Re: ibis question
From: Scott McMorrow ([email-masked])
Date: Tue Oct 16 2001 - 17:53:09 PDT

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  --------------------------------------------------------------------

Sonny,

You have three issues with you s2ibis2 extraction:

1) the temperature range for typ/min/max are incorrect.
2) the voltage range for typ/min/max is incorrect.

        These are causing your first warning message.

3) you did not include min and max fixture voltages in
your waveform table extractions.

        This is causing your waveform table warnings.

Make the following changes to your s2i file:

| typ min max
|
[Temperature range] 25 100 0

| typ min max
|
[Voltage range] 1.2 1.1 1.2

| Rf Vf Vf_min Vf_max Lf Cf Rd Ld Cd
|
[Rising waveform] 50 0.0 0.0 0.0 NA NA NA NA NA
[Rising waveform] 50 1.2 1.1 1.3 NA NA NA NA NA
[Falling waveform] 50 1.2 1.1 1.3 NA NA NA NA NA
[Falling waveform] 50 0.0 0.0 0.0 NA NA NA NA NA

And make sure that your calls to the spice process decks track
the min and max corners correctly.

The monotonicity issues can be edited out of the file

best regards,

scott

- --
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com
Sonny Tang wrote:
> Dear sir:
>            I am making an ibis model for an IO.  After I run ibischk3, I
> got some warnings about VT curves and VI curves are not matching within
> 2%.  Actually, I follow the ibis cookbook to run hspice and make my ibis
> file.  I don't know what cause this kind warning and how to fix it.
> Also, how does ibis checker calculate data for check VT,VI curve.  The
> following are my ibis file and error message.  Thanks
>
> Regards,
>
> Sonny
>
>   ------------------------------------------------------------------------------------------------------------------------------------
>               Name: abc.ibs
>    abc.ibs    Type: application/x-unknown-content-type-ibs_auto_file
>           Encoding: base64
>
>   ------------------------------------------------------------------------------------------------------------------------------------
> IBISCHK3 V3.2.5
>
> Checking abc.ibs for IBIS 2.1 Compatibility...
>
> WARNING (line   36) - Typ value is not in between min and max
> WARNING (line   47) - Pulldown Typical data is non-monotonic
> WARNING (line   48) - Pulldown Minimum data is non-monotonic
> WARNING - Model 'abc': TYP AC Rising Endpoints ( 0.00V,  0.60V) not within
>           0.012V (2%) of ( 0.00V,  0.65V) on VI curves for 50 Ohms to 0V
> WARNING - Model 'abc': TYP AC Rising Endpoints ( 0.59V,  1.20V) not within
>           0.012V (2%) of ( 0.59V,  1.25V) on VI curves for 50 Ohms to 1.2V
> WARNING - Model 'abc': TYP AC Falling Endpoints ( 0.59V,  1.20V) not within
>           0.012V (2%) of ( 0.59V,  1.25V) on VI curves for 50 Ohms to 1.2V
> WARNING - Model 'abc': TYP AC Falling Endpoints ( 0.00V,  0.60V) not within
>           0.012V (2%) of ( 0.00V,  0.65V) on VI curves for 50 Ohms to 0V
> WARNING - Model 'abc': MIN AC Rising Endpoints ( 0.00V,  0.52V) not within
>           0.010V (2%) of ( 0.00V,  0.57V) on VI curves for 50 Ohms to 0V
> WARNING - Model 'abc': MIN AC Rising Endpoints ( 0.54V,  1.08V) not within
>           0.011V (2%) of ( 0.60V,  1.20V) on VI curves for 50 Ohms to 1.2V
> WARNING - Model 'abc': MIN AC Falling Endpoints ( 0.54V,  1.08V) not within
>           0.011V (2%) of ( 0.60V,  1.20V) on VI curves for 50 Ohms to 1.2V
> WARNING - Model 'abc': MIN AC Falling Endpoints ( 0.00V,  0.52V) not within
>           0.010V (2%) of ( 0.00V,  0.57V) on VI curves for 50 Ohms to 0V
> WARNING - Model 'abc': MAX AC Rising Endpoints ( 0.00V,  0.66V) not within
>           0.013V (2%) of ( 0.00V,  0.56V) on VI curves for 50 Ohms to 0V
> WARNING - Model 'abc': MAX AC Rising Endpoints ( 0.65V,  1.32V) not within
>           0.013V (2%) of ( 0.59V,  1.16V) on VI curves for 50 Ohms to 1.2V
> WARNING - Model 'abc': MAX AC Falling Endpoints ( 0.65V,  1.32V) not within
>           0.013V (2%) of ( 0.59V,  1.16V) on VI curves for 50 Ohms to 1.2V
> WARNING - Model 'abc': MAX AC Falling Endpoints ( 0.00V,  0.66V) not within
>           0.013V (2%) of ( 0.00V,  0.56V) on VI curves for 50 Ohms to 0V
>
> Errors  : 0
> Warnings: 15
>
> File Passed

  --------------------------------------------------------------------

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This archive was generated by hypermail 2b28 : Tue Oct 16 2001 - 18:11:04
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------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: Re: ibis question
From: Scott McMorrow ([email-masked])
Date: Tue Oct 16 2001 - 18:18:42 PDT

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  --------------------------------------------------------------------

Sonny,

Oops, I made one mistake.

|
[Voltage range] 1.2 1.1 1.2

should be:

|
[Voltage range] 1.2 1.1 1.3

regards,

scott

Scott McMorrow wrote:

> Sonny,
>
> You have three issues with you s2ibis2 extraction:
>
> 1) the temperature range for typ/min/max are incorrect.
> 2) the voltage range for typ/min/max is incorrect.
>
> These are causing your first warning message.
>
> 3) you did not include min and max fixture voltages in
> your waveform table extractions.
>
> This is causing your waveform table warnings.
>
> Make the following changes to your s2i file:
>
> | typ min max
> |
> [Temperature range] 25 100 0
>
> | typ min max
> |
> [Voltage range] 1.2 1.1 1.2
>
> | Rf Vf Vf_min Vf_max Lf Cf Rd Ld Cd
> |
> [Rising waveform] 50 0.0 0.0 0.0 NA NA NA NA NA
> [Rising waveform] 50 1.2 1.1 1.3 NA NA NA NA NA
> [Falling waveform] 50 1.2 1.1 1.3 NA NA NA NA NA
> [Falling waveform] 50 0.0 0.0 0.0 NA NA NA NA NA
>
> And make sure that your calls to the spice process decks track
> the min and max corners correctly.
>
> The monotonicity issues can be edited out of the file
>
> best regards,
>
> scott
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR 97062-3090
> (503) 885-1231
> http://www.siqual.com
>
> Sonny Tang wrote:
>
> > Dear sir:
> > I am making an ibis model for an IO. After I run ibischk3, I
> > got some warnings about VT curves and VI curves are not matching within

> > 2%. Actually, I follow the ibis cookbook to run hspice and make my ibis

> > file. I don't know what cause this kind warning and how to fix it.
> > Also, how does ibis checker calculate data for check VT,VI curve. The
> > following are my ibis file and error message. Thanks
> >
> > Regards,
> >
> > Sonny
> >
> >
- ------------------------------------------------------------------------------------------------------------------------------------

> > Name: abc.ibs
> > abc.ibs Type: application/x-unknown-content-type-ibs_auto_file
> > Encoding: base64
> >
> >
- ------------------------------------------------------------------------------------------------------------------------------------

> > IBISCHK3 V3.2.5
> >
> > Checking abc.ibs for IBIS 2.1 Compatibility...
> >
> > WARNING (line 36) - Typ value is not in between min and max
> > WARNING (line 47) - Pulldown Typical data is non-monotonic
> > WARNING (line 48) - Pulldown Minimum data is non-monotonic
> > WARNING - Model 'abc': TYP AC Rising Endpoints ( 0.00V, 0.60V) not
within
> > 0.012V (2%) of ( 0.00V, 0.65V) on VI curves for 50 Ohms to 0V
> > WARNING - Model 'abc': TYP AC Rising Endpoints ( 0.59V, 1.20V) not
within
> > 0.012V (2%) of ( 0.59V, 1.25V) on VI curves for 50 Ohms to 1.2V
> > WARNING - Model 'abc': TYP AC Falling Endpoints ( 0.59V, 1.20V) not
within
> > 0.012V (2%) of ( 0.59V, 1.25V) on VI curves for 50 Ohms to 1.2V
> > WARNING - Model 'abc': TYP AC Falling Endpoints ( 0.00V, 0.60V) not
within
> > 0.012V (2%) of ( 0.00V, 0.65V) on VI curves for 50 Ohms to 0V
> > WARNING - Model 'abc': MIN AC Rising Endpoints ( 0.00V, 0.52V) not
within
> > 0.010V (2%) of ( 0.00V, 0.57V) on VI curves for 50 Ohms to 0V
> > WARNING - Model 'abc': MIN AC Rising Endpoints ( 0.54V, 1.08V) not
within
> > 0.011V (2%) of ( 0.60V, 1.20V) on VI curves for 50 Ohms to 1.2V
> > WARNING - Model 'abc': MIN AC Falling Endpoints ( 0.54V, 1.08V) not
within
> > 0.011V (2%) of ( 0.60V, 1.20V) on VI curves for 50 Ohms to 1.2V
> > WARNING - Model 'abc': MIN AC Falling Endpoints ( 0.00V, 0.52V) not
within
> > 0.010V (2%) of ( 0.00V, 0.57V) on VI curves for 50 Ohms to 0V
> > WARNING - Model 'abc': MAX AC Rising Endpoints ( 0.00V, 0.66V) not
within
> > 0.013V (2%) of ( 0.00V, 0.56V) on VI curves for 50 Ohms to 0V
> > WARNING - Model 'abc': MAX AC Rising Endpoints ( 0.65V, 1.32V) not
within
> > 0.013V (2%) of ( 0.59V, 1.16V) on VI curves for 50 Ohms to 1.2V
> > WARNING - Model 'abc': MAX AC Falling Endpoints ( 0.65V, 1.32V) not
within
> > 0.013V (2%) of ( 0.59V, 1.16V) on VI curves for 50 Ohms to 1.2V
> > WARNING - Model 'abc': MAX AC Falling Endpoints ( 0.00V, 0.66V) not
within
> > 0.013V (2%) of ( 0.00V, 0.56V) on VI curves for 50 Ohms to 0V
> >
> > Errors : 0
> > Warnings: 15
> >
> > File Passed

- --
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

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------------------------------

Date: Thu, 18 Oct 2001 00:56:56 -0400
From: Steve Grout <[email-masked]>
Subject: test - please ignore

This is a test of the [email-masked] list - Please
ignore.

------------------------------

Date: Fri, 19 Oct 2001 08:42:49 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: IBIS Meeting Agenda 10/26

		     IBIS Open Forum Meeting Agenda
			      for 10/26/01

		 Bridge Number    Reservation #   Passcode
             1-916-356-2663   3               0776283

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Stephen Peters and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Peters

     - Intros of New IBIS Participants, Meeting Quorum       Peters
     - Membership Update and Treasurers Report               Fleming/Ross
     - Review of Previous Meeting's Minutes (and ARs)        Peters
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Leventhal, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - pr EIAJ ED-5302 Standard for I/O Interface Model      
	  for Integrated Circuits (IMIC)                       Peters
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters
     - JEDEC JC-16 Modeling and Testing                      Sessions
     - T10, Project 1414-DT - SCSI Signal Modeling           Barnes

     Other Summit Meeting Plans                              Peters/Ross
     - DesignCon2002
     - Date2002
     - Future JEDEC/IBIS Meeting

     IBIS Model Review Committee                             Ross

     Majordomo Update                                        Angulo

     New Administrative Issues                               All

8:45 Technical Discussion

     Connector Proposal Report                               Peters/Ross

     IBIS Futures Group Report                               Peters/Green

     BIRD72.2 - Accommodating PMOS and NMOS/PMOS Series FET  Dagostino/Ross
                Models (VOTE)

     BIRD73.2 - Fall Back Submodel                           Ross

     ibischk3 Status                                         Ross
     - BUG61 - Parser Fails to Flag Missing [Series Switch   Ross/Bell
               Groups] Table

     - BUG62 - Not All Non-Monotonic Points Reported         Green/Wang/Ross

     XML for IBIS                                            Ross

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Peters

9:55 Sign Off

------------------------------

End of ibis V1 #3
*****************