Subject: ibis V1 #1
From: owner-ibis@ (ibis)
To: [email-masked]

ibis             Friday, October 19 2001             Volume 01 : Number 001

----------------------------------------------------------------------

Date: Fri, 03 Aug 2001 17:00:14 +0800
From: Li Li <[email-masked]>
Subject: about [Driver Schedule]

Hi,

    I got some questions about [Driver Schedule].
    Are there any other relationships between the models defined in
[Driver Schedule] except timing relationships?
    How can I judge the way buffer of this model is connected to that of
other models with the timing relationships?
    Where can I find the documents or test cases about [Driver
Schedule]?

    Any comment or suggestion will be greatly appreciated.

Thanks,
Li

------------------------------

Date: Fri, 03 Aug 2001 11:10:36 -0400
From: "Cecilia Fleming" <[email-masked]>
Subject: Re: about [Driver Schedule]

Our bank information is as follows:

First Union National Bank
ABA# 056007604
ACCT# 2000005725537
Bank Swift Code: PNBPUS33

Regards,

Cece

>>> Li Li <[email-masked]> 08/03/01 05:00AM >>>
Hi,

    I got some questions about [Driver Schedule].
    Are there any other relationships between the models defined in
[Driver Schedule] except timing relationships?
    How can I judge the way buffer of this model is connected to that of
other models with the timing relationships?
    Where can I find the documents or test cases about [Driver
Schedule]?

    Any comment or suggestion will be greatly appreciated.

Thanks,
Li

------------------------------

Date: Fri, 3 Aug 2001 09:00:20 -0700 
From: "Peters, Stephen" <[email-masked]>
Subject: Agenda, IBIS Open Forum Teleconference 8/10

		     IBIS Open Forum Meeting Agenda
			      for 8/10/01

		 Bridge Number    Reservation #   Passcode
  New Number --> (877) 299-1938   none            6350164

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Stephen Peters and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Peters

     - Intros of New IBIS Participants, Meeting Quorum       Peters
     - Membership Update and Treasurers Report               Fleming/Ross
     - Review of Previous Meeting's Minutes (and ARs)        Peters
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Leventhal, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-1 (IBIS Version 3.2)                        Fleming
     - pr EIAJ ED-5302 Standard for I/O Interface Model      
	  for Integrated Circuits (IMIC)                       Peters
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters
     - JEDEC JC-16 Modeling and Testing                      Sessions
     - T10, Project 1414-DT - SCSI Signal Modeling           Barnes

     PCBEAST 2001 IBIS Summit Meeting                        Ross
     - Funding

     IBIS Model Review Committee                             Angulo/Ross

     Majordomo Update                                        Angulo

     New Administrative Issues                               All

8:45 Technical Discussion

     Connector Proposal Review                               Peters/Ross

     IBIS Futures Group Report (IBIS-X, API, BIRDxx)         Peters
     - IBIS-X parser funding

     BIRD70.4 - Golden Waveforms  (VOTE)                     Edlund

     BIRD71 - Timing Test Loads in [Model Spec] to Support   Peters
              PCI & PCI-X   (VOTE)

     BIRD72 - Accommodating PMOS and NMOS/PMOS Series FET    Dagostino/Ross
              Models

     BIRD73 - Fall Back Submodel                             Ross

     Other Pending BIRDS                                     Peters

     ibischk3 Bug Tracking                                   Ross
     - BUG58 -  Wrong Line Number for Missing R,L,C_pkg      Ross
                Subparameter(s)

     - BUG59 -  Crash with Decimal Points for [Package]      Mirmak
                Subparameters

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Peters

9:55 Sign Off

------------------------------

Date: Fri, 3 Aug 2001 11:33:38 -0400
From: [email-masked]
Subject: Re: about [Driver Schedule]

OUCH!  Someone is bumming!

Adam Tambone

------------------------------

Date: Wed, 08 Aug 2001 05:34:49 -0500
From: Bharat Kumar Bhatt <[email-masked]>
Subject: BIOS

Sir,

where can i find information on "driver schedule"  in IBIS.

Thanking u
bharath.

------------------------------

Date: Wed, 08 Aug 2001 15:46:34 -0400
From: Kathy Breda <[email-masked]>
Subject: IBIS Summit - 2nd call for participation and presentations

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 

- ------------------------------------------------------- 

IBIS SUMMIT  

        SECOND CALL FOR  

                PARTICIPATION & 

                        PRESENTATIONS!!!  

- ------------------------------------------------------- 

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 

             I B I S   S U M M I T   M E E T I N G 

Time/Date:    8:30 AM - 5:00 PM, Thursday, September 13, 2001 

Location:       The Crowne Plaza Hotel 

                       10 Lincoln Square 

                       Worcester, MA 

                       Tel:  (508) 791-1600 

                       Fax:  (508) 791-1796 

Content:        Presentations and Discussions 

Purpose:      Solicit and Exchange IBIS Model Related Information and Ideas. 

Sponsors:    North East Systems Associates, Inc. (NESA), 

                      IBIS Users Group 

                     Others to be determined 

                                         WE ARE LOOKING FOR ADDITIONAL SPONSORS! 

                  (contact Kathy Breda, [email-masked] 

                  or Bob Ross, [email-masked]) 

PCB Conference: September 10-14, 2001 

East            Worcester's Centrum Centre 

                    Worcester, Massachusetts 

                    See http://www.pcbeast.com/ for more information. 

BACKGROUND 

The IBIS Users Group (IBIS East) has been formed under the leadership of   

Dr. Edward Sayre from North East Systems Associates, Inc. (NESA) and has 

been meeting to consider and forward IBIS model user concerns.  As a result 

of East coast meetings, the group has developed an IBIS Accuracy Handbook 

document and has initiated the project to format Connector Models.  These 

topics plus others of current interest to the EIA IBIS Open Forum will be 

discussed at this meeting. 

This meeting will be conducted as a formal IBIS Summit Meeting.  Presentation 

are expected to be available and archived in an electronic format, and minutes 

of the meeting will be issued.  Any pending formal decisions (votes) will be 

announced at least two weeks prior to the meeting. 

CALL FOR PARTICIPANTS 

People involved in IBIS Model development, EDA tool development, and digital 

circuit design are invited to participate to the Summit meeting.  If you plan 

to participate, please register with the information below: 

  Name: 

  E-mail address: 

  Company: 

  Telephone: 

Send to: 

  Kathy Breda ([email-masked]) 

CALL FOR PRESENTATIONS 

We are seeking presentations from individuals who have IBIS experiences 

or issues. 

Format of Presentation:  Overhead Projections 

Time:                    15-30 Minutes 

Electronic Archival:     We request electronic versions so that the 

                         presentations can be archived and also made 

                         available to non-attendees.  Formats used in 

                         the past have been text, Power Point, Word,  

                         Postscript, and Acrobat.  Electronic presentations 

                         should be made available by September 7, 2001. 

                         Otherwise the presenter will be expected to provide 

                         up to 50 copies for distribution. 

If you plan a presentation, please supply 

  Title: 

  Presenter: 

  E-mail address: 

  Company: 

  Telephone: 

  Estimate Time: 

Send this to: 

  Kathy Breda ([email-masked]) 

AGENDA 

The agenda includes presentations, discussions, breaks, and a luncheon (which 

will be provided).  This will be developed as presentation proposals are 

received.  So far the following presentations are planned: 

  "A Proposal for s2ibis3", Michael Steer, North Carolina State University 

  "Modeling the Radiated Emission of Micro-controllers", Etienne Sicard, 

  National Institute of Applied Science (INSA/DEIG), France 

  "Power/Ground Simulation with IBIS Models and Pin Mapping Issues", 

  Raj Raghuram, Sigrity, Inc. 

  A user presentation - title to be determined, Bob Haller, Cereva 

  Plus IBIS Macro Language and demonstration, IBIS Connector Specification, 

  and other IBIS issues. 

LIST OF NEARBY HOTELS 

See http://www.pcbeast.com for travel directions, hotels and other 

information. 

************************************************************** 

<bold><color><param>0000,0000,8080</param><bigger>

</bigger></color></bold><excerpt>

<center>_____________________________________________________________________________________________________

</center>

<center>Kathy Breda  | Director of Marketing & Sales 

North East Systems Associates, Inc.  |  5 LAN Drive, Suite 200  |
Westford, MA 01886 

[T]  978-392-8787      [F]  978-392-8686    [W] www.nesa.com 

</center></excerpt>

------------------------------

Date: Fri, 10 Aug 2001 10:32:20 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: [email-masked] address experiencing problems, use [email-masked] g

Greetings:

   With the recent changeover to Majordomo, users have been experiencing
problems with posts to the general IBIS mailing list ([email-masked]) not
propagating to everyone on the list.  While the IBIS postmaster and the
folks in charge of the eda.org server investigate this problem, I ask
everyone to Cc: any postings you make to the IBIS reflector to the
[email-masked] mail address also.  The IBIS users reflector is
unaffected and is propagating normally.  

  To those on the IBIS users reflector I apologize for the extra mail
traffic.  Hopefully, we will have this problem resolved shortly.

  Regards,
  Stephen Peters
  Intel Corp.
  Chair EIA/IBIS Open Forum

------------------------------

Date: Sun, 12 Aug 2001 14:18:21 +0300
From: "Yoked Erlich (r58559)" <[email-masked]>
Subject: I/O buffer modeling cookbook

This is a multi-part message in MIME format.
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Hi ,

I would like to ask some questions about the 'I/O buffer modeling
cookbook'
paper (revision 2.0X) , Which I've got from 'www.eig.org' web site.

1. Is there anywhere I can find revision 3.2 cookbook?
2. I've an I/O buffer model which working in some chip pads as I/O ,
some pads as steady input and some pads as steady output.
    I would like to know if the buffer grouping is made by the buffer
type or by the pad direction?
    If buffer type is the answer so one model with I/O type in enough
for this buffer,
    If pad direction is the answer so three model is needed for this
buffer , I/O model , Input model and Output model
    ( in this case Input and Output model tests will be exactly the same
as I/O model ) .

3-6 questions are about 'Extracting Data for the [Ramp] keyword'
paragraph in the cookbook :
3. It is written that 'if the device does not have enough
     drive capability to make a significant output transition than a
higher load may be used' ,
     How much is significant output transition ?
4. it is written that ' For an open drain , measure the rise and fall
time into the load resistor and voltage used
    by the manufacture when specifying propagation delays'  , This
sentence is not clear
    what is the test structure in open drain buffer case?.
5. it is written that ' Falling edge ramp data is captured with the load
resistor tied to VCC'
    , Is VCC mean the pmos Driver source voltage (pad voltage) or low
voltage?
6. It is written that 'simulations are performed with C_comp included in
the circuit' , This sentence is not clear.
    As I understood C_comp is the capacitance seen when looking from the
pad back into the buffer ,
    It is written that C_comp should be added to the simulation , but
C_comp is not a capacitor it is capacitance measurement.

7. In 'Ground Clamp' paragraph it is written that 'The data in table
must cover the range of -Vcc to Vcc ' ,
    Isn't it suppose to be -Vcc to 2*Vcc ?
8. In 'pulldn' paragraph it is written 'If the buffer is a 3-state
device then first subtract the ground clamp current
    from the pulldown current then enter the result into the [pulldown]
table' ,
    first , it is written above the graph 'Pullup I/V curve after
subtraction of ground clamp currents' Which is probably mistake.
    second , Should I replace the pulldn results in Ibis model file
after the subtraction?
9. In 'Power Clamp' It is written that 'the data in the table must cover
the range of vcc to vcc*2' ,
    Isn't the range suppose to be -Vcc to 2*Vcc ?

- --

With regards,

Yoked.

_____________________________________
E-mail:       [email-masked]
Tel: 972-9-9522482 Fax: 972-9-9522888
WIRELESS     CIRCUIT  - IO      GROUP
MOTOROLA     SEMICONDUCTOR     ISRAEL

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<html>
Hi ,
<p>I would like to ask some questions about the 'I/O buffer modeling&nbsp;
cookbook'
<br>paper (revision 2.0X) , Which I've got from 'www.eig.org' web site.
<p>1. Is there anywhere I can find revision 3.2 cookbook?
<br>2. I've an I/O buffer model which working in some chip pads as I/O
, some pads as steady input and some pads as steady output.
<br>&nbsp;&nbsp;&nbsp; I would like to know if the buffer grouping is made
by the buffer type or by the pad direction?
<br>&nbsp;&nbsp;&nbsp; If buffer type is the answer so one model with I/O
type in enough for this buffer,
<br>&nbsp;&nbsp;&nbsp; If pad direction is the answer so three model is
needed for this buffer , I/O model , Input model and Output model
<br>&nbsp;&nbsp;&nbsp; ( in this case Input and Output model tests will
be exactly the same as I/O model ) .
<p><font color="#3333FF">3-6 questions are about 'Extracting Data for the
[Ramp] keyword' paragraph in the cookbook :</font>
<br>3. It is written that 'if the device does not have enough
<br>&nbsp;&nbsp;&nbsp;&nbsp; drive capability to make a significant output
transition than a higher load may be used' ,
<br>&nbsp;&nbsp;&nbsp;&nbsp; How much is significant output transition
?
<br>4. it is written that ' For an open drain , measure the rise and fall
time into the load resistor and voltage used
<br>&nbsp;&nbsp;&nbsp; by the manufacture when specifying propagation delays'&nbsp;
, This sentence is not clear
<br>&nbsp;&nbsp;&nbsp; what is the test structure in open drain buffer
case?.
<br>5. it is written that ' Falling edge ramp data is captured with the
load resistor tied to VCC'
<br>&nbsp;&nbsp;&nbsp; , Is VCC mean the pmos Driver source voltage (pad
voltage) or low voltage?
<br>6. It is written that 'simulations are performed with C_comp included
in the circuit' , This sentence is not clear.
<br>&nbsp;&nbsp;&nbsp; As I understood C_comp is the capacitance seen when
looking from the pad back into the buffer ,
<br>&nbsp;&nbsp;&nbsp; It is written that C_comp should be added to the
simulation , but C_comp is not a capacitor it is capacitance measurement.
<p>7. In 'Ground Clamp' paragraph it is written that 'The data in table
must cover the range of -Vcc to Vcc ' ,
<br>&nbsp;&nbsp;&nbsp; Isn't it suppose to be -Vcc to 2*Vcc ?
<br>8. In 'pulldn' paragraph it is written 'If the buffer is a 3-state
device then first subtract the ground clamp current
<br>&nbsp;&nbsp;&nbsp; from the pulldown current then enter the result
into the [pulldown] table' ,
<br>&nbsp;&nbsp;&nbsp; first , it is written above the graph 'Pullup I/V
curve after subtraction of ground clamp currents' Which is probably mistake.
<br>&nbsp;&nbsp;&nbsp; second , Should I replace the pulldn results in
Ibis model file after the subtraction?
<br>9. In 'Power Clamp' It is written that 'the data in the table must
cover the range of vcc to vcc*2' ,
<br>&nbsp;&nbsp;&nbsp; Isn't the range suppose to be -Vcc to 2*Vcc ?
<pre>--

With regards,

Yoked.

_____________________________________
E-mail:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; [email-masked]
Tel: 972-9-9522482 Fax: 972-9-9522888
WIRELESS&nbsp;&nbsp;&nbsp;&nbsp; CIRCUIT&nbsp; - IO&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; GROUP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
MOTOROLA&nbsp;&nbsp;&nbsp;&nbsp; SEMICONDUCTOR&nbsp;&nbsp;&nbsp;&nbsp; ISRAEL</pre>
&nbsp;</html>

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------------------------------

Date: Mon, 13 Aug 2001 15:14:54 -0700
From: "Ross, Bob" <[email-masked]>
Subject: IBIS - I/O Buffer Modeling Cookbook

Hello Yoked:

We are temporarily having reflector e-mail problems,
so you message did not get sent to the general list.

However, I am responding on the ibis-users reflector
and copying Stephen Peters, who authored the Cookbook.
My responses are in your text noted by "*" marks.  These
are brief responses without looking at the Cookbook
document.  I am trying to convey what was intended,
not any editorial issues regarding how it is documented.

Bob Ross
Mentor Graphics

- ---------------------

Subject: I/O buffer modeling cookbook
From: Yoked Erlich (r58559) ([email-masked])
Date: Sun Aug 12 2001 - 04:18:21 PDT 

Hi , 

I would like to ask some questions about the 'I/O buffer modeling 
cookbook' 
paper (revision 2.0X) , Which I've got from 'www.eig.org' web site. 

1. Is there anywhere I can find revision 3.2 cookbook? 

* No, a Version 3.2 Cookbook has not been written.  Cookbook 2 was
intended to cover Version 3.2 features, but we never got that far.

2. I've an I/O buffer model which working in some chip pads as I/O , 
some pads as steady input and some pads as steady output. 
    I would like to know if the buffer grouping is made by the buffer 
type or by the pad direction? 
    If buffer type is the answer so one model with I/O type in enough 
for this buffer, 
    If pad direction is the answer so three model is needed for this 
buffer , I/O model , Input model and Output model 
    ( in this case Input and Output model tests will be exactly the same 
as I/O model ) . 

* If the buffer is truely an I/O, then it should be provided and
documented as I/O.  A user might have additional knowledge that
certain I/O buffers are configured only as Input or Output buffers.
It would be permissible to modify that instance of the model and
just change the Model_type.  That would help the EDA tool do
only the simulations that are relevant for the design.

3-6 questions are about 'Extracting Data for the [Ramp] keyword' 
paragraph in the cookbook : 
3. It is written that 'if the device does not have enough 
     drive capability to make a significant output transition than a 
higher load may be used' , 
     How much is significant output transition ? 

* I do not have any hard guideline.  I prefer impedances in the
order of magnitude of transmission line loads since that is a
typical high-speed design application.  That ususally captures
a fast edge that would be seen with a PCB interconnect.

* This makes no sense for certain weak buffers which would
require multiple reflections to change from one state to the
other for an open line.  If the application is not high-speed,
then it does not manner.   I would guess that a higher value
load might be OK for a driver source impedance > 300 ohms. 
Others might have different ideas. 

4. it is written that ' For an open drain , measure the rise and fall 
time into the load resistor and voltage used 
    by the manufacture when specifying propagation delays' , This 
sentence is not clear 
    what is the test structure in open drain buffer case?. 

* This is ambiguous.  I prefer low impedance (50 ohm) pullups to
capture a faster edge.  This may be in the order of magnitude of
the load seen during the intial part of the transition when the
device is connected through a PCB interconnect.

5. it is written that ' Falling edge ramp data is captured with the load 
resistor tied to VCC' 
    , Is VCC mean the pmos Driver source voltage (pad voltage) or low 
voltage? 

* This means that one end of the load resistor is connected to 
Vcc, and the other end is connected to the output pad.

6. It is written that 'simulations are performed with C_comp included in 
the circuit' , This sentence is not clear. 
    As I understood C_comp is the capacitance seen when looking from the 
pad back into the buffer , 
    It is written that C_comp should be added to the simulation , but 
C_comp is not a capacitor it is capacitance measurement.

* It is difficult to de-embed the die capacitance information from a
Spice net list (since some of the contribution is due to paramaters
within the transistor/diode models) or from a real physical measurements.

* So the intent is to clarify that the die capacitance is already
included in any waveform extraction.  Since C_comp is a first order
approximation of the die capacitance, its effects should be included
in an EDA tool simulation.  I have not looked at the specific
wording, but I assume this is confusing.

7. In 'Ground Clamp' paragraph it is written that 'The data in table 
must cover the range of -Vcc to Vcc ' , 
    Isn't it suppose to be -Vcc to 2*Vcc ? 

* This response also covers 9.

* No, the minimum range is intended to be -vcc to vcc.  The Power
Clamp covers from vcc to 2vcc.  When this minimum range was
established, most Inputs were at negligle current at Vcc and the
slope (current vs voltage) was also nearly 0.  So concatenation
of the tables produced the same effect as extrapolation.

* It is allowed to extend the clamp ranges beyond the specified
range.  In some cases you should do so, especially if you are
including the effect of an internal terminator.  In such cases,
the conditions above are not met, and I prefer -vcc to 2vcc for
both clamp tables.  Care must be taken so that
currents are not double counted.  However, for many situations,
the "minimal" IBIS guidelines are sufficient.

8. In 'pulldn' paragraph it is written 'If the buffer is a 3-state 
device then first subtract the ground clamp current 
    from the pulldown current then enter the result into the [pulldown] 
table' , 
    first , it is written above the graph 'Pullup I/V curve after 
subtraction of ground clamp currents' Which is probably mistake. 
    second , Should I replace the pulldn results in Ibis model file 
after the subtraction?

* What is entered in the [Pulldown] table is the result after
subtraction.

9. In 'Power Clamp' It is written that 'the data in the table must cover 
the range of vcc to vcc*2' , 
    Isn't the range suppose to be -Vcc to 2*Vcc ? 

* See 7 above.

- --
With regards,
Yoked.
_____________________________________
E-mail:       [email-masked]
Tel: 972-9-9522482 Fax: 972-9-9522888
WIRELESS     CIRCUIT  - IO      GROUP
MOTOROLA     SEMICONDUCTOR     ISRAEL

------------------------------

Date: Mon, 13 Aug 2001 17:00:01 -0700
From: "John Angulo" <[email-masked]>
Subject: IBIS Open Forum now under Majordomo

Hello,

All members of the IBIS Open Forum will soon receive welcome messages from
the new Majordomo list administration software.  There is no change in your
list membership status - this is just an automatic message resulting from
the change in the underlying mail administration.

As the Chair of the EIA/IBIS Open Forum, Stephen Peters, said last week, we
have been having some initial trouble with Majordomo.  Unfortunately,
messages posted to [email-masked] since July 24 have not been sent to the Open
Forum members.  These messages have not been lost, but have been archived
at:

http://www.eda.org/ibis/hm/

You can visit this hypermail archive to view all posted messages.

Note that the IBIS Users Group Reflector is still running smoothly under the
old mail system, and that most of the Open Forum messages are cross posted
there.

New postings to [email-masked] should now be forwarded to all Open Forum
members.  For the time being, however, we ask that you cross post all
messages to [email-masked] to [email-masked].

There are several other issues we are working to resolve.  Specifically, you
will notice that the title provided by Majordomo in your welcome email and
on the hypermail archive should be changed from "IBIS - IEEE DASC IBIS
Standard Activity" to "EIA/IBIS Standards Committee Activity".  Also, the
text drawings in messages on the hypermail archive are corrupted by
font/whitespace conversions.  Please send any questions about this message
or suggestions for mailing list improvements to:

[email-masked]

Thanks for your patience during this transition,
John Angulo
IBIS Open Forum Postmaster

------------------------------

Date: Tue, 14 Aug 2001 09:07:41 -0700
From: Guy de Burgh <[email-masked]>
Subject: IBIS Open Forum Minutes (8/10/01)

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DATE: 8/14/01

SUBJECT: August 10, 2001 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2001 PARTICIPANTS LIST:
3Com (& CommWorks)             Roy Leventhal
Ansoft Corporation             (Eric Bracken)
Apple Computer                 John Figueroa
Applied Simulation Technology  [Raj Raghuram], Norio Matsui, Fred Balistreri
Avanti                         (Chen Hongyu)
Cadence Design                 [Ian Dodd], Patrick Dos Santos, Heiko Dudek,
                               Lynne Green*, Lance Wang
Cisco Systems                  Syed Huq, Lungfu Chen
Cypress Semiconductor          (Rajesh Manapat)
EMC Corporation                Brian Arsenault, Jinhua Chen
Fairchild Semiconductor        Adam Tambone
Huawei Technologies            Rachild Chen
IBM                            Michael Cohen, Greg Edlund*, Wes Martin,
                               Yeon-Chang Hahm, Bill DeVey, Pravin Patel
Innoveda (& HyperLynx)         Guy de Burgh*, John Angulo*, Cary Mandel, 
                               Matthew Flora, Steve Kaufer
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Dave Lorang,
                               Michael Mirmak*, Qinglun Chen, Will Hobbs,
                               Wei-hsing Huang
LSI Logic                      Larry Barnes
Mentor Graphics                Bob Ross*, Tom Dagostino*, Chris Reid,
                               Mike Donnelly, Hazem Hegazy, Tony Dunbar,
                               Griff Derryberry, Dan Lake, Sherif Hammad,
                               Mohammed Korany, Weston Beal, Chris Swaim,
                               Ali Samii, Eric Ronger, Karine Loudet,
                               Daisaku Shiga, Kenji Kushima
Micron Technology              Randy Wolff*, Yong Phan*
Mitsubishi                     Pat Hefferan
Molex Incorporated             Gus Panella, Brian O'Malley
National Semiconductor         Milt Schwartz
North East Systems Associates  Edward Sayre
Philips Semiconductor          Zack Ciccone, Rob Mataheroe
Quantic EMC                    (Mike Ventham)
Signal Integrity Software      Douglas Burns, Barry Katz, Walter Katz
Sigrity                        Raj Raghuram*
SiQual                         Scott McMorrow, Rob Hinz, Bernard Voss,
                               Chris Brewster
Texas Instruments              Thomas Fisher, Stephen Nolan, Ramzi Ammar,
                               Jean Claude Perrin, Moshiul Haque
Time Domain Analysis Systems   Dima Smolyansky, Steve Corey
Tyco Electronics               (Russell Moser)
Via Technologies               (Weber Chuang)
Zuken (& Incases)              John Berrie, Ralf Bruening

OTHER PARTICIPANTS IN 2001:
Actel Corporation              Silvia Montoya
Acuson                         Kim Helliwell
AMCC                           Jeff Smith
ASIS Ltd                       David Wright
Brocade Communications         Robert Badal
BMW                            Friedrich Hasinger
Cereva Networks                Bob Haller
Compaq                         [Peter LaFlamme], Ron Bellomio, Quang Dam,
                               Bill Ham
EADS Airbus Industry           Claude Huet
  (Aerospatiale)
EFM                            Ekkehard Miersch, Horle Raines
EIA                            Cecilia Fleming*
Ericsson Radio Systems         Anders Ekholm
FCI                            Sercu Stefaan
Foundary Networks              Bertram Chan
Framatom Conectors             Danny Morlion
Fraunhofer Institute           Mariusz Faferko, Peter Kralicek
  Reliability and
  Integration
Fujitsu Ltd                    Tadashi Arai, Takeshi Murakami
Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt
Hyundai Electronics            Jongho Kang
Idaho State University         Al Davis
Infineon Technologies          Christian Sporrer
Intrinsix Corporation          Steven Chin
Motorola                       (Rick Kingen)
National Institute of Applied  Etienne Sicard
  Science (INSA)
Nokia                          Tapani von Ravner, Mika Castren,
                               Janne Uusitalo
Nortel Networks                Calvin Trowell
Oak Technology                 Darmin Jin
Plexus Technology Group        Joseph Socha
Siemens (& Automotive) AG      Bernhard Unger, Helmut Katzier, Katja Koller,
                               Wolfram Meyer, Eckhard Lenski, Gerald
Bannert,
                               Burkhard Muller, Christian Marot,
                               Manfred Maurer, Amir Motamedi, Hans
Pichlmaier
Sintecs                        Hans Klos
STMicroelectronics             Peter Hirt, Fabrice Boissieres
Sun                            Adrian Udenze
Toshiba Corp.                  Hirokaza Kato, Yuichi Koga, Toshio Sudo
Xilinx                         Susan Wu

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are
as follows:

  Date                Bridge Number    Reservation #    Passcode
  August 31, 2001     (916) 356-2663   2                4779396  
  Thursday, September 13, 2001 IBIS Summit Meeting, No Phone Bridge

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after.  When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES ------------------------------------

INTRODUCTIONS AND MEETING QUORUM
No new members.

MEMBERSHIP UPDATE AND TREASURER'S REPORT
Stephen Peters reported that Sigrity has become an official EIA IBIS Member
and Cypress Semiconductor has renewed its membership, making 31 members to
date.  They are now listed as Voting Members.

REVIEW OF MINUTES AND AR'S
The July 20, 2001 IBIS Minutes were approved without change.

The ARs will be discussed during the meeting.

MISCELLANY/ANNOUNCEMENTS
None.

PRESS AND WEB PAGE UPDATES
Bob Ross reported that the August 2001 issue of Integrated System Design
(ISD) has the article "Signal Integrity Analysis Reaps Huge Dividends for
Network Board Designers" by Hans Pichlmaier and Heinz Harmut Ibowski
on pp. 26-30.  The article includes discussion of IBIS and IBIS modeling
issues.  It can be found at:

  http://www.isdmag.com/story/OEG20010803S0027

Bob also put some uploaded some old IBIS material for historical interest.
Some older IBIS Summit meeting material (mostly minutes) from 1993 through
1996 are under

  http://www.eda.org/pub/ibis/summits/

The .zip files containing the sets of minutes for 1993 and 1994 are expanded
under
  
http://www.eda.org/pub/ibis/minutes/

Bob noted that Syed Huq has done some more Roster updates and updated the
JEITA IMIC link to be listed later.

NEW MODELS AVAILABLE, LIBRARY UPDATE
Bob Ross reported on some new and changed IBIS Model links:

Elpida Memory, Inc. (Distributes Hitachi and NEC Memories):

  http://www.elpida-memory.com/en/products/model.html

Hitachi DRAM and Modules are now under (URL is split to avoid truncation):

  http://www.hitachi.co.jp/Sicd/English/Products/memory/simulation/
     dram_simulatee.html

I-Cube, Inc. has IBIS models under Products, Design Support Downloads:

  http://www.icube.com/

Music Semiconductor's IBIS models are moved to:

  http://www.music-ic.com/index.php?section1=support&contentid=support_ibis

OPENS FOR NEW ISSUES
Bob Ross - DesignCon 2002 IBIS Summit Meeting. This is discussed below.

INTERNATIONAL/EXTERNAL PROGRESS
- - IEC 62014-1 (IBIS Version 3.2) - Cecilia Fleming stated that the document
is available and can be found under the following links (split into two
lines to avoid mailer truncation).

    http://www.iec.ch/cgi-bin/procgi.pl/www/
      iecwww.p?wwwlang=e&wwwprog=TCpubs.p&committee=TC&number=93

It can be purchased for 136 Swiss Francs.  The IEC 62014-1 agenda item
will now be dropped.

- - JEITA ED-5302 Standard for I/O Interface Model for Integrated Circuits
  (IMIC) - Bob Ross reported EIAJ has merged with JEITA and that the IMIC
  document is now located under:

    http://tsc.jeita.or.jp/eds/IOPG.htm
                                       
- - IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal
  (formerly, IEC 93/67/NP IBIS and EMC Simulation) - Stephen Peters
  stated that Etienne Sicard plans to present the work at the
  September 13, 2001 IBIS Summit.  This will be discussed later in the meeting.

- - JEDEC JC-16 - Modeling and Testing - No report.

- - T10, Project 1414-DT - SCSI Signal Modeling (a Technical Committee of the
  National Committee for Information Technology (NCITS)) - No report.

PCB CONFERENCE EAST 2001 IBIS SUMMIT MEETING PLANS
Stephen Peters reported that an IBIS Summit Meeting is planned for Thursday,
September 13, 2001 in Worcester, Massachusetts at the Crowne Plaza Hotel
near the PCB Conference East 2001 show.  The meeting follows the day after
the trade show portion of the show.  The Upcoming events link of the IBIS Home
page already contains the sign-up information and hotel information.  Free
lunch and refreshments are included.

Stephen stated that the first and second announcements have been sent by 
Kathy Breda of NESA.  Currently 13 or 14 attendees have signed up.  
Stephen asked, and most of the officers are planning to attend.

To date, four presentations are planned (titles may change):

  "Modeling the Radiated Emission of Micro-controllers", Etienne Sicard,
     National Institute of Applied Science (INSA) in France

  "A Proposal for s2ibis3", Michael Steer, North Carolina State University

  "Power/Ground Simulation with IBIS Models and Pin Mapping Issues", 
     Raj Raghuram, Sigrity, Inc.  

  Title to be determined related to being a user of IBIS models
     Bob Haller, Cereva Networks

Stephen stated that Lynne Green of the futures committee will present
several IBIS-X examples for discussion and Stephen will discuss IBIS-X
and Connector Specification progress.  Two other presentations on various
issues are pending.

Stephen and Bob Ross discussed the funding issue.  Economic conditions are
tight this year.  Mentor Graphics is still willing to commit to sharing
either 1/3 of the expenses with others or giving a fixed amount.  The overall
meeting cost including lunch is estimated to be around $2,000.  Another
company also expressed interest.  Bob stated that the only benefit would be
co-sponsorship recognition on the announcements and at the meeting and
possibly having your name on a banner at the meeting.  Allowing co-sponsors
to give product demonstrations would not be offered since this was not being
offered to all interested companies.

Stephen proposed that the EIA IBIS Open Forum pick up the remaining balance.
Bob seconded the proposal.  After some discussion, the Committee voted
unanimously by roll call vote to accept the proposal.

DESIGNCON 2002 IBIS SUMMIT MEETING (New Agenda Item)
Bob Ross reported early planning is underway for an IBIS Summit Meeting
on Monday, January 28, 2002 in Santa Clara, California and associated with
DesignCon 2002.  We expect to be an Associate Sponsor, as in the past.

Bob asked whether we should have a passive booth.  Guy de Burgh stated that
Innoveda is willing to supply and handle the booth setup.

In the past, National Semiconductor has sponsored the lunch.  Milt Schwartz
stated that he is still investigating the possibility this year.  Because of
the economy, it may take a while to find out.  Bob stated that we do not
need an immediate answer.  However, other companies are welcome to be a 
co-sponsor.  

IBIS MODEL REVIEW COMMITTEE DISCUSSION
Bob Ross will take over short term until we find a replacement.  In the 
mean time, John Angulo will transfer any outstanding information to Bob.

MAJORDOMO UPDATE
John Angulo reported that [email-masked] is now being distributed under
majordomo.  Some details and settings regarding archiving are still being
worked out, but since July 24, 2001, the [email-masked] e-mail is archived
under

  http://www.eda.org/pub/ibis/hm/

John indicated that he is still working on issues including some cosmetic
formatting details and attachment references (attachments are permitted and
are stored in a lower directory).  Bob Ross stated that the archive is in
HTML format which loses some text spacing alignment detail.  Also Bob
stated that some messages appear not to have been delivered, indicating
that there are still some glitches.

John stated that the subscription process through majordomo involves a
response, and a response to the response to validate the correct address.
Even with significant overlap, we still plan to maintain two lists, if
possible.  One is the normal business list ([email-masked]), and the other is
the users list ([email-masked]).

John stated that we have not received a significant amount of spam through
the lists at this time.  Bob proposed that the list remain open at this time
to minimize the disruption.  We can trap some spam mail, if needed.

John stated that he has had good response with the list administrators, and
will probably complete the conversion in a few weeks.  Stephen Peters thanked
John for his work.

CONNECTOR PROPOSAL REVIEW
Stephen Peters reported that the Connector review committee meet July 24
and 31, and again August 7th.  The committee is continuing with the review
of the specification, including a couple of specific keywords that were
added.  Bob Ross also mentioned that, starting August 14th, the connector
meeting has been expanded to two hours weekly. 

IBIS FUTURES (IBIS-X, API, BIRDxx)
Stephen Peters reported that the IBIS futures committee meet July 24, 31,
and August 3.  Stephen also noted that starting August 17th the meetings
will change days to Thursday afternoon.

Stephen reported that the committee has finalized the list of primitive
element for IBIS-X, and Lynne Green will be documenting them in the IBIS-X
Macro Language Reference manual.  The committee also reviewed a proposal to 
restructure the IBIS-X data file.  After considerable debate, the committee 
decided to postpone major restructuring until after the initial IBIS-X
specification has been released. 

Stephen then gave the background regarding the funding proposal for an 
IBIS-X parser.  Al Davis has offered his parser, under several different 
license arrangements, for use by the committee. Stephen stated that he 
felt the IBIS Open Forum must retain control of the source of any 
"official" IBIS-X parser, and Bob Ross concurred.  A lively discussion 
ensued, in which several people noted that the IBIS-X parser should go 
through a bidding process as was done for the IBIS 3.2 parser. It was noted 
that we cannot do this until the current IBIS-X specification is stable.
Several people indicated that there might be a business conflict of interest,
and Bob Ross stated that we need to adopt an arms length relationship
regarding any financial or business aspects related to any unofficial parser
development activity.

BIRD70.4 - GOLDEN WAVEFORMS
Stephen Peters introduced BIRD70.4 that Greg Edlund issued on July 23, 2001.
(Bob Ross discovered that the date on uploaded BIRD70.4 was incorrect,
leading to some initial confusion.)  

Stephen noted that while the waveform tables in this bird were assumed to 
follow the same rules for construction as the existing 
[Rising Waveform]/[Falling Waveform] keywords, the proposed bird did not
state this explicitly.  Greg agreed to adding a sentence to make this explicit. 

Both Lynne Green and Stephen mentioned that the location where waveform 
data was measured was not explicitly defined.  After discussion Greg agreed 
to add wording that clarified that 'near' data is measured at the driver pad
while 'far' data is measured as the receiver pad.

Bob Ross noted that if Test_data_type is Differential, the bird did not state
which driver output (inverting or non-inverting) a single ended waveform would
be generated from.  After discussion Greg agreed to clarify this by explicitly
specifying the non-inverting output.  Finally, Bob observed that the use of the
term 'SPICE' when describing reference waveforms was not clear.  Bob proposed
using the term 'reference waveforms', and after discussion this was agreed to. 

Stephen then called for a vote with the above changes.  Bird 70.4, as amended,
was accepted unanimously by roll call vote. 

AR - Greg Edlund issue BIRD70.5 with the approved changes. [Done]

BIRD71 - TIMING TEST LOADS IN [Model Spec] TO SUPPORT PCI & PCI-X
Stephen Peters then introduced Bird 71 for a final vote.  Bob Ross 
noted a few minor editorial changes which Stephen agreed to.  Stephen
then called for a vote.  Bird 71 was accepted unanimously by roll call
vote.

BIRD72 - ACCOMMODATING PMOS AND NMOS/PMOS SERIES FET MODELS
Stephen Peters deferred discussion because not everyone received a copy due
to mailer problems.  This will be discussed at the next meeting.

AR - Bob Ross will reissue BIRD72 on both reflectors.

BIRD73 - FALL BACK SUBMODEL
Stephen Peters deferred discussion because not everyone received a copy due
to mailer problems.  This will be discussed at the next meeting.

AR - Bob Ross will reissue BIRD72 on both reflectors.

AR - Stephen Peters will issue a notice on the ibis-users reflector stating
that the main ibis reflector is not propagating all posts. [Done]

IBISCHK3 BUG TRACKING
Bob Ross reported that Atul Agarwal will plans to do the ibischk3 parser
update for BUGs 48-56 by the middle to end of September, 2001.  This may not
include BUG54, which he does not understand.

BUG58 - Wrong Bug Number for Missing R,L,C_pkg Subparameters(s)
Bob Ross discussed BUG58 submitted by Lance Wang.  The Error message
issued for a missing required subparameter line such as L_pkg is not 
close to the problem.  For example, the error line number was not for
the next keyword, but the following keyword.

After some discussion, BUG58 was classified as ANNOYING, LOW, and OPEN.
We will plan to fix this unless we find some difficult technical issues.

BUG59 - Crash with Decimal Points for [Package] Subparameters
Michael Mirmak introduced BUG59 by stating that ibischk3 crashed on a 
Windows 2000 system only when a subparameter numerical entry was
incorrectly entered (two decimal points for a C_pkg value).  Michael also
stated that Bob Ross could not reproduce the crash on a Windows NT system.
Instead, Bob did observe that the error messages were different on Unix
workstations.  The NT (DOS mode) reported an extra PROGRAM BUG and also
another related ERROR message, but it did not cause ibischk3 to crash or
terminate prematurely.

Lynne Green and John Angulo will try the BUG59 test case independently.

BUG59 was classified as ANNOYING, LOW, and OPEN.  More investigation will
be done on it.  We need to at least resolve the "PROGRAM BUG" report since
that is a soft program failure message.  Stephen Peters stated that someone
besides Atul Agarwal may need to investigate this if Atul does not have
access to the Windows NT system.

NEXT MEETING:
The next teleconference meeting will be on Friday, August 31, 2001, from 
8:00 AM to 10:00 AM.

==============================================================================
                                      NOTES

IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
            [email-masked]
            Senior Hardware Engineer, Intel Corporation
            M/S JF4-215
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

VICE CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            [email-masked]
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

SECRETARY:  Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN:  Roy Leventhal (837) 797-2152, Fax: (847) 222-2799
            [email-masked]
            Senior Engineer, CommWorks Corp. (a wholly owned 3Com subsidiary)
            1800 W. Central Rd.
            Mt. Prospect, IL 60056-2293

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            [email-masked]
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
            [email-masked]
            Development Engineer, Innoveda
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  [email-masked]
      To join, change, or drop from either the IBIS Open Forum Reflector
      ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
      or both.  State your request.

  [email-masked]
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  [email-masked]
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  [email-masked]
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  [email-masked]
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results.  You can get on via FTP anonymous.

===============================================================================

- --------------7362F29A2F8C55942DFCB8BB--

------------------------------

Date: Tue, 21 Aug 2001 17:39:43 +0300
From: yoked erlich <[email-masked]>
Subject: Re: IBIS - I/O Buffer Modeling Cookbook

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Hi ,

There are another few questions about ibischk3 results:

1. I've got the next warning:
 WARNING - [Model] iovb has no description of the buffer's high state
                    DC drive characteristics (no [Pullup] table).  This
warning
                    can be silenced by changing the Model_type or by adding
a
                    [Pullup] table.
This cell ('iovb') is 'Open_drain' type which according to Ibis maker cook
book do not
suppose to have [Pullup] table , only the [pulldown],[gnd_clamp] and
[power_clamp] tables ,
What do you think might be the reason of this error ?.

2. I've got the next warning:
WARNING (line  427) - Pulldown Typical data is non-monotonic
WARNING (line  427) - Pulldown Maximum data is non-monotonic
WARNING (line  428) - Pulldown Minimum data is non-monotonic
according to pulldn subtraction gnd_clamp cookbook and standard instructions
,
it is impossible to get monotonic data.
It is even mentioned in the standard that the [pulldn] or  [pullup] tables
might be non-monotonic.
Is it all right to ignore this warning ?

With regards

Yoked.
"Ross, Bob" wrote:

> Hello Yoked:
>
> We are temporarily having reflector e-mail problems,
> so you message did not get sent to the general list.
>
> However, I am responding on the ibis-users reflector
> and copying Stephen Peters, who authored the Cookbook.
> My responses are in your text noted by "*" marks.  These
> are brief responses without looking at the Cookbook
> document.  I am trying to convey what was intended,
> not any editorial issues regarding how it is documented.
>
> Bob Ross
> Mentor Graphics
>
> ---------------------
>
> Subject: I/O buffer modeling cookbook
> From: Yoked Erlich (r58559) ([email-masked])
> Date: Sun Aug 12 2001 - 04:18:21 PDT
>
> Hi ,
>
> I would like to ask some questions about the 'I/O buffer modeling
> cookbook'
> paper (revision 2.0X) , Which I've got from 'www.eig.org' web site.
>
> 1. Is there anywhere I can find revision 3.2 cookbook?
>
> * No, a Version 3.2 Cookbook has not been written.  Cookbook 2 was
> intended to cover Version 3.2 features, but we never got that far.
>
> 2. I've an I/O buffer model which working in some chip pads as I/O ,
> some pads as steady input and some pads as steady output.
>     I would like to know if the buffer grouping is made by the buffer
> type or by the pad direction?
>     If buffer type is the answer so one model with I/O type in enough
> for this buffer,
>     If pad direction is the answer so three model is needed for this
> buffer , I/O model , Input model and Output model
>     ( in this case Input and Output model tests will be exactly the same
> as I/O model ) .
>
> * If the buffer is truely an I/O, then it should be provided and
> documented as I/O.  A user might have additional knowledge that
> certain I/O buffers are configured only as Input or Output buffers.
> It would be permissible to modify that instance of the model and
> just change the Model_type.  That would help the EDA tool do
> only the simulations that are relevant for the design.
>
> 3-6 questions are about 'Extracting Data for the [Ramp] keyword'
> paragraph in the cookbook :
> 3. It is written that 'if the device does not have enough
>      drive capability to make a significant output transition than a
> higher load may be used' ,
>      How much is significant output transition ?
>
> * I do not have any hard guideline.  I prefer impedances in the
> order of magnitude of transmission line loads since that is a
> typical high-speed design application.  That ususally captures
> a fast edge that would be seen with a PCB interconnect.
>
> * This makes no sense for certain weak buffers which would
> require multiple reflections to change from one state to the
> other for an open line.  If the application is not high-speed,
> then it does not manner.   I would guess that a higher value
> load might be OK for a driver source impedance > 300 ohms.
> Others might have different ideas.
>
> 4. it is written that ' For an open drain , measure the rise and fall
> time into the load resistor and voltage used
>     by the manufacture when specifying propagation delays' , This
> sentence is not clear
>     what is the test structure in open drain buffer case?.
>
> * This is ambiguous.  I prefer low impedance (50 ohm) pullups to
> capture a faster edge.  This may be in the order of magnitude of
> the load seen during the intial part of the transition when the
> device is connected through a PCB interconnect.
>
> 5. it is written that ' Falling edge ramp data is captured with the load
> resistor tied to VCC'
>     , Is VCC mean the pmos Driver source voltage (pad voltage) or low
> voltage?
>
> * This means that one end of the load resistor is connected to
> Vcc, and the other end is connected to the output pad.
>
> 6. It is written that 'simulations are performed with C_comp included in
> the circuit' , This sentence is not clear.
>     As I understood C_comp is the capacitance seen when looking from the
> pad back into the buffer ,
>     It is written that C_comp should be added to the simulation , but
> C_comp is not a capacitor it is capacitance measurement.
>
> * It is difficult to de-embed the die capacitance information from a
> Spice net list (since some of the contribution is due to paramaters
> within the transistor/diode models) or from a real physical measurements.
>
> * So the intent is to clarify that the die capacitance is already
> included in any waveform extraction.  Since C_comp is a first order
> approximation of the die capacitance, its effects should be included
> in an EDA tool simulation.  I have not looked at the specific
> wording, but I assume this is confusing.
>
> 7. In 'Ground Clamp' paragraph it is written that 'The data in table
> must cover the range of -Vcc to Vcc ' ,
>     Isn't it suppose to be -Vcc to 2*Vcc ?
>
> * This response also covers 9.
>
> * No, the minimum range is intended to be -vcc to vcc.  The Power
> Clamp covers from vcc to 2vcc.  When this minimum range was
> established, most Inputs were at negligle current at Vcc and the
> slope (current vs voltage) was also nearly 0.  So concatenation
> of the tables produced the same effect as extrapolation.
>
> * It is allowed to extend the clamp ranges beyond the specified
> range.  In some cases you should do so, especially if you are
> including the effect of an internal terminator.  In such cases,
> the conditions above are not met, and I prefer -vcc to 2vcc for
> both clamp tables.  Care must be taken so that
> currents are not double counted.  However, for many situations,
> the "minimal" IBIS guidelines are sufficient.
>
> 8. In 'pulldn' paragraph it is written 'If the buffer is a 3-state
> device then first subtract the ground clamp current
>     from the pulldown current then enter the result into the [pulldown]
> table' ,
>     first , it is written above the graph 'Pullup I/V curve after
> subtraction of ground clamp currents' Which is probably mistake.
>     second , Should I replace the pulldn results in Ibis model file
> after the subtraction?
>
> * What is entered in the [Pulldown] table is the result after
> subtraction.
>
> 9. In 'Power Clamp' It is written that 'the data in the table must cover
> the range of vcc to vcc*2' ,
>     Isn't the range suppose to be -Vcc to 2*Vcc ?
>
> * See 7 above.
>
> --
> With regards,
> Yoked.
> _____________________________________
> E-mail:       [email-masked]
> Tel: 972-9-9522482 Fax: 972-9-9522888
> WIRELESS     CIRCUIT  - IO      GROUP
> MOTOROLA     SEMICONDUCTOR     ISRAEL

- --

With regards,

Yoked.

_____________________________________
E-mail:           [email-masked]
Tel: 972-9-9522482 Fax: 972-9-9522888
WIRELESS     CIRCUIT  - IO      GROUP
MOTOROLA     SEMICONDUCTOR     ISRAEL

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<html>
Hi ,
<p>There are another few questions about ibischk3 results:
<p>1. I've got the next warning:
<br><font color="#FF0000">&nbsp;WARNING - [Model] iovb has no description
of the buffer's high state</font>
<br><font color="#FF0000">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
DC drive characteristics (no [Pullup] table).&nbsp; This warning</font>
<br><font color="#FF0000">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
can be silenced by changing the Model_type or by adding a</font>
<br><font color="#FF0000">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
[Pullup] table.</font>
<br>This cell ('iovb') is 'Open_drain' type which according to Ibis maker
cook book do not
<br>suppose to have [Pullup] table , only the [pulldown],[gnd_clamp] and
[power_clamp] tables ,
<br>What do you think might be the reason of this error ?.
<p>2. I've got the next warning:
<br><font color="#FF0000">WARNING (line&nbsp; 427) - Pulldown Typical data
is non-monotonic</font>
<br><font color="#FF0000">WARNING (line&nbsp; 427) - Pulldown Maximum data
is non-monotonic</font>
<br><font color="#FF0000">WARNING (line&nbsp; 428) - Pulldown Minimum data
is non-monotonic</font>
<br>according to pulldn subtraction gnd_clamp cookbook and standard instructions
,
<br>it is impossible to get monotonic data.
<br>It is even mentioned in the standard that the [pulldn] or&nbsp; [pullup]
tables might be non-monotonic.
<br>Is it all right to ignore this warning ?
<p>With regards
<p>Yoked.
<br>"Ross, Bob" wrote:
<blockquote TYPE=CITE>Hello Yoked:
<p>We are temporarily having reflector e-mail problems,
<br>so you message did not get sent to the general list.
<p>However, I am responding on the ibis-users reflector
<br>and copying Stephen Peters, who authored the Cookbook.
<br>My responses are in your text noted by "*" marks.&nbsp; These
<br>are brief responses without looking at the Cookbook
<br>document.&nbsp; I am trying to convey what was intended,
<br>not any editorial issues regarding how it is documented.
<p>Bob Ross
<br>Mentor Graphics
<p>---------------------
<p>Subject: I/O buffer modeling cookbook
<br>From: Yoked Erlich (r58559) ([email-masked])
<br>Date: Sun Aug 12 2001 - 04:18:21 PDT
<p>Hi ,
<p>I would like to ask some questions about the 'I/O buffer modeling
<br>cookbook'
<br>paper (revision 2.0X) , Which I've got from 'www.eig.org' web site.
<p>1. Is there anywhere I can find revision 3.2 cookbook?
<p>* No, a Version 3.2 Cookbook has not been written.&nbsp; Cookbook 2
was
<br>intended to cover Version 3.2 features, but we never got that far.
<p>2. I've an I/O buffer model which working in some chip pads as I/O ,
<br>some pads as steady input and some pads as steady output.
<br>&nbsp;&nbsp;&nbsp; I would like to know if the buffer grouping is made
by the buffer
<br>type or by the pad direction?
<br>&nbsp;&nbsp;&nbsp; If buffer type is the answer so one model with I/O
type in enough
<br>for this buffer,
<br>&nbsp;&nbsp;&nbsp; If pad direction is the answer so three model is
needed for this
<br>buffer , I/O model , Input model and Output model
<br>&nbsp;&nbsp;&nbsp; ( in this case Input and Output model tests will
be exactly the same
<br>as I/O model ) .
<p>* If the buffer is truely an I/O, then it should be provided and
<br>documented as I/O.&nbsp; A user might have additional knowledge that
<br>certain I/O buffers are configured only as Input or Output buffers.
<br>It would be permissible to modify that instance of the model and
<br>just change the Model_type.&nbsp; That would help the EDA tool do
<br>only the simulations that are relevant for the design.
<p>3-6 questions are about 'Extracting Data for the [Ramp] keyword'
<br>paragraph in the cookbook :
<br>3. It is written that 'if the device does not have enough
<br>&nbsp;&nbsp;&nbsp;&nbsp; drive capability to make a significant output
transition than a
<br>higher load may be used' ,
<br>&nbsp;&nbsp;&nbsp;&nbsp; How much is significant output transition
?
<p>* I do not have any hard guideline.&nbsp; I prefer impedances in the
<br>order of magnitude of transmission line loads since that is a
<br>typical high-speed design application.&nbsp; That ususally captures
<br>a fast edge that would be seen with a PCB interconnect.
<p>* This makes no sense for certain weak buffers which would
<br>require multiple reflections to change from one state to the
<br>other for an open line.&nbsp; If the application is not high-speed,
<br>then it does not manner.&nbsp;&nbsp; I would guess that a higher value
<br>load might be OK for a driver source impedance > 300 ohms.
<br>Others might have different ideas.
<p>4. it is written that ' For an open drain , measure the rise and fall
<br>time into the load resistor and voltage used
<br>&nbsp;&nbsp;&nbsp; by the manufacture when specifying propagation delays'
, This
<br>sentence is not clear
<br>&nbsp;&nbsp;&nbsp; what is the test structure in open drain buffer
case?.
<p>* This is ambiguous.&nbsp; I prefer low impedance (50 ohm) pullups to
<br>capture a faster edge.&nbsp; This may be in the order of magnitude
of
<br>the load seen during the intial part of the transition when the
<br>device is connected through a PCB interconnect.
<p>5. it is written that ' Falling edge ramp data is captured with the
load
<br>resistor tied to VCC'
<br>&nbsp;&nbsp;&nbsp; , Is VCC mean the pmos Driver source voltage (pad
voltage) or low
<br>voltage?
<p>* This means that one end of the load resistor is connected to
<br>Vcc, and the other end is connected to the output pad.
<p>6. It is written that 'simulations are performed with C_comp included
in
<br>the circuit' , This sentence is not clear.
<br>&nbsp;&nbsp;&nbsp; As I understood C_comp is the capacitance seen when
looking from the
<br>pad back into the buffer ,
<br>&nbsp;&nbsp;&nbsp; It is written that C_comp should be added to the
simulation , but
<br>C_comp is not a capacitor it is capacitance measurement.
<p>* It is difficult to de-embed the die capacitance information from a
<br>Spice net list (since some of the contribution is due to paramaters
<br>within the transistor/diode models) or from a real physical measurements.
<p>* So the intent is to clarify that the die capacitance is already
<br>included in any waveform extraction.&nbsp; Since C_comp is a first
order
<br>approximation of the die capacitance, its effects should be included
<br>in an EDA tool simulation.&nbsp; I have not looked at the specific
<br>wording, but I assume this is confusing.
<p>7. In 'Ground Clamp' paragraph it is written that 'The data in table
<br>must cover the range of -Vcc to Vcc ' ,
<br>&nbsp;&nbsp;&nbsp; Isn't it suppose to be -Vcc to 2*Vcc ?
<p>* This response also covers 9.
<p>* No, the minimum range is intended to be -vcc to vcc.&nbsp; The Power
<br>Clamp covers from vcc to 2vcc.&nbsp; When this minimum range was
<br>established, most Inputs were at negligle current at Vcc and the
<br>slope (current vs voltage) was also nearly 0.&nbsp; So concatenation
<br>of the tables produced the same effect as extrapolation.
<p>* It is allowed to extend the clamp ranges beyond the specified
<br>range.&nbsp; In some cases you should do so, especially if you are
<br>including the effect of an internal terminator.&nbsp; In such cases,
<br>the conditions above are not met, and I prefer -vcc to 2vcc for
<br>both clamp tables.&nbsp; Care must be taken so that
<br>currents are not double counted.&nbsp; However, for many situations,
<br>the "minimal" IBIS guidelines are sufficient.
<p>8. In 'pulldn' paragraph it is written 'If the buffer is a 3-state
<br>device then first subtract the ground clamp current
<br>&nbsp;&nbsp;&nbsp; from the pulldown current then enter the result
into the [pulldown]
<br>table' ,
<br>&nbsp;&nbsp;&nbsp; first , it is written above the graph 'Pullup I/V
curve after
<br>subtraction of ground clamp currents' Which is probably mistake.
<br>&nbsp;&nbsp;&nbsp; second , Should I replace the pulldn results in
Ibis model file
<br>after the subtraction?
<p>* What is entered in the [Pulldown] table is the result after
<br>subtraction.
<p>9. In 'Power Clamp' It is written that 'the data in the table must cover
<br>the range of vcc to vcc*2' ,
<br>&nbsp;&nbsp;&nbsp; Isn't the range suppose to be -Vcc to 2*Vcc ?
<p>* See 7 above.
<p>--
<br>With regards,
<br>Yoked.
<br>_____________________________________
<br>E-mail:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; [email-masked]
<br>Tel: 972-9-9522482 Fax: 972-9-9522888
<br>WIRELESS&nbsp;&nbsp;&nbsp;&nbsp; CIRCUIT&nbsp; - IO&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
GROUP
<br>MOTOROLA&nbsp;&nbsp;&nbsp;&nbsp; SEMICONDUCTOR&nbsp;&nbsp;&nbsp;&nbsp;
ISRAEL</blockquote>

<pre>--&nbsp;

With regards,

Yoked.

_____________________________________
E-mail:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; [email-masked]
Tel: 972-9-9522482 Fax: 972-9-9522888
WIRELESS&nbsp;&nbsp;&nbsp;&nbsp; CIRCUIT&nbsp; - IO&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; GROUP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
MOTOROLA&nbsp;&nbsp;&nbsp;&nbsp; SEMICONDUCTOR&nbsp;&nbsp;&nbsp;&nbsp; ISRAEL</pre>
&nbsp;</html>

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- --------------ED3B6BFAD69F0FFCEA61E194--

------------------------------

Date: Tue, 21 Aug 2001 11:39:09 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: RE: IBIS - I/O Buffer Modeling Cookbook

This message is in MIME format. Since your mail reader does not understand
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Hi Yoked:
 
  Regarding the non-monotonic warnings, I would still check the line number
on the pulldown curves and verify what is causing the non-monotonic warning.
It should be the area where ground clamp current was subtracted from the
total pulldown current and not somewhere else.
  By the way, when creating a model for a non-tristatable output (i.e. one
in which either the pullup or pulldown curves are always on) one does not
have to subtract ground and power clamp current from the curves.  In this
case the warning should not occur.
 
  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: yoked erlich [mailto:[email-masked]]
Sent: Tuesday, August 21, 2001 7:40 AM
To: Ross, Bob; [email-masked]; [email-masked]; [email-masked];
Sergey Sofer (r53493)
Cc: Lior Aviv
Subject: Re: IBIS - I/O Buffer Modeling Cookbook

Hi , 

There are another few questions about ibischk3 results: 

1. I've got the next warning: 
 WARNING - [Model] iovb has no description of the buffer's high state 
                    DC drive characteristics (no [Pullup] table).  This
warning 
                    can be silenced by changing the Model_type or by adding
a 
                    [Pullup] table. 
This cell ('iovb') is 'Open_drain' type which according to Ibis maker cook
book do not 
suppose to have [Pullup] table , only the [pulldown],[gnd_clamp] and
[power_clamp] tables , 
What do you think might be the reason of this error ?. 

2. I've got the next warning: 
WARNING (line  427) - Pulldown Typical data is non-monotonic 
WARNING (line  427) - Pulldown Maximum data is non-monotonic 
WARNING (line  428) - Pulldown Minimum data is non-monotonic 
according to pulldn subtraction gnd_clamp cookbook and standard instructions
, 
it is impossible to get monotonic data. 
It is even mentioned in the standard that the [pulldn] or  [pullup] tables
might be non-monotonic. 
Is it all right to ignore this warning ? 

With regards 

Yoked. 
"Ross, Bob" wrote: 

Hello Yoked: 

We are temporarily having reflector e-mail problems, 
so you message did not get sent to the general list. 

However, I am responding on the ibis-users reflector 
and copying Stephen Peters, who authored the Cookbook. 
My responses are in your text noted by "*" marks.  These 
are brief responses without looking at the Cookbook 
document.  I am trying to convey what was intended, 
not any editorial issues regarding how it is documented. 

Bob Ross 
Mentor Graphics 

- --------------------- 

Subject: I/O buffer modeling cookbook 
From: Yoked Erlich (r58559) ([email-masked]) 
Date: Sun Aug 12 2001 - 04:18:21 PDT 

Hi , 

I would like to ask some questions about the 'I/O buffer modeling 
cookbook' 
paper (revision 2.0X) , Which I've got from 'www.eig.org' web site. 

1. Is there anywhere I can find revision 3.2 cookbook? 

* No, a Version 3.2 Cookbook has not been written.  Cookbook 2 was 
intended to cover Version 3.2 features, but we never got that far. 

2. I've an I/O buffer model which working in some chip pads as I/O , 
some pads as steady input and some pads as steady output. 
    I would like to know if the buffer grouping is made by the buffer 
type or by the pad direction? 
    If buffer type is the answer so one model with I/O type in enough 
for this buffer, 
    If pad direction is the answer so three model is needed for this 
buffer , I/O model , Input model and Output model 
    ( in this case Input and Output model tests will be exactly the same 
as I/O model ) . 

* If the buffer is truely an I/O, then it should be provided and 
documented as I/O.  A user might have additional knowledge that 
certain I/O buffers are configured only as Input or Output buffers. 
It would be permissible to modify that instance of the model and 
just change the Model_type.  That would help the EDA tool do 
only the simulations that are relevant for the design. 

3-6 questions are about 'Extracting Data for the [Ramp] keyword' 
paragraph in the cookbook : 
3. It is written that 'if the device does not have enough 
     drive capability to make a significant output transition than a 
higher load may be used' , 
     How much is significant output transition ? 

* I do not have any hard guideline.  I prefer impedances in the 
order of magnitude of transmission line loads since that is a 
typical high-speed design application.  That ususally captures 
a fast edge that would be seen with a PCB interconnect. 

* This makes no sense for certain weak buffers which would 
require multiple reflections to change from one state to the 
other for an open line.  If the application is not high-speed, 
then it does not manner.   I would guess that a higher value 
load might be OK for a driver source impedance > 300 ohms. 
Others might have different ideas. 

4. it is written that ' For an open drain , measure the rise and fall 
time into the load resistor and voltage used 
    by the manufacture when specifying propagation delays' , This 
sentence is not clear 
    what is the test structure in open drain buffer case?. 

* This is ambiguous.  I prefer low impedance (50 ohm) pullups to 
capture a faster edge.  This may be in the order of magnitude of 
the load seen during the intial part of the transition when the 
device is connected through a PCB interconnect. 

5. it is written that ' Falling edge ramp data is captured with the load 
resistor tied to VCC' 
    , Is VCC mean the pmos Driver source voltage (pad voltage) or low 
voltage? 

* This means that one end of the load resistor is connected to 
Vcc, and the other end is connected to the output pad. 

6. It is written that 'simulations are performed with C_comp included in 
the circuit' , This sentence is not clear. 
    As I understood C_comp is the capacitance seen when looking from the 
pad back into the buffer , 
    It is written that C_comp should be added to the simulation , but 
C_comp is not a capacitor it is capacitance measurement. 

* It is difficult to de-embed the die capacitance information from a 
Spice net list (since some of the contribution is due to paramaters 
within the transistor/diode models) or from a real physical measurements. 

* So the intent is to clarify that the die capacitance is already 
included in any waveform extraction.  Since C_comp is a first order 
approximation of the die capacitance, its effects should be included 
in an EDA tool simulation.  I have not looked at the specific 
wording, but I assume this is confusing. 

7. In 'Ground Clamp' paragraph it is written that 'The data in table 
must cover the range of -Vcc to Vcc ' , 
    Isn't it suppose to be -Vcc to 2*Vcc ? 

* This response also covers 9. 

* No, the minimum range is intended to be -vcc to vcc.  The Power 
Clamp covers from vcc to 2vcc.  When this minimum range was 
established, most Inputs were at negligle current at Vcc and the 
slope (current vs voltage) was also nearly 0.  So concatenation 
of the tables produced the same effect as extrapolation. 

* It is allowed to extend the clamp ranges beyond the specified 
range.  In some cases you should do so, especially if you are 
including the effect of an internal terminator.  In such cases, 
the conditions above are not met, and I prefer -vcc to 2vcc for 
both clamp tables.  Care must be taken so that 
currents are not double counted.  However, for many situations, 
the "minimal" IBIS guidelines are sufficient. 

8. In 'pulldn' paragraph it is written 'If the buffer is a 3-state 
device then first subtract the ground clamp current 
    from the pulldown current then enter the result into the [pulldown] 
table' , 
    first , it is written above the graph 'Pullup I/V curve after 
subtraction of ground clamp currents' Which is probably mistake. 
    second , Should I replace the pulldn results in Ibis model file 
after the subtraction? 

* What is entered in the [Pulldown] table is the result after 
subtraction. 

9. In 'Power Clamp' It is written that 'the data in the table must cover 
the range of vcc to vcc*2' , 
    Isn't the range suppose to be -Vcc to 2*Vcc ? 

* See 7 above. 

- -- 
With regards, 
Yoked. 
_____________________________________ 
E-mail:       [email-masked] 
Tel: 972-9-9522482 Fax: 972-9-9522888 
WIRELESS     CIRCUIT  - IO      GROUP 
MOTOROLA     SEMICONDUCTOR     ISRAEL

- -- 

With regards,

Yoked.

_____________________________________

E-mail:           [email-masked]

Tel: 972-9-9522482 Fax: 972-9-9522888

WIRELESS     CIRCUIT  - IO      GROUP                 

MOTOROLA     SEMICONDUCTOR     ISRAEL

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<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=816272518-21082001>Hi 
Yoked:</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=816272518-21082001></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=816272518-21082001>&nbsp;&nbsp;Regarding the non-monotonic warnings, I 
would still check the line number on the pulldown curves and verify what is 
causing the non-monotonic warning.&nbsp; It should be the area where&nbsp;ground 
clamp current was subtracted from the total pulldown current and not somewhere 
else.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=816272518-21082001>&nbsp; 
By the way, when creating a model for a non-tristatable output&nbsp;(i.e. one in 
which either the pullup or pulldown curves are always on) one does not have to 
subtract ground and power clamp current from the curves.&nbsp; In this case the 
warning should not occur.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=816272518-21082001></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=816272518-21082001>&nbsp; 
Regards,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=816272518-21082001>&nbsp; 
Stephen Peters</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=816272518-21082001>&nbsp; 
Intel Corp.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=816272518-21082001></SPAN></FONT>&nbsp;</DIV>
<BLOCKQUOTE>
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma 
  size=2>-----Original Message-----<BR><B>From:</B> yoked erlich 
  [mailto:[email-masked]]<BR><B>Sent:</B> Tuesday, August 21, 2001 7:40 
  AM<BR><B>To:</B> Ross, Bob; [email-masked]; [email-masked]; 
  [email-masked]; Sergey Sofer (r53493)<BR><B>Cc:</B> Lior Aviv<BR><B>Subject:</B> 
  Re: IBIS - I/O Buffer Modeling Cookbook<BR><BR></DIV></FONT>Hi , 
  <P>There are another few questions about ibischk3 results: 
  <P>1. I've got the next warning: <BR><FONT color=#ff0000>&nbsp;WARNING - 
  [Model] iovb has no description of the buffer's high state</FONT> <BR><FONT 
  color=#ff0000>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
  DC drive characteristics (no [Pullup] table).&nbsp; This warning</FONT> 
  <BR><FONT 
  color=#ff0000>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
  can be silenced by changing the Model_type or by adding a</FONT> <BR><FONT 
  color=#ff0000>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
  [Pullup] table.</FONT> <BR>This cell ('iovb') is 'Open_drain' type which 
  according to Ibis maker cook book do not <BR>suppose to have [Pullup] table , 
  only the [pulldown],[gnd_clamp] and [power_clamp] tables , <BR>What do you 
  think might be the reason of this error ?. 
  <P>2. I've got the next warning: <BR><FONT color=#ff0000>WARNING (line&nbsp; 
  427) - Pulldown Typical data is non-monotonic</FONT> <BR><FONT 
  color=#ff0000>WARNING (line&nbsp; 427) - Pulldown Maximum data is 
  non-monotonic</FONT> <BR><FONT color=#ff0000>WARNING (line&nbsp; 428) - 
  Pulldown Minimum data is non-monotonic</FONT> <BR>according to pulldn 
  subtraction gnd_clamp cookbook and standard instructions , <BR>it is 
  impossible to get monotonic data. <BR>It is even mentioned in the standard 
  that the [pulldn] or&nbsp; [pullup] tables might be non-monotonic. <BR>Is it 
  all right to ignore this warning ? 
  <P>With regards 
  <P>Yoked. <BR>"Ross, Bob" wrote: 
  <BLOCKQUOTE TYPE="CITE">Hello Yoked: 
    <P>We are temporarily having reflector e-mail problems, <BR>so you message 
    did not get sent to the general list. 
    <P>However, I am responding on the ibis-users reflector <BR>and copying 
    Stephen Peters, who authored the Cookbook. <BR>My responses are in your text 
    noted by "*" marks.&nbsp; These <BR>are brief responses without looking at 
    the Cookbook <BR>document.&nbsp; I am trying to convey what was intended, 
    <BR>not any editorial issues regarding how it is documented. 
    <P>Bob Ross <BR>Mentor Graphics 
    <P>--------------------- 
    <P>Subject: I/O buffer modeling cookbook <BR>From: Yoked Erlich (r58559) 
    ([email-masked]) <BR>Date: Sun Aug 12 2001 - 04:18:21 PDT 
    <P>Hi , 
    <P>I would like to ask some questions about the 'I/O buffer modeling 
    <BR>cookbook' <BR>paper (revision 2.0X) , Which I've got from 'www.eig.org' 
    web site. 
    <P>1. Is there anywhere I can find revision 3.2 cookbook? 
    <P>* No, a Version 3.2 Cookbook has not been written.&nbsp; Cookbook 2 was 
    <BR>intended to cover Version 3.2 features, but we never got that far. 
    <P>2. I've an I/O buffer model which working in some chip pads as I/O , 
    <BR>some pads as steady input and some pads as steady output. 
    <BR>&nbsp;&nbsp;&nbsp; I would like to know if the buffer grouping is made 
    by the buffer <BR>type or by the pad direction? <BR>&nbsp;&nbsp;&nbsp; If 
    buffer type is the answer so one model with I/O type in enough <BR>for this 
    buffer, <BR>&nbsp;&nbsp;&nbsp; If pad direction is the answer so three model 
    is needed for this <BR>buffer , I/O model , Input model and Output model 
    <BR>&nbsp;&nbsp;&nbsp; ( in this case Input and Output model tests will be 
    exactly the same <BR>as I/O model ) . 
    <P>* If the buffer is truely an I/O, then it should be provided and 
    <BR>documented as I/O.&nbsp; A user might have additional knowledge that 
    <BR>certain I/O buffers are configured only as Input or Output buffers. 
    <BR>It would be permissible to modify that instance of the model and 
    <BR>just change the Model_type.&nbsp; That would help the EDA tool do 
    <BR>only the simulations that are relevant for the design. 
    <P>3-6 questions are about 'Extracting Data for the [Ramp] keyword' 
    <BR>paragraph in the cookbook : <BR>3. It is written that 'if the device 
    does not have enough <BR>&nbsp;&nbsp;&nbsp;&nbsp; drive capability to make a 
    significant output transition than a <BR>higher load may be used' , 
    <BR>&nbsp;&nbsp;&nbsp;&nbsp; How much is significant output transition ? 
    <P>* I do not have any hard guideline.&nbsp; I prefer impedances in the 
    <BR>order of magnitude of transmission line loads since that is a 
    <BR>typical high-speed design application.&nbsp; That ususally captures 
    <BR>a fast edge that would be seen with a PCB interconnect. 
    <P>* This makes no sense for certain weak buffers which would <BR>require 
    multiple reflections to change from one state to the <BR>other for an open 
    line.&nbsp; If the application is not high-speed, <BR>then it does not 
    manner.&nbsp;&nbsp; I would guess that a higher value <BR>load might be OK 
    for a driver source impedance &gt; 300 ohms. <BR>Others might have different 
    ideas. 
    <P>4. it is written that ' For an open drain , measure the rise and fall 
    <BR>time into the load resistor and voltage used <BR>&nbsp;&nbsp;&nbsp; by 
    the manufacture when specifying propagation delays' , This <BR>sentence is 
    not clear <BR>&nbsp;&nbsp;&nbsp; what is the test structure in open drain 
    buffer case?. 
    <P>* This is ambiguous.&nbsp; I prefer low impedance (50 ohm) pullups to 
    <BR>capture a faster edge.&nbsp; This may be in the order of magnitude of 
    <BR>the load seen during the intial part of the transition when the 
    <BR>device is connected through a PCB interconnect. 
    <P>5. it is written that ' Falling edge ramp data is captured with the load 
    <BR>resistor tied to VCC' <BR>&nbsp;&nbsp;&nbsp; , Is VCC mean the pmos 
    Driver source voltage (pad voltage) or low <BR>voltage? 
    <P>* This means that one end of the load resistor is connected to <BR>Vcc, 
    and the other end is connected to the output pad. 
    <P>6. It is written that 'simulations are performed with C_comp included in 
    <BR>the circuit' , This sentence is not clear. <BR>&nbsp;&nbsp;&nbsp; As I 
    understood C_comp is the capacitance seen when looking from the <BR>pad back 
    into the buffer , <BR>&nbsp;&nbsp;&nbsp; It is written that C_comp should be 
    added to the simulation , but <BR>C_comp is not a capacitor it is 
    capacitance measurement. 
    <P>* It is difficult to de-embed the die capacitance information from a 
    <BR>Spice net list (since some of the contribution is due to paramaters 
    <BR>within the transistor/diode models) or from a real physical 
    measurements. 
    <P>* So the intent is to clarify that the die capacitance is already 
    <BR>included in any waveform extraction.&nbsp; Since C_comp is a first order 
    <BR>approximation of the die capacitance, its effects should be included 
    <BR>in an EDA tool simulation.&nbsp; I have not looked at the specific 
    <BR>wording, but I assume this is confusing. 
    <P>7. In 'Ground Clamp' paragraph it is written that 'The data in table 
    <BR>must cover the range of -Vcc to Vcc ' , <BR>&nbsp;&nbsp;&nbsp; Isn't it 
    suppose to be -Vcc to 2*Vcc ? 
    <P>* This response also covers 9. 
    <P>* No, the minimum range is intended to be -vcc to vcc.&nbsp; The Power 
    <BR>Clamp covers from vcc to 2vcc.&nbsp; When this minimum range was 
    <BR>established, most Inputs were at negligle current at Vcc and the 
    <BR>slope (current vs voltage) was also nearly 0.&nbsp; So concatenation 
    <BR>of the tables produced the same effect as extrapolation. 
    <P>* It is allowed to extend the clamp ranges beyond the specified 
    <BR>range.&nbsp; In some cases you should do so, especially if you are 
    <BR>including the effect of an internal terminator.&nbsp; In such cases, 
    <BR>the conditions above are not met, and I prefer -vcc to 2vcc for <BR>both 
    clamp tables.&nbsp; Care must be taken so that <BR>currents are not double 
    counted.&nbsp; However, for many situations, <BR>the "minimal" IBIS 
    guidelines are sufficient. 
    <P>8. In 'pulldn' paragraph it is written 'If the buffer is a 3-state 
    <BR>device then first subtract the ground clamp current 
    <BR>&nbsp;&nbsp;&nbsp; from the pulldown current then enter the result into 
    the [pulldown] <BR>table' , <BR>&nbsp;&nbsp;&nbsp; first , it is written 
    above the graph 'Pullup I/V curve after <BR>subtraction of ground clamp 
    currents' Which is probably mistake. <BR>&nbsp;&nbsp;&nbsp; second , Should 
    I replace the pulldn results in Ibis model file <BR>after the subtraction? 
    <P>* What is entered in the [Pulldown] table is the result after 
    <BR>subtraction. 
    <P>9. In 'Power Clamp' It is written that 'the data in the table must cover 
    <BR>the range of vcc to vcc*2' , <BR>&nbsp;&nbsp;&nbsp; Isn't the range 
    suppose to be -Vcc to 2*Vcc ? 
    <P>* See 7 above. 
    <P>-- <BR>With regards, <BR>Yoked. <BR>_____________________________________ 
    <BR>E-mail:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; [email-masked] 
    <BR>Tel: 972-9-9522482 Fax: 972-9-9522888 
    <BR>WIRELESS&nbsp;&nbsp;&nbsp;&nbsp; CIRCUIT&nbsp; - 
    IO&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; GROUP <BR>MOTOROLA&nbsp;&nbsp;&nbsp;&nbsp; 
    SEMICONDUCTOR&nbsp;&nbsp;&nbsp;&nbsp; ISRAEL</P></BLOCKQUOTE><PRE>--&nbsp;

With regards,

Yoked.

_____________________________________
E-mail:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; [email-masked]
Tel: 972-9-9522482 Fax: 972-9-9522888
WIRELESS&nbsp;&nbsp;&nbsp;&nbsp; CIRCUIT&nbsp; - IO&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; GROUP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
MOTOROLA&nbsp;&nbsp;&nbsp;&nbsp; SEMICONDUCTOR&nbsp;&nbsp;&nbsp;&nbsp; ISRAEL</PRE>&nbsp; 
</BLOCKQUOTE></BODY></HTML>

- ------_=_NextPart_001_01C12A70.90BFD7C0--

------------------------------

Date: Tue, 21 Aug 2001 13:00:26 -0700
From: "Ross, Bob" <[email-masked]>
Subject: IBIS - Reissue of BIRD72 - Accommodating PMOS and NMOS//PMOS Seri es FET  Models

To All:

BIRD72 authored by Tom Dagostino is reissued for discussion since
it was not properly distributed earlier.  Copies of BIRDs can
also be found under

  http://www.eda.org/pub/ibis/birds/

Bob Ross
Mentor Graphics

******************************************************************************
******************************************************************************

BIRD ID#:        72
ISSUE TITLE:     Accommodating PMOS and NMOS//PMOS Series FET Models
REQUESTER:       Tom Dagostino, Mentor Graphics
DATE SUBMITTED:  July 26, 2001
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

******************************************************************************
******************************************************************************

STATEMENT OF THE ISSUE:

The IBIS FET Bus Switch model assumes a series NMOS FET which has its gate
tied to Vdd.  We have come across two other topologies for the FET switches,
specifically: 

1. What appears to be a PMOS device with it's gate tied to ground 
2. Parallel NMOS and PMOS devices with gates respectively tied to Vdd and
   ground.

The IBIS Golden Parser produces warnings and errors with models that describe
this behavior.

******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

These models cause issues with the IBIS Golden Parser and, depending on
assumptions in the simulator's implementations that support the bus switch,
analysis issues.  

For the single PMOS case:

The parser is set up to see increasing current as Vgs increase where Vgs is
defined as Vcc - Vsource.  Given this definition for Vgs the current Id will
decrease as 'Vgs' increases for the PMOS device with its gate to ground.  The
parser gives an error of decreasing current as 'Vgs' increases.

Simulators may make the assumption the FET is a NMOS device and may not handle
the characteristics properly if the model gets parsed in.

For the dual PMOS/NMOS case:

In the case of the dual PMOS/NMOS topology the currents through the parallel
FET's will sum and produce an Id curve that: 

- -- starts with significant current at 'Vgs' = 0 (current is flowing through
the PMOS device)

- -- decreases by 10 to 90% at about 40% of 'Vgs' range where both the PMOS and
NMOS devices are both on  

- -- increases to a larger value at 'Vgs' = Vdd than at 'Vgs" = 0.  This is
where the NMOS device is fully on

This characteristic has been observed in several devices.  This will cause a
non-monotonic warning from the parser.

It is not known how all simulators will handle this non-monotonic behavior.
 
In general the simulators should be able to handle these characteristics.
The IV curves define the device's characteristics and the simulator should
just work with that definition.

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

The following changes are proposed:

The definition of Voltage in the IV table changes.  Vgs has been Vcc - Vsource
assuming the gate was tied to Vcc.  IBIS should now assume the voltage in the
IV table is really Vcc minus the FET's source voltage (Voltage = Vcc -
Vsource).  This makes old models compatible and no change in the model format
is required.

Decreasing current vs. Voltage are allowed.

Non-monotonic currents in the table are expected in the parallel case but
warnings can still be issued.  It may be useful to have the modeler note the
type of switch in the model so the user can better understand any
non-monotonic issues.  

******************************************************************************

Changes and additions to the IBIS Specification are shown by the |* lines

|=============================================================================
|     Keyword:  [Series MOSFET]
|    Required:  Yes, for series MOSFET switches
| Description:  The data points under this keyword define the I-V tables for
|               voltages measured at Pin 2 for a given Vds setting.  Currents 
|               are considered positive if they flow into Pin 1.  Pins 1 and 
|               2 are listed under the [Series Pin Mapping] keyword under
|               [Series Pin Mapping] and pin_2 columns, respectively.
|  Sub-Params:  Vds
| Usage Rules:  The first column contains the voltage value, and the three
|               remaining columns hold the typical, minimum, and maximum
|               current values.  The four entries, Voltage, I(typ), I(min),
|               and I(max) must be placed on a single line and must be
|               separated by at least one white space.
|
|               All four columns are required under these keywords.  However,
|               data is only required in the typical column.  If minimum 
|               and/or maximum current values are not available, the reserved
|               word "NA" must be used.  "NA" can be used for currents in the
|               typical column, but numeric values MUST be specified for the
|               first and last voltage points on any I-V table.  Each I-V 
|               table must have at least 2, but not more than 100, voltage
|               points.
|
| Other Notes:  There is no monotonicity requirement. However the model
|               supplier should realize that it may not be possible to derive
|               a behavioral model from non-monotonic data.
|
|* the old model is:
|*               The model is:
|*
|*                                Table Current
|*                                   ------->
|*                               +     Vds     -
|*                             Pin 1           Pin 2
|*                               <---|     |--->  +
|*                               d   |_____| - s
|*                                    --+-- Vgs   Vs
|*                                      | g  +
|*                                                -
|*                      Vg = [Voltage Range] = Vcc
|*                      Vgs = Table Voltage = Vtable = Vcc - Vs
|*                      Ids = Table Current for a given Vcc and Vds
|
|*The new model is:
|*
|*                                Table Current
|*                                   ------->  Ids
|*                               +     Vds     -
|*
|*                                     Vcc
|*                                      | g
|*                                  ----+----
|*                                   -------  NMOS
|*                             Pin 1 |     |    Pin 2
|*                               <---|     |--->  Voltage = Vcc - Vs
|*                       PMOS    d   |_____|  s
|*                                    --+-- 
|*                                      | g  
|*                                     GND 
|*
|* Either of the FET's could be removed (or have zero current
|* contribution.  Thus this model covers all four conditions, off,
|* single NMOS, single PMOS and parallel NMOS/PMOS.
|*         
|*                      Voltage = Table Voltage = Vtable = Vcc - Vs
|*                       Ids = Table Current for a given Vcc and Vds
|
|
|* old       Internal logic that is generally referenced to the power rail
|*             is used to set the MOSFET switch to its 'On' state.  Thus the
|*             [Voltage Range] settings provide the assumed gate voltages.
|*             If the [POWER Clamp Reference] exists, it overrides the
|*             [Voltage Range] value.  The table entries are actually the Vgs
|*             values referenced to the power rail.  The polarity conventions
|*
|* new      Internal Logic that is generally referenced to the power rail
|*              is used to set the NMOS MOSFET switch to its 'ON' state.
|*             Internal logic likewise referenced to ground is used to set the 
|*-             PMOS device to its 'ON' state if the PMOS device is present.
|*             Thus the [Voltage Range] settings provide the assumed 
|*             gate voltages.  If the [POWER Clamp Reference] exists, it 
|*             overrides the [Voltage Range] value.  The table entries are
|*             actually Vgs of the NMOS device and Vcc - Vgs of the PMOS
!*             device if present.  The polarity conventions

|               are identical with those used for other tables that are
|               referenced to power rails.  Thus the voltage column can be
|               viewed as a table defining the source voltages Vs according to
|               the convention:  Vtable = Vcc - Vs.
|
|               If the switch is used in an application such as interfacing
|               between 3.3 V and 5.0 V logic, the Vcc may be biased at a 
|               voltage (such as 4.3 V) that is different from a power rail
|               voltage (such as 5.0 V) used to create the model.  Just
|               readjust the [Voltage Range] entries (or [POWER Clamp
|               Reference] entries).
|
|               One fundamental assumption in the MOSFET switch model is that
|               it operates in a symmetrical manner.  The tables and
|               expressions are given assuming that Vd >= Vs.  If Vd < Vs,
|               then apply the same relationships under the assumption that
|               the source and drain nodes are interchanged.  A consequence of
|               this assumption is that the Vds subparameter is constrained to
|               values Vds > 0.  It is assumed that with Vds = 0 the currents
|               will be 0 mA.  A further consequence of this assumption that
|               would be embedded in the analysis process is that the voltage
|               table is based on the side of the model with the lowest
|               voltage (and that side is defined as the source).  Thus the
|               analysis must allow current to flow in both directions, as
|               would occur due to reflections when the switch is connected in
|               series with an unterminated transmission line.
|
|               The model data is used to create an On state relationship
|               between the actual drain to source current, ids, and the
|               actual drain to source voltage, vds:
|
|                                    ids = f(vds).
|
|               This functional relationship depends on the actual source
|               voltage Vs and can be expressed in terms of the corresponding
|               table currents associated with Vs (and expressed as a function
|               of Vgs).
|
|               If only one [Series MOSFET] table is supplied (as a first
|               order approximation), the functional relationship is assumed
|               to be linearly related to the table drain to source current,
|               Ids, for the given Vds subparameter value and located at the
|               existing gate to source voltage value Vgs.  This table current
|               is denoted as Ids(Vgs, Vds).  The functional relationship
|               becomes:
|
|* old                            ids = Ids(Vgs, Vds) * vds / Vds.  
|*
|* new     ids = Idsn(V, Vds) * vds/Vds + Idsp((Vcc - V), Vds) * vds/Vds
|
|               More than one [Series MOSFET] table is permitted, but it is
|               simulator dependent how the data will be used.  Each
|               successive [Series MOSFET] table must have a different
|               subparameter value for Vds.  The number of tables must not 
|               exceed 100.
|
|               C_comp values are ignored for [Series MOSFET] models.
|-----------------------------------------------------------------------------
[On]
[Series MOSFET]
Vds = 1.0  
|  Voltage   I(typ)    I(min)    I(max)
    5.0V    257.9m     153.3m    399.5m     | Defines the Ids current as a
    4.0V    203.0m     119.4m    317.3m     | function of Vgs, for Vds = 1.0
    3.0V    129.8m      74.7m    205.6m 
    2.0V     31.2m      16.6m     51.0m
    1.0V     52.7p      46.7p     56.7p
    0.0V      0.0p       0.0p      0.0p
|=============================================================================

******************************************************************************

ANY OTHER BACKGROUND INFORMATION:

An Ad Hoc presentation on this topic was initially presented at the IBIS
Summit Meeting on June 21, 2001.

******************************************************************************

------------------------------

Date: Tue, 21 Aug 2001 14:03:04 -0600
From: "Ross, Bob" <[email-masked]>
Subject: IBIS - BIRD73 - Fall Back Submodel

To All:

BIRD73 is also reissued since it has not been properly
distributed.

Bob Ross
Mentor Graphics

****************************************************************************
**
****************************************************************************
**

BIRD ID#:        73
ISSUE TITLE:     Fall Back Submodel
REQUESTER:       Bob Ross, Mentor Graphics
DATE SUBMITTED:  8-2-2001
DATE ACCEPTED BY IBIS OPEN FORUM:  Pending

****************************************************************************
**
****************************************************************************
**

STATEMENT OF THE ISSUE:

Existing submodels have a trigger for turning on functions.  This works for
Bus_hold (and corresponding active terminators) and Dynamic_clamp functions.

However another mechanism to turn off the submodels is needed for AVC type
devices which have the overall driver strength reduced after the output
passes through a voltage threshold value.

****************************************************************************
**

STATEMENT OF THE RESOLVED SPECIFICATIONS:

This BIRD proposes a new Submodel_type: Fall_back.  The new submodel
operates
similar to the Bus_hold submodel, but with opposite action.  The trigger
turns off a submodel (presumed on) when the output die voltage passes
through a trigger threshold.

Additions are noted in the relevant sections below by |* lines:

Comments for a new section or for unchanged sections are shown using
**** lines.

|===========================================================================
==
|===========================================================================
==
|
|                                 Section 6a
|
|              A D D    S U B M O D E L    D E S C R I P T I O N
|
|===========================================================================
==
|===========================================================================
==
|
| The [Add Submodel] keyword can be used under a top-level [Model] keyword
to
| to add special-purpose functionality to the existing top-level model.
This
| section describes the structure of the top-level model and the submodel.
|
| TOP-LEVEL MODEL:
|
| When special-purpose functional detail is needed, the top-level model can
| call one or more submodels.  The [Add Submodel] keyword is positioned 
| after the initial set of required and optional subparameters of the
[Model] 
| keyword and among the keywords under [Model].
| 
| The [Add Submodel] keyword lists of name of each submodel and the
permitted
| mode (Driving, Non-Driving or All) under which each added submodel is
used.
|
| SUBMODEL:
|
| A submodel is defined using the [Submodel] keyword.  It contains a subset
| of keywords and subparameters used for the [Model] keyword along with
other
| keywords and subparameters that are needed for the added functionality.
|
| The [Submodel] and [Submodel Spec] keywords are defined first since they
| are used for all submodels 
|
| The only required subparameter in [Submodel] is Submodel_type to define
the
| list of submodel types.  No subparameters under [Model] are permitted
under
| the [Submodel] keyword.
|
| The following set of keywords that are defined under the [Model] keyword
are
| supported by the [Submodel] keyword:
|
| [Pulldown]
| [Pullup]
| [GND Clamp]
| [POWER Clamp]
| [Ramp]
| [Rising Waveform]
| [Falling Waveform]
|
| The [Voltage Range], [Pullup Reference], [Pulldown Reference], [GND Clamp
| Reference], and [POWER Clamp Reference] keywords are not permitted.  The
| voltage settings are inherited from the top-level model.
|
| These additional keywords are used only for the [Submodel] are documented
| in this section:
|
| [Submodel Spec]
| [GND Pulse Table]
| [POWER Pulse Table]
|
| The application of these keywords depends upon the Submodel_type entries
| listed below:
|
| Dynamic_clamp
| Bus_hold
|* Fall_back
|
| Permitted keywords that are not defined for any of these submodel types
are
| ignored.  The rules for what set of keywords are required are found under
| the Dynamic Clamp and Bus Hold headings of this section.
|
|===========================================================================
==
|     Keyword:  [Submodel]
|    Required:  No
| Description:  Used to define a submodel, and its attributes.
|  Sub-Params:  Submodel_type        
| Usage Rules:  Each submodel must begin with the keyword [Submodel].  The
|               submodel name must match the one that is listed under an
|               [Add Submodel] keyword and must not contain more than 20
|               characters.  A .ibs file must contain enough [Submodel]
|               keywords to cover all of the model names specified under the
|               [Add Submodel] keyword.
|
|               Submodel_type subparameter is required and must be one of
the
|               following:
|
|*               Dynamic_clamp, Bus_hold, Fall_back
|
|               The C_comp subparameter is not permitted under the
[Submodel]
|               keyword.  The total effective die capacitance including the
|               submodel contributions are provided in the top-level model.
|
| Other Notes:  The following list of keywords that are defined under the 
|               [Model] keyword can be used under [Submodel]:  [Pulldown], 
|               [Pullup], [GND Clamp], [POWER Clamp], [Ramp], [Rising
|               Waveform], and [Falling Waveform].
|
|               The following list of additional keywords can be used:
|               [Submodel Spec], [GND Pulse Table], and [POWER Pulse Table].
|---------------------------------------------------------------------------
- --
[Submodel]      Dynamic_clamp1
Submodel_type   Dynamic_clamp
|

**** The next two sections are unchanged, but are shown for reference:

|===========================================================================
== 
|     Keyword:  [Submodel Spec]
|    Required:  No
| Description:  The [Submodel Spec] keyword defines four columns under which

|               specification and information subparameters are defined for 
|               submodels.
|  Sub-Params:  V_trigger_r, V_trigger_f, Off_delay
| Usage Rules:  The [Submodel Spec] is to be used only with submodels.
|
|               The following subparameters are used:
|                 V_trigger_r           Rising edge trigger voltage 
|                 V_trigger_f           Falling edge trigger voltage 
|                 Off_delay             Turn-off delay from V_trigger_r or
|                                       V_trigger_f
|
|               For each subparameter contained in the first column, the
|               remaining three hold its typical, minimum and maximum
values. 
|               The entries of typical, minimum and maximum be must be
placed 
|               on a single line and must be separated by at least one white

|               space.  All four columns are required under the [Submodel
|               Spec] keyword.  However, data is required only in the
typical
|               column.  If minimum and/or maximum values are not available,
|               the reserved word "NA" must be used to indicate the typical
|               value by default. 
|
|               The values in the minimum and maximum columns usually
|               correspond to the values in the same columns for the
inherited 
|               top-level voltage range or reference voltages in the
top-level 
|               model.  The V_trigger_r and V_trigger_f subparameters should
|               hold values in the minimum and maximum columns that
correspond
|               to the voltage range or reference voltages of the top-level
|               model.  The Off_delay subparameter, however, is an exception
|               to this rule because in some cases it may be completely or
|               or partially independent from supply voltages and/or
|               manufacturing process variations.  Therefore the minimum and
|               maximum entries for the Off_delay subparameter should be
|               ordered simply by their magnitude.
|
|               Unless noted, each [Submodel Spec] subparameter is
independent 
|               of any other subparameter.
|
|               V_trigger_r, V_trigger_f rules: 
|
|               The voltage trigger values for the rising and falling edges 
|               provide the starting time when an action is initiated.
|
|               Off_delay rules: 
|
|               The functionality of the Off_delay subparameter is to
provide
|               an additional time related mechanism to turn off circuit
|               elements.
|
|---------------------------------------------------------------------------
- -- 
| Dynamic Clamp Example:
|
[Submodel Spec]
|   Subparameter          typ        min        max 
|
V_trigger_r               3.6        2.9        4.3 | Starts power pulse
table 
V_trigger_f               1.4        1.2        1.6 | Starts gnd pulse table
|
| Bus Hold Example:
|
[Submodel Spec]
|   Subparameter          typ        min        max
V_trigger_r               3.1        2.4        3.7 | Starts low to high
                                                    | bus hold transition
V_trigger_f               1.8        1.6        2.0 | Starts high to low
                                                    | bus hold transition
|
| Bus_hold application with pullup structure triggered on and then clocked
off: 
|
[Submodel Spec]
|   Subparameter          typ        min        max
V_trigger_r               3.1        2.4        3.7 | Low to high transition
                                                    | triggers the turn on 
                                                    | process of the pullup
V_trigger_f             -10.0      -10.0      -10.0 | Not used, so trigger
                                                    | voltages are set out 
                                                    | of range
Off_delay                 5n         6n         4n  | Time from rising edge
                                                    | trigger at which the
                                                    | pullup turned off
|
|===========================================================================
==
|===========================================================================
==
|
| Bus Hold:
|
| When the Submodel_type subparameter under the [Submodel] keyword is set to

| Bus_hold, the added model describes the bus hold functionality.  However, 
| while described in terms of bus hold functionality, active terminators
| can also be modeled.
|
| Existing keywords and subparameters are used to describe bus hold models. 
| The [Pullup] and [Pulldown] tables both are used to define an internal
| buffer that is triggered switch to its opposite state.  This switching 
| transition is specified by a [Ramp] keyword or by the [Rising Waveform]
and
| [Falling Waveform] keywords.  The usage rules for these keywords are the 
| same as under the [Model] keyword.  In particular, at least either the
| [Pullup] or [Pulldown] keyword is required.  Also, the [Ramp] keyword is
| required, even if the [Rising Waveform] and [Falling Waveform] tables
exist. 
| However, the voltage ranges and reference voltages are inherited from the
| top-level model.
|
| For bus hold submodels, the [Submodel Spec] keyword, V_trigger_r, and
| V_trigger_f are required.  The Off_delay subparameter is optional, but can
| only be used if the submodel consists of a pullup or a pulldown structure
| only, and not both.  Devices which have both pullup and pulldown
structures
| controlled in this fashion can be modeled using two submodels, one for
each
| half of the circuit.
|
| The transition is triggered by action at the die using the [Submodel Spec]

| V_trigger_r and V_trigger_f subparameters as follows:
|
| If the starting voltage is below V_trigger_f, then the bus hold model is
set
| to the low state causing additional pulldown current.  If the starting 
| voltage is above V_trigger_r, the bus hold model is set to the high state
| for additional pullup current.  When the input passes though V_trigger_f
| during a high-to-low transition at the die, the bus hold output switches
to
| the low state.  Similarly, when the input passes though V_trigger_r during
| a low-to-high transition at the die, the bus hold output switches to the
| high state.
|
| If the bus hold submodel has a pullup structure only, V_trigger_r provides
| the time when its pullup is turned on and V_trigger_f or Off_delay
provides
| the time when it is turned off, whichever occurs first.  Similarly, if the
| submodel has a pulldown structure only, V_trigger_f provides the time when
| its pulldown is turned on and V_trigger_r or Off_delay provides the time
| when it is turned off, whichever occurs first.  The required V_trigger_r
| and V_trigger_f voltage entries can be set to values outside of the input
| signal range if the pullup or pulldown structures are to be held on until
| the Off_delay turns them off.
|
| The starting mode for each of the submodels which include the Off_delay
| subparameter of the [Submodel Spec] keyword is the off state.  Also, while
| two submodels provide the desired operation, either of the submodels may
| exist without the other to simulate turning on and off only a pullup or a
| pulldown current.
|
| No additional keywords are needed for this functionality. 
|---------------------------------------------------------------------------
- -- 
|
| Complete Bus Hold Model Example:
|
[Submodel]       Bus_hold_1
Submodel_type    Bus_hold
|
[Submodel Spec]
|   Subparameter          typ        min        max 
|
V_trigger_f               1.3        1.2        1.4  | Falling edge trigger 
V_trigger_r               3.1        2.6        4.6  | Rising edge trigger 
|
|                         typ        min        max
| [Voltage Range]           5.0        4.5        5.5
| Note, the actual voltage range and reference voltages are inherited from 
| the top-level model.
|
[Pulldown]
|
- -5V     -100uA     -80uA     -120uA
- -1V     -30uA      -25uA     -40uA
0V       0           0         0
1V       30uA       25uA     40uA
3V       50uA       45uA     50uA
5V       100uA      80uA     120uA
10v      120uA      90uA     150uA
|
[Pullup]
|
- -5V      100uA      80uA     120uA
- -1V      30uA       25uA     40uA
0V       0           0         0
1V      -30uA      -25uA    -40uA
3V      -50uA      -45uA    -50uA
5V      -100uA     -80uA    -120uA
10v     -120uA     -90uA    -150uA
|
|---------------------------------------------------------------------------
- -- 
|
[Ramp]
|                       typ             min             max 
dV/dt_r                 2.0/0.50n       2.0/0.75n       2.0/0.35n 
dV/dt_f                 2.0/0.50n       2.0/0.75n       2.0/0.35n 
R_load = 500
|
|---------------------------------------------------------------------------
- -- 
|
| Complete Pullup Timed Latch Example: 
|
[Submodel]       Timed_pullup_latch
Submodel_type    Bus_hold
|
[Submodel Spec]
|   Subparameter          typ        min        max 
|
V_trigger_r               3.1        2.6        4.6  | Rising edge trigger 
                                                     | Values could be set
out
                                                     | of range to disable
the
                                                     | trigger
V_trigger_f               1.3        1.2        1.4  | Falling edge
trigger[Submodel]       Dynamic_Output_r
Submodel_type    Fall_back
|
[Submodel Spec]
|   Subparameter          typ        min        max 
|
V_trigger_f             -10.0      -10.0      -10.0  | Falling edge trigger
                                                     | set out of range to 
                                                     | disable trigger
V_trigger_r               3.1        2.6        4.6  | Rising edge trigger 
|
|                         typ        min        max
| [Voltage Range]           5.0        4.5        5.5
| Note, the actual voltage range and reference voltages are inherited from 
| the top-level model.
|
[Pullup]
|
- -5V      100mA      80mA      120mA
0V       0           0         0
10v     -200mA     -160mA    -240mA
|
| [Pulldown] table omitted to signify an Open_source Submodel.
|
|---------------------------------------------------------------------------
- -- 
|
[Ramp]
|                       typ             min             max 
dV/dt_r                 1.5/0.50n       1.43/0.75n      1.58/0.35n 
dV/dt_f                 1.5/0.50n       1.43/0.75n      1.58/0.35n 
R_load = 50
|
|---------------------------------------------------------------------------
- -- 
[Submodel]       Dynamic_Output_r
Submodel_type    Fall_back
|
[Submodel Spec]
|   Subparameter          typ        min        max 
|
V_trigger_f             -10.0      -10.0      -10.0  | Falling edge trigger
                                                     | set out of range to 
                                                     | disable trigger
V_trigger_r               3.1        2.6        4.6  | Rising edge trigger 
|
|                         typ        min        max
| [Voltage Range]           5.0        4.5        5.5
| Note, the actual voltage range and reference voltages are inherited from 
| the top-level model.
|
[Pullup]
|
- -5V      100mA      80mA      120mA
0V       0           0         0
10v     -200mA     -160mA    -240mA
|
| [Pulldown] table omitted to signify an Open_source Submodel.
|
|---------------------------------------------------------------------------
- -- 
|
[Ramp]
|                       typ             min             max 
dV/dt_r                 1.5/0.50n       1.43/0.75n      1.58/0.35n 
dV/dt_f                 1.5/0.50n       1.43/0.75n      1.58/0.35n 
R_load = 50
|
|---------------------------------------------------------------------------
- -- 

Off_delay                 3n         5n         2n   | Delay to turn off the
                                                     | pullup table
|
| Note that if the input signal goes above the V_trigger_r value, the
| pulldown structure will turn off even if the timer didn't expire yet.
|
|                         typ        min        max
| [Voltage Range]         5.0        4.5        5.5
| Note, the actual voltage range and reference voltages are inherited from 
| the top-level model.
|
[Pulldown]
|
- -5V     -100uA     -80uA     -120uA
- -1V      -30uA     -25uA     -40uA
0V       0           0         0
1V       30uA       25uA     40uA
3V       50uA       45uA     50uA
5V       100uA      80uA     120uA
10v      120uA      90uA    150uA
|
| [Pullup] table is omitted to signal Open_source functionality 
|
|---------------------------------------------------------------------------
- -- 
|
[Ramp]
|                       typ             min             max 
dV/dt_r                 2.0/0.50n       2.0/0.75n       2.0/0.35n 
dV/dt_f                 2.0/0.50n       2.0/0.75n       2.0/0.35n 
R_load = 500
|
|===========================================================================
==

**** This section is added: 

|===========================================================================
==
|===========================================================================
==
|
| Fall Back:
|
| When the Submodel_type subparameter under the [Submodel] keyword is set to

| Fall_back, the added model describes the fall back functionality.  This
| submodel can be used to model drivers that reduce their strengths and
| increase their output impedances during their transitions.  The fall back
| function can be considered opposite of the bus hold function, but there
| some details discussed below that are unique. 
|
| Existing keywords and subparameters are used to describe fall back models.

| The [Pullup] and [Pulldown] tables both are used to define an internal
| buffer that is triggered switch to its opposite state.  This switching 
| transition is specified by a [Ramp] keyword or by the [Rising Waveform]
and
| [Falling Waveform] keywords.  The usage rules for these keywords are the 
| same as under the [Model] keyword.  In particular, at least either the
| [Pullup] or [Pulldown] keyword is required.  Also, the [Ramp] keyword is
| required, even if the [Rising Waveform] and [Falling Waveform] tables
exist. 
| However, the voltage ranges and reference voltages are inherited from the
| top-level model.
|
| For fallback submodels, the [Submodel Spec] keyword, V_trigger_r, and
| V_trigger_f are required.  Unlike the bus hold model, the Off_delay
| subparameter is not permitted.  Devices which have both pullup and
pulldown
| structures can be modeled using two submodels, one for the rising cycle
| and one for the falling cycle.
|
| The transition is triggered by action at the die using the [Submodel Spec]

| V_trigger_r and V_trigger_f subparameters as follows:
|
|   SIMULATOR RISING CYCLE:
|
|   Prior         Vdie            Rising Edge    Vdie > V_trigger_r
|   State                         Transition     Transition
|
|   low/none      <= V_trigger_r  low-to-high    high-to-low
|                 > V_trigger_r   Set/stays low  Stays low
|
|   high          <= V_trigger_r  Stays high     high-to-low
|                 > V_trigger_r   high-to-low    Stays low
|
|   SIMULATOR FALLING CYCLE:
|
|   Prior         Vdie            Falling Edge   Vdie < V_trigger_f
|   State                         Transition     Transition
|
|   high/none     => V_trigger_f  high-to-low    low-to-high
|                 < V_trigger_f   Set/stays high Stays high
|
|   low           <= V_trigger_f  Stays low      high-to-low
|                 > V_trigger_f   low-to-high    Stays high
|
|   The prior state of "none" describes the initial setting for the first
|   simulator edge encountered, either RISING or FALLING.  After that the
|   prior state is tracked.
|
| One application is to configure the submodel with one pullup structure
only.
| At the beginning of the rising edge cycle, the pullup is turned on to the
| high state.  When the die voltage passes V_trigger_r, the pullup structure
| is turned off.  Because only the pullup structure is used, the off state
is
| the same as a high-Z state.  During the falling transition, the pullup 
| remains in the high-Z state.  The V_trigger_f is set out of range, so no
| futher change of state occurs.  With this approach, the overall rising
| transition starts by turning the fall back submodel turned on.  This
| submodel is triggered to drop out after the output die voltage passes a
| trigger voltage, and it remains off until the next rising transition is
| initiated.
|
| A similar submodel consisting of only a pulldown structure could be
| constructed to provide added drive strength only at the beginning of the
| falling cycle.  The complete IBIS model would have both submodels to give
| added drive strength for both the start of the rising and the start of the
| falling cycles.
|
| No additional keywords are needed for this functionality. 
|---------------------------------------------------------------------------
- -- 
|
| Complete Dynamic Output Model Example Using Two Submodels:
|
[Submodel]       Dynamic_Output_r
Submodel_type    Fall_back
|
[Submodel Spec]
|   Subparameter          typ        min        max 
|
V_trigger_f             -10.0      -10.0      -10.0  | Falling edge trigger
                                                     | set out of range to 
                                                     | disable trigger
V_trigger_r               3.1        2.6        4.6  | Rising edge trigger 
|
|                           typ        min        max
| [Voltage Range]           5.0        4.5        5.5
| Note, the actual voltage range and reference voltages are inherited from 
| the top-level model.
|
[Pullup]
|
- -5V      100mA      80mA      120mA
0V       0           0         0
10v     -200mA     -160mA    -240mA
|
| [Pulldown] table omitted to signify an Open_source Submodel.
|
|---------------------------------------------------------------------------
- -- 
|
[Ramp]
|                       typ             min             max 
dV/dt_r                 1.5/0.50n       1.43/0.75n      1.58/0.35n 
dV/dt_f                 1.5/0.50n       1.43/0.75n      1.58/0.35n 
R_load = 50
|
|---------------------------------------------------------------------------
- -- 
|
[Submodel]       Dynamic_Output_f
Submodel_type    Fall_back
|
[Submodel Spec]
|   Subparameter          typ        min        max 
|
V_trigger_r               10.0       10.0       10.0 | Rising edge trigger
                                                     | set out of range to 
                                                     | disable trigger
V_trigger_f               1.3        1.2        1.4  | Falling edge trigger
|
|                           typ        min        max
| [Voltage Range]           5.0        4.5        5.5
| Note, the actual voltage range and reference voltages are inherited from 
| the top-level model.
|
[Pulldown]
|
- -5V     -100mA     -80mA     -120mA
0V       0           0         0
10v      200mA      160mA     240mA
|
| [Pullup] table omitted to signify an Open_drain Submodel.
|
|---------------------------------------------------------------------------
- -- 
|
[Ramp]
|                       typ             min             max 
dV/dt_r                 1.5/0.50n       1.43/0.75n      1.58/0.35n 
dV/dt_f                 1.5/0.50n       1.43/0.75n      1.58/0.35n 
R_load = 50
|
|---------------------------------------------------------------------------
- -- 

****************************************************************************
**

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

The AVC technology is structured using various trade marked terms such as
Dynamic Output Control(tm), Dynamic Control Output(tm), etc.  They are
designed to operate by starting at full strength, but finishing at a reduced
strength (higher impedance) when the output voltage passes through a trigger
voltage.  The final higher impedance usually matches better the load (such
as
a transmission line equivalent circuit of the printed circuit board trace)
to
produce better signal integrity matching conditions.

The operation is opposite of the Bus_hold submodel which is triggered to
turn on when the die voltage passes a threshold voltage.  So a bus hold
structure cannot be configured or modified to produce this "fall back"
effect.

BIRD73 proposes a new submodel which mimics the opposite effect.  The main
idea is that when the output voltage passes a trigger voltage, a rising
transition buffer changed to a falling transition, and a falling transition
buffer is changed to a rising transition.  The two existing [Submodel]
subparameters V_trigger_r and V_trigger_f are used for the fall back
operation.

Unlike the bus hold submodel, the rules for setting the initial state are
more complicated.  Furthermore, prior history or conditions could already
nullify some transitions.  Within a simulator rising edge cycle, 0, 1 or 2
transitions are possible.  One can be initiated at the start of the cycle,
and the other initiated when the output voltage passes V_trigger_r.  Several
initialization and switching conditions exist, and a table is used to
document the allowable fixed and transition states:

SIMULATOR RISING CYCLE:

  Prior         Vdie            Rising Edge    Vdie > V_trigger_r
  State                         Transition     Transition

  low/none      <= V_trigger_r  low-to-high    high-to-low
                > V_trigger_r   Set/stays low  Stays low

  high          <= V_trigger_r  Stays high     high-to-low
                > V_trigger_r   high-to-low    Stays low

SIMULATOR FALLING CYCLE:

  Prior         Vdie            Falling Edge   Vdie < V_trigger_f
  State                         Transition     Transition

  high/none     => V_trigger_f  high-to-low    low-to-high
                < V_trigger_f   Set/stays high Stays high

  low           <= V_trigger_f  Stays low      high-to-low
                > V_trigger_f   low-to-high    Stays high

The prior state of "none" describes the initial setting for the first
simulator edge encountered, either RISING or FALLING.  After that the
prior state is tracked.

The number of transitions for each simulator cycle is limited to two or
less.
It might be possible to connect several fall back and bus hold submodels in
a manner and with different V_trigger_r and V_trigger_f values to work 
against each other to cause the Vdie to move above and below the V_trigger_*
values several times within a cycle.  There does not appear to be any
practical reason to make the above state and transition tables more
complicated to account for opposite direction movement (or oscillation)
around V_trigger_*.  So after the RISING or FALLLING transitions are
initiated, some states are simply held constant regardless of potential
oscillations.  Such fixed stated are defined by "Stays high" or "Stays low".

The rules are set to work in a manner consistent with the bus hold submodel.
However, Off_delay subparameter is not supported here.  Nor is the opposite
acting subparameter proposed that might be called "Off_delay" that might
add one more transition reversal after a V_trigger_* transition.  There does
not appear to be any practical need for such an extension which would add
complication to the state and transition conditions above.

While a complete set of states and transitions are defined, the most
practical implementation for AVC technology is intended to be done with
adding two submodels, one with only a [Pullup] table for rising edge
impedance control, and one with only a [Pulldown] table for falling edge
impedance control.  With this setup, the corresponding "off" states will
be high-Z making each submodel function independently for each edge only
to increase the impedance of the final state of the buffer.  As in other
submodels, letting the V_trigger_* values to be set out of range is used
to keep the off state of the submodel in the high-Z mode.  This is shown
in an example.

The need for providing the new functionality currently exists and is
proposed
for IBIS Version 4.0 as a shorter term solution.  BIRD73 also provides the
basis for considering a more advanced solution that could be achieved using
a proposed IBIS-X Macro language.  This later solution could also provide
more
detail and a superset of what is currently practical for Version 4.0.

****************************************************************************
**

ANY OTHER BACKGROUND INFORMATION:

****************************************************************************
**

------------------------------

Date: Fri, 24 Aug 2001 08:37:15 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: IBIS Open Forum Meeting Agenda for 8/31

		     IBIS Open Forum Meeting Agenda
			      for 8/31/01

		 Bridge Number    Reservation #   Passcode
             (916) 356-2663   2                4779396

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Peters

     - Intros of New IBIS Participants, Meeting Quorum       Peters
     - Membership Update and Treasurers Report               Fleming/Ross
     - Review of Previous Meeting's Minutes (and ARs)        Peters
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Leventhal, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - pr EIAJ ED-5302 Standard for I/O Interface Model      
	  for Integrated Circuits (IMIC)                       Peters
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters
     - JEDEC JC-16 Modeling and Testing                      Sessions
     - T10, Project 1414-DT - SCSI Signal Modeling           Barnes

     PCBEAST 2001 IBIS Summit Meeting                        Ross

     DESIGNCON 2002 IBIS Summit Meeting Planning             Ross

     IBIS Model Review Committee                             Ross

     Majordomo Update                                        Angulo

     New Administrative Issues                               All

8:45 Technical Discussion

     Connector Proposal Report                               Peters/Ross

     IBIS Futures Group Report                               Peters

     BIRD72 - Accommodating PMOS and NMOS/PMOS Series FET    Dagostino/Ross
              Models

     BIRD73 - Fall Back Submodel                             Ross

     ibischk3 Status                                         Ross

     BUG59 - Crash with Decimal Points for [Package]         Mirmak
             Subparameters

     BUG60 - Incorrect Series Function Table Order           Ross
             Dependency

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Peters

9:55 Sign Off

------------------------------

Date: Mon, 27 Aug 2001 15:23:46 -0400
From: Kathy Breda <[email-masked]>
Subject: Reminder:  IBIS Summit - East 9/13/01

> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

> -------------------------------------------------------

> IBIS SUMMIT

>         FIRST CALL FOR

>                 PARTICIPATION,

>                         PRESENTATIONS

>                                 & SPONSORSHIP!!!!

> -------------------------------------------------------

> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

> 

>              I B I S   S U M M I T   M E E T I N G

> 

> Time/Date:      8:30 AM - 5:00 PM, Thursday, September 13, 2001

> 

> Location:       The Crowne Plaza Hotel

>                 10 Lincoln Square

>                 Worcester, MA

>                 Tel:  (508) 791-1600

>                 Fax:  (508) 791-1796

> 

> Content:        Presentations and Discussions

> 

> Purpose:        Solicit and Exchange IBIS Model Related Information and

Ideas.

> 

> Sponsors:       North East Systems Associates, Inc. (NESA),

>                 IBIS Users Group

>                 Others to be determined

>                 WE ARE LOOKING FOR ADDITIONAL SPONSORS!

>                   (contact Kathy Breda, [email-masked]

>                   or Bob Ross, [email-masked])

> 

> PCB Conference: September 10-14, 2001

> East            Worcester's Centrum Centre

>                 Worcester, Massachusetts

>                 See http://www.pcbeast.com/ for more information.

> 

> BACKGROUND

> 

> The IBIS Users Group (IBIS East) has been formed under the leadership of

> Dr. Edward Sayre from North East Systems Associates, Inc. (NESA) and has

> been meeting to consider and forward IBIS model user concerns.  As a

result

> of East coast meetings, the group has developed an IBIS Accuracy Handbook

> document and has initiated the project to format Connector Models.  These

> topics plus others of current interest to the EIA IBIS Open Forum will be

> discussed at this meeting.

> 

> This meeting will be conducted as a formal IBIS Summit Meeting.

Presentation

> are expected to be available and archived in an electronic format, and

minutes

> of the meeting will be issued.  Any pending formal decisions (votes) will

be

> announced at least two weeks prior to the meeting.

> 

> CALL FOR PARTICIPANTS

> 

> People involved in IBIS Model development, EDA tool development, and

digital

> circuit design are invited to participate to the Summit meeting.  If you

plan

> to participate, please register with the information below:

> 

>   Name:

>   E-mail address:

>   Company:

>   Telephone:

> 

> Send to:

> 

>   Kathy Breda ([email-masked])

> 

> 

> CALL FOR PRESENTATIONS

> 

> We are seeking presentations from individuals who have IBIS experiences

> or issues.

> 

> Format of Presentation:  Overhead Projections

> Time:                    15-30 Minutes

> Electronic Archival:     We request electronic versions so that the

>                          presentations can be archived and also made

>                          available to non-attendees.  Formats used in

>                          the past have been text, Power Point, Word,

>                          Postscript, and Acrobat.  Electronic

presentations

>                          should be made available by September 7, 2001.

>                          Otherwise the presenter will be expected to

provide

>                          up to 50 copies for distribution.

> 

> If you plan a presentation, please supply

> 

>   Title:

>   Presenter:

>   E-mail address:

>   Company:

>   Telephone:

> 

>   Estimate Time:

> 

> Send this to:

> 

>   Kathy Breda ([email-masked])

> 

> AGENDA

> 

> The agenda includes presentations, discussions, breaks, and a luncheon

(which

> will be provided).  This will be developed as presentation proposals are

> received.  So far the following presentatation is planned:

> 

>   "A Proposal for s2ibis3", Michael Steer, North Carolina State University

> 

>   "Modeling the Radiated Emission of Micro-controllers", Etienne Sicard,

>   National Institute of Applied Science (INSA/DEIG), France

> 

>   Plus IBIS Macro Language and demonstration, IBIS Connector

Specification,

>   and other IBIS issues.

> 

> LIST OF NEARBY HOTELS

> 

> See http://www.pcbeast.com for travel directions, hotels and other

> information.

> 

> **************************************************************

<bold><color><param>0000,0000,8080</param><bigger>

</bigger></color></bold><excerpt>

<center>_____________________________________________________________________________________________________

</center>

<center>Kathy Breda  | Director of Marketing

North East Systems Associates, Inc.  |  5 LAN Drive, Suite 200  |
Westford, MA 01886 

[T]  978-392-8787      [F]  978-392-8686    [W] www.nesa.com 

</center></excerpt>

------------------------------

Date: Mon, 27 Aug 2001 16:40:53 -0500
From: [email-masked]
Subject: Re: IBIS Open Forum Meeting Agenda for 8/31

All,

I'll be out of town and unable to attend. I'm retesting the model links as I
write this.

Best Regards,

Roy

------------------------------

Date: Tue, 28 Aug 2001 08:35:59 -0700
From: "Ross, Bob" <[email-masked]>
Subject: IBIS SUMMIT THIRD CALL REMINDER

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C12FD7.70CC5D00
Content-Type: text/plain

To All:

Here is an updated reminder with more presentation
detail.

Bob Ross
Mentor Graphics

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~  
- -------------------------------------------------------  
IBIS SUMMIT   
        THIRD CALL FOR   
                PARTICIPATION &  
                        PRESENTATIONS!!!   
- -------------------------------------------------------  
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~  

             I B I S   S U M M I T   M E E T I N G  

Time/Date:   8:30 AM - 5:00 PM, Thursday, September 13, 2001  

Location:    The Crowne Plaza Hotel  
             10 Lincoln Square  
             Worcester, MA  
             Tel:  (508) 791-1600  
             Fax:  (508) 791-1796  
                 
Content:     Presentations and Discussions  

Purpose:     Solicit and Exchange IBIS Model Related Information and Ideas.

Sponsors:    North East Systems Associates, Inc. (NESA),  
             IBIS Users Group
             Mentor Graphics
             IBIS Open Forum
             WE ARE LOOKING FOR ADDITIONAL SPONSORS!  
                  (contact Kathy Breda, [email-masked]  
                  or Bob Ross, [email-masked])  

PCB Conference: September 10-14, 2001  
East            Worcester's Centrum Centre  
                Worcester, Massachusetts  
                See http://www.pcbeast.com/ for more information.  

BACKGROUND  

The IBIS Users Group (IBIS East) has been formed under the leadership of    
Dr. Edward Sayre from North East Systems Associates, Inc. (NESA) and has  
been meeting to consider and forward IBIS model user concerns.  As a result

of East coast meetings, the group has developed an IBIS Accuracy Handbook  
document and has initiated the project to format Connector Models.  These  
topics plus others of current interest to the EIA IBIS Open Forum will be  
discussed at this meeting.  

This meeting will be conducted as a formal IBIS Summit Meeting.
Presentation  
are expected to be available and archived in an electronic format, and
minutes  
of the meeting will be issued.  Any pending formal decisions (votes) will be

announced at least two weeks prior to the meeting.  

CALL FOR PARTICIPANTS  

People involved in IBIS Model development, EDA tool development, and digital

circuit design are invited to participate to the Summit meeting.  If you
plan  
to participate, please register with the information below:  

  Name:  
  E-mail address:  
  Company:  
  Telephone:  

Send to:  

  Kathy Breda ([email-masked])  

CALL FOR PRESENTATIONS  

We are seeking presentations from individuals who have IBIS experiences  
or issues.  

Format of Presentation:  Overhead Projections  
Time:                    15-30 Minutes  
Electronic Archival:     We request electronic versions so that the  
                         presentations can be archived and also made  
                         available to non-attendees.  Formats used in  
                         the past have been text, Power Point, Word,   
                         Postscript, and Acrobat.  Electronic presentations

                         should be made available by September 7, 2001.  
                         Otherwise the presenter will be expected to provide

                         up to 50 copies for distribution.  

If you plan a presentation, please supply  

  Title:  
  Presenter:  
  E-mail address:  
  Company:  
  Telephone:  

  Estimate Time:  

Send this to:  

  Kathy Breda ([email-masked])  

AGENDA  

The agenda includes presentations, discussions, breaks, and a luncheon
(which  
will be provided).  This will be developed as presentation proposals are  
received.  So far the following presentations are planned:  
    
  "A Proposal for s2ibis3", Michael Steer, North Carolina State University  

  "Modeling the Radiated Emission of Micro-controllers", Etienne Sicard,  
  National Institute of Applied Science (INSA/DEIG), France  

  "Power/Ground Simulation with IBIS Models and Pin Mapping Issues",  
  Raj Raghuram, Sigrity, Inc.  

  "From Model Creator to Model User", Bob Haller, Cereva  

  Plus IBIS Macro Language and demonstration, IBIS Connector Specification,

  and other IBIS issues.  

LIST OF NEARBY HOTELS  

See http://www.pcbeast.com for travel directions, hotels and other  
information.  

**************************************************************

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2653.12">
<TITLE>IBIS SUMMIT THIRD CALL REMINDER</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>To All:</FONT>
</P>

<P><FONT SIZE=3D2>Here is an updated reminder with more =
presentation</FONT>
<BR><FONT SIZE=3D2>detail.</FONT>
</P>

<P><FONT SIZE=3D2>Bob Ross</FONT>
<BR><FONT SIZE=3D2>Mentor Graphics</FONT>
</P>
<BR>

<P><FONT =
SIZE=3D2>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~&nbsp; =
</FONT>
<BR><FONT =
SIZE=3D2>-------------------------------------------------------&nbsp; =
</FONT>
<BR><FONT SIZE=3D2>IBIS SUMMIT&nbsp;&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; THIRD =
CALL FOR&nbsp;&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; PARTICIPATION &amp;&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp; PRESENTATIONS!!!&nbsp;&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>-------------------------------------------------------&nbsp; =
</FONT>
<BR><FONT =
SIZE=3D2>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~&nbsp; =
</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; I B I S&nbsp;&nbsp; S U M M I T&nbsp;&nbsp; M E E T I N =
G&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>Time/Date:&nbsp;&nbsp; 8:30 AM - 5:00 PM, Thursday, =
September 13, 2001&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>Location:&nbsp;&nbsp;&nbsp; The Crowne Plaza =
Hotel&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; 10 Lincoln Square&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Worcester, MA&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Tel:&nbsp; (508) 791-1600&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Fax:&nbsp; (508) 791-1796&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; </FONT>
<BR><FONT SIZE=3D2>Content:&nbsp;&nbsp;&nbsp;&nbsp; Presentations and =
Discussions&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>Purpose:&nbsp;&nbsp;&nbsp;&nbsp; Solicit and Exchange =
IBIS Model Related Information and Ideas.&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>Sponsors:&nbsp;&nbsp;&nbsp; North East Systems =
Associates, Inc. (NESA),&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; IBIS Users Group</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Mentor Graphics</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; IBIS Open Forum</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; WE ARE LOOKING FOR ADDITIONAL SPONSORS!&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (contact Kathy Breda, =
[email-masked]&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; or Bob Ross, =
[email-masked])&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>PCB Conference: September 10-14, 2001&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>East&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp; Worcester's Centrum Centre&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; Worcester, Massachusetts&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; See <A HREF=3D"http://www.pcbeast.com/" =
TARGET=3D"_blank">http://www.pcbeast.com/</A> for more =
information.&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>BACKGROUND&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>The IBIS Users Group (IBIS East) has been formed =
under the leadership of&nbsp;&nbsp;&nbsp; </FONT>
<BR><FONT SIZE=3D2>Dr. Edward Sayre from North East Systems Associates, =
Inc. (NESA) and has&nbsp; </FONT>
<BR><FONT SIZE=3D2>been meeting to consider and forward IBIS model user =
concerns.&nbsp; As a result&nbsp; </FONT>
<BR><FONT SIZE=3D2>of East coast meetings, the group has developed an =
IBIS Accuracy Handbook&nbsp; </FONT>
<BR><FONT SIZE=3D2>document and has initiated the project to format =
Connector Models.&nbsp; These&nbsp; </FONT>
<BR><FONT SIZE=3D2>topics plus others of current interest to the EIA =
IBIS Open Forum will be&nbsp; </FONT>
<BR><FONT SIZE=3D2>discussed at this meeting.&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>This meeting will be conducted as a formal IBIS =
Summit Meeting.&nbsp; Presentation&nbsp; </FONT>
<BR><FONT SIZE=3D2>are expected to be available and archived in an =
electronic format, and minutes&nbsp; </FONT>
<BR><FONT SIZE=3D2>of the meeting will be issued.&nbsp; Any pending =
formal decisions (votes) will be&nbsp; </FONT>
<BR><FONT SIZE=3D2>announced at least two weeks prior to the =
meeting.&nbsp; </FONT>
</P>
<BR>

<P><FONT SIZE=3D2>CALL FOR PARTICIPANTS&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>People involved in IBIS Model development, EDA tool =
development, and digital&nbsp; </FONT>
<BR><FONT SIZE=3D2>circuit design are invited to participate to the =
Summit meeting.&nbsp; If you plan&nbsp; </FONT>
<BR><FONT SIZE=3D2>to participate, please register with the information =
below:&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>&nbsp; Name:&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp; E-mail address:&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp; Company:&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp; Telephone:&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>Send to:&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>&nbsp; Kathy Breda ([email-masked])&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>CALL FOR PRESENTATIONS&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>We are seeking presentations from individuals who =
have IBIS experiences&nbsp; </FONT>
<BR><FONT SIZE=3D2>or issues.&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>Format of Presentation:&nbsp; Overhead =
Projections&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>Time:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 15-30 =
Minutes&nbsp; </FONT>
<BR><FONT SIZE=3D2>Electronic Archival:&nbsp;&nbsp;&nbsp;&nbsp; We =
request electronic versions so that the&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; presentations can be archived and also made&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; available to non-attendees.&nbsp; Formats used in&nbsp; =
</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; the past have been text, Power Point, Word,&nbsp;&nbsp; =
</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Postscript, and Acrobat.&nbsp; Electronic presentations&nbsp; =
</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; should be made available by September 7, 2001.&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Otherwise the presenter will be expected to provide&nbsp; =
</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; up to 50 copies for distribution.&nbsp; </FONT>
</P>
<BR>

<P><FONT SIZE=3D2>If you plan a presentation, please supply&nbsp; =
</FONT>
</P>

<P><FONT SIZE=3D2>&nbsp; Title:&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp; Presenter:&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp; E-mail address:&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp; Company:&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp; Telephone:&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>&nbsp; Estimate Time:&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>Send this to:&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>&nbsp; Kathy Breda ([email-masked])&nbsp; </FONT>
</P>
<BR>

<P><FONT SIZE=3D2>AGENDA&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>The agenda includes presentations, discussions, =
breaks, and a luncheon (which&nbsp; </FONT>
<BR><FONT SIZE=3D2>will be provided).&nbsp; This will be developed as =
presentation proposals are&nbsp; </FONT>
<BR><FONT SIZE=3D2>received.&nbsp; So far the following presentations =
are planned:&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp; &quot;A Proposal for s2ibis3&quot;, Michael =
Steer, North Carolina State University&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>&nbsp; &quot;Modeling the Radiated Emission of =
Micro-controllers&quot;, Etienne Sicard,&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp; National Institute of Applied Science =
(INSA/DEIG), France&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>&nbsp; &quot;Power/Ground Simulation with IBIS Models =
and Pin Mapping Issues&quot;,&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp; Raj Raghuram, Sigrity, Inc.&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>&nbsp; &quot;From Model Creator to Model User&quot;, =
Bob Haller, Cereva&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>&nbsp; Plus IBIS Macro Language and demonstration, =
IBIS Connector Specification,&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp; and other IBIS issues.&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>LIST OF NEARBY HOTELS&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>See <A HREF=3D"http://www.pcbeast.com" =
TARGET=3D"_blank">http://www.pcbeast.com</A> for travel directions, =
hotels and other&nbsp; </FONT>
<BR><FONT SIZE=3D2>information.&nbsp; </FONT>
</P>

<P><FONT =
SIZE=3D2>**************************************************************<=
/FONT>
</P>

</BODY>
</HTML>
- ------_=_NextPart_001_01C12FD7.70CC5D00--

------------------------------

Date: Wed, 29 Aug 2001 11:22:42 -0700
From: "John Angulo" <[email-masked]>
Subject: Test: please ignore

Test msg only...

John Angulo
IBIS Open Forum Postmaster

------------------------------

Date: Wed, 29 Aug 2001 14:48:20 -0400
From: Kathy Breda <[email-masked]>
Subject: Updated with presentations - IBIS Summit Announcement

>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~  

>-------------------------------------------------------  

>IBIS SUMMIT   

>        THIRD CALL FOR   

>                PARTICIPATION &  

>                        PRESENTATIONS!!!   

>-------------------------------------------------------  

>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~  

>

>             I B I S   S U M M I T   M E E T I N G  

>

>Time/Date:   8:30 AM - 5:00 PM, Thursday, September 13, 2001  

>

>Location:    The Crowne Plaza Hotel  

>             10 Lincoln Square  

>             Worcester, MA  

>             Tel:  (508) 791-1600  

>             Fax:  (508) 791-1796  

>                 

>Content:     Presentations and Discussions  

>

>Purpose:     Solicit and Exchange IBIS Model Related Information and Ideas.

>

>

>Sponsors:    North East Systems Associates, Inc. (NESA),  

>             IBIS Users Group

>             Mentor Graphics

>             IBIS Open Forum

>             WE ARE LOOKING FOR ADDITIONAL SPONSORS!  

>                  (contact Kathy Breda, [email-masked]  

>                  or Bob Ross, [email-masked])  

>

>PCB Conference: September 10-14, 2001  

>East            Worcester's Centrum Centre  

>                Worcester, Massachusetts  

>                See http://www.pcbeast.com/ for more information.  

>

>BACKGROUND  

>

>The IBIS Users Group (IBIS East) has been formed under the leadership of    

>Dr. Edward Sayre from North East Systems Associates, Inc. (NESA) and has  

>been meeting to consider and forward IBIS model user concerns.  As a result

>

>of East coast meetings, the group has developed an IBIS Accuracy Handbook  

>document and has initiated the project to format Connector Models.  These  

>topics plus others of current interest to the EIA IBIS Open Forum will be  

>discussed at this meeting.  

>

>This meeting will be conducted as a formal IBIS Summit Meeting.

>Presentation  

>are expected to be available and archived in an electronic format, and

>minutes  

>of the meeting will be issued.  Any pending formal decisions (votes) will be

>

>announced at least two weeks prior to the meeting.  

>

>

>CALL FOR PARTICIPANTS  

>

>People involved in IBIS Model development, EDA tool development, and digital

>

>circuit design are invited to participate to the Summit meeting.  If you

>plan  

>to participate, please register with the information below:  

>

>  Name:  

>  E-mail address:  

>  Company:  

>  Telephone:  

>

>Send to:  

>

>  Kathy Breda ([email-masked])  

>    

>

>CALL FOR PRESENTATIONS  

>

>We are seeking presentations from individuals who have IBIS experiences  

>or issues.  

>

>Format of Presentation:  Overhead Projections  

>Time:                    15-30 Minutes  

>Electronic Archival:     We request electronic versions so that the  

>                         presentations can be archived and also made  

>                         available to non-attendees.  Formats used in  

>                         the past have been text, Power Point, Word,   

>                         Postscript, and Acrobat.  Electronic presentations

>

>                         should be made available by September 7, 2001.  

>                         Otherwise the presenter will be expected to provide

>

>                         up to 50 copies for distribution.  

>

>

>If you plan a presentation, please supply  

>

>  Title:  

>  Presenter:  

>  E-mail address:  

>  Company:  

>  Telephone:  

>

>  Estimate Time:  

>

>Send this to:  

>

>  Kathy Breda ([email-masked])  

>

>

>AGENDA  

>

>The agenda includes presentations, discussions, breaks, and a luncheon

>(which  

>will be provided).  This will be developed as presentation proposals are  

>received.  So far the following presentations are planned:  

>    

>  "A Proposal for s2ibis3", Michael Steer, North Carolina State University  

>

>  "Modeling the Radiated Emission of Micro-controllers", Etienne Sicard,  

>  National Institute of Applied Science (INSA/DEIG), France  

>

>  "Power/Ground Simulation with IBIS Models and Pin Mapping Issues",  

>  Raj Raghuram, Sigrity, Inc.  

>

>  "From Model Creator to Model User", Bob Haller, Cereva  

>

>  Plus IBIS Macro Language and demonstration, IBIS Connector Specification,

>

>  and other IBIS issues.  

>

>LIST OF NEARBY HOTELS  

>

>See http://www.pcbeast.com for travel directions, hotels and other  

>information.  

>

>**************************************************************

>

>

<bold><color><param>0000,0000,8080</param><bigger>

</bigger></color></bold><excerpt>

<center>_____________________________________________________________________________________________________

</center>

<center>Kathy Breda  | Director of Marketing

North East Systems Associates, Inc.  |  5 LAN Drive, Suite 200  |
Westford, MA 01886 

[T]  978-392-8787      [F]  978-392-8686    [W] www.nesa.com 

</center></excerpt>

------------------------------

Date: Tue, 4 Sep 2001 10:18:00 -0700
From: [email-masked] (Guy de Burgh)
Subject: EIA IBIS Open Forum Meeting Minutes

DATE: 9/4/01

SUBJECT: August 31, 2001 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2001 PARTICIPANTS LIST:
3Com (& CommWorks)             Roy Leventhal
Ansoft Corporation             (Eric Bracken)
Apple Computer                 John Figueroa
Applied Simulation Technology  [Raj Raghuram], Norio Matsui,
                               Fred Balistreri
Avanti                         (Chen Hongyu)
Cadence Design                 [Ian Dodd], Patrick Dos Santos, Heiko Dudek,
                               Lynne Green*, Lance Wang*
Cisco Systems                  Syed Huq, Lungfu Chen
Cypress Semiconductor          (Rajesh Manapat)
EMC Corporation                Brian Arsenault, Jinhua Chen
Fairchild Semiconductor        Adam Tambone
Huawei Technologies            Rachild Chen
IBM                            Michael Cohen, Greg Edlund*, Wes Martin,
                               Yeon-Chang Hahm, Bill DeVey, Pravin Patel*
Innoveda (& HyperLynx)         Guy de Burgh*, John Angulo*, Cary Mandel, 
                               Matthew Flora, Steve Kaufer
Intel Corporation              Stephen Peters*, Arpad Muranyi*,
                               Dave Lorang, Michael Mirmak*, Qinglun Chen,
                               Will Hobbs, Wei-hsing Huang
LSI Logic                      Larry Barnes
Mentor Graphics                Bob Ross*, Tom Dagostino*, Chris Reid,
                               Mike Donnelly, Hazem Hegazy, Tony Dunbar,
                               Griff Derryberry, Dan Lake, Sherif Hammad,
                               Mohammed Korany, Weston Beal, Chris Swaim,
                               Ali Samii, Eric Ronger, Karine Loudet,
                               Daisaku Shiga, Kenji Kushima, Ian Dodd*
Micron Technology              Randy Wolff*, Yong Phan*
Mitsubishi                     Pat Hefferan
Molex Incorporated             Gus Panella, Brian O'Malley
National Semiconductor         Milt Schwartz
North East Systems Associates  Edward Sayre
Philips Semiconductor          Zack Ciccone, Rob Mataheroe
Quantic EMC                    (Mike Ventham)
Signal Integrity Software      Douglas Burns, Barry Katz, Walter Katz
Sigrity                        Raj Raghuram*
SiQual                         Scott McMorrow, Rob Hinz, Bernard Voss,
                               Chris Brewster
Texas Instruments              Thomas Fisher, Stephen Nolan, Ramzi Ammar,
                               Jean Claude Perrin, Moshiul Haque
Time Domain Analysis Systems   Dima Smolyansky, Steve Corey
Tyco Electronics               (Russell Moser)
Via Technologies               (Weber Chuang)
Zuken (& Incases)              John Berrie, Ralf Bruening

OTHER PARTICIPANTS IN 2001:
Actel Corporation              Silvia Montoya
Acuson                         Kim Helliwell
AMCC                           Jeff Smith
ASIS Ltd                       David Wright
Brocade Communications         Robert Badal
BMW                            Friedrich Hasinger
Cereva Networks                Bob Haller
Compaq                         [Peter LaFlamme], Ron Bellomio, Quang Dam,
                               Bill Ham
EADS Airbus Industry           Claude Huet
  (Aerospatiale)
EFM                            Ekkehard Miersch, Horle Raines
EIA                            Cecilia Fleming
Ericsson Radio Systems         Anders Ekholm
FCI                            Sercu Stefaan
Foundary Networks              Bertram Chan
Framatom Conectors             Danny Morlion
Fraunhofer Institute           Mariusz Faferko, Peter Kralicek
  Reliability and
  Integration
Fujitsu Ltd                    Tadashi Arai, Takeshi Murakami
Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt
Hyundai Electronics            Jongho Kang
Idaho State University         Al Davis
Infineon Technologies          Christian Sporrer
Intrinsix Corporation          Steven Chin
Motorola                       (Rick Kingen)
National Institute of Applied  Etienne Sicard
  Science (INSA)
Nokia                          Tapani von Ravner, Mika Castren,
                               Janne Uusitalo
Nortel Networks                Calvin Trowell
Oak Technology                 Darmin Jin
Plexus Technology Group        Joseph Socha
Siemens (& Automotive) AG      Bernhard Unger, Helmut Katzier,
                               Katja Koller, Wolfram Meyer, Eckhard Lenski,
                               Gerald Bannert, Burkhard Muller,
                               Christian Marot, Manfred Maurer,
                               Amir Motamedi, Hans Pichlmaier
Sintecs                        Hans Klos
STMicroelectronics             Peter Hirt, Fabrice Boissieres
Sun                            Adrian Udenze
Toshiba Corp.                  Hirokaza Kato, Yuichi Koga, Toshio Sudo
Xilinx                         Susan Wu

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are
as follows:

  Date                Bridge Number    Reservation #    Passcode
  Thursday, September 13, 2001 IBIS Summit Meeting, No Phone Bridge

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after.  When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES -----------------------------------

INTRODUCTIONS AND MEETING QUORUM
No new participants

MEMBERSHIP UPDATE AND TREASURER'S REPORT
Stephen Peters reported that we have 31 new members, with one more 
prospect.  We had projected 30 members for the year, so we are ahead of 
budget.

REVIEW OF MINUTES AND AR'S
The August 10, 2001 IBIS Minutes were approved without change.

The ARs were discussed during the meeting.

MISCELLANY/ANNOUNCEMENTS
None

PRESS AND WEB PAGE UPDATES
Bob Ross noted that Syed Huq and Cecilia Fleming did several Web updates 
(Roster, Upcoming Events).

A top-level "Ver 4.0 Work In Progress" link on the web site has been updated
with the latest Ver 4.0 draft. This unofficial draft includes the recently 
passed Birds 70.5 and 71.

Bob reported that Zuken is offering a free "ibisinf" utility that works on
several platforms and can be downloaded from:

  http://www.zuken.com/ibis/  or

  http://www.zuken.com/solutions_board_ibis.asp

Stephen Peters asked what it produces.  Bob responded that it provides model
information including subparameter values (e.g., Vinh, Vmeas), I-V and V-T
table informations (e.g, R_fixture value of each table).  It also provides
component information including how many pins are modeled.

Bob reported that Syed added a link to this under the FREE Tools section 
of the IBIS Home page.

Bob reported that Roy Leventhal is checking and updating the links on the
Models page.

Stephen added that he has invited a newly formed Signal Integrity Technical
Committee within the EMC Society (and announced on the SI reflector) to
inform the IBIS community of its activities.

NEW MODELS AVAILABLE, LIBRARY UPDATE
No new models or library updates were reported.

OPENS FOR NEW ISSUES
None

INTERNATIONAL/EXTERNAL PROGRESS
- - JEITA ED-5302 Standard for I/O Interface Model for Integrated Circuits
  (IMIC) -  No report.

- - IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal
  (formerly, IEC 93/67/NP IBIS and EMC Simulation) - Stephen Peters reported
  the Jean-Claude Perrin sent him an email stating that the document is
  now officially stored as an IEC technical document. Bob Ross will ask
  Cecilia Fleming if she can find the link.

- - JEDEC JC-16 - Modeling and Testing - No report.

- - T10, Project 1414-DT - SCSI Signal Modeling (a Technical Committee of the
  National Committee for Information Technology (NCITS)) - No report.

PCB CONFERENCE EAST 2001 IBIS SUMMIT MEETING PLANS
Stephen Peters reported that an IBIS Summit Meeting is planned for Thursday,
September 13, 2001 in Worcester, Massachusetts at the Crowne Plaza Hotel
near the PCB Conference East 2001 show.  The meeting follows the day after
the trade show portion of the show.  The Upcoming events link of the IBIS
home page already contains the sign-up information and hotel information.
Free lunch and refreshments are included.

The third announcement has been sent out. Bob Ross reports that we still
expect about 20 people.  Some local people have not signed up yet, and
Stephen urged those that have not signed up to do so.

To date, four presentations are planned (titles may change):

  "Modeling the Radiated Emission of Micro-controllers", Etienne Sicard,
     National Institute of Applied Science (INSA) in France

  "A Proposal for s2ibis3", Michael Steer, North Carolina State University

  "Power/Ground Simulation with IBIS Models and Pin Mapping Issues", 
     Raj Raghuram, Sigrity, Inc.  

  "From Model Creator to Model User", Bob Haller, Cereva Networks

Stephen added these presentations from the Working Groups:

  "Progress and Update in the Connector Specification",
     Stephen Peters, Intel

  "Progress and Issues in IBIS-X", Stephen Peters, Intel

  "IBIS-X Primitives and Example", Lynne Green, Cadence Design

Bob added later that we will work with Stephen and Kathy Breda and send
out an agenda on Thursday, September 6, 2001.  He will also work with the
presenters to get the presentations in by Friday, September 7 for copying.
Otherwise the presenters should expect to bring 30 copies.

Bob also added that the sponsors to date are Mentor Graphics, NESA, the
IBIS Users Group, and the IBIS Open Forum.

DESIGNCON 2002 IBIS SUMMIT MEETING
Stephen Peters reported on the plans for the IBIS Summit Meeting scheduled
on Monday, January 28, 2002 associated with DesignCon 2002 in Santa Clara,
California.  We will an Associate Sponsor.  A large meeting room and
refreshments will be provided.  We will also plan on a booth, and Guy de
Burgh will be handling the arrangements.  Innoveda will be providing 
the backdrop.

Stephen reported that National Semiconductor will sponsor the lunch, as
before.  We might require a signup for lunch this time to keep the costs
reasonable.  

Most of the initial plans are complete.  We will be sending out the
meeting announcements and call for presentations later this year.

IBIS MODEL REVIEW COMMITTEE DISCUSSION
John Angulo reported that Texas Instrument model has been sent out for
review.  Another model has been received and John will forward it to
Bob Ross.  Bob also stated that he will update the IBIS home page 
email link with his email address.  John also mentioned that Jon Powell of
Innoveda has expressed an interest in taking on the IBIS Model Review 
function.  John Angulo will follow up.

MAJORDOMO UPDATE
John Angulo reported that the [email-masked] list is now propagating fully.  
Stephen Peters asked if posters still need to copy the ibis-users reflector
when they post to the main IBIS relector.  After a short discussion we 
agreed that this procedure was no longer needed.  John took the AR to issue
a note that effect to the reflector.

John then reported that we still have some archive difficulties linking
to *.txt attachments (this needs to done manually) and with ASCII formatted
data (the white space information is hard to restore).  We are working on
these issues.  Bob Ross added that we have been moving the location under
the IBIS FTP site and plan to open up another archive that currently only
the system administrators can read.  That may help resolve the white space
archive problem.

John added that Majordomo subscriptions require his approval, but
unsubscribe requests are handled automatically. 

When this is accomplished we will plan to move the ibis-users list under
Majordomo as well.  This may possibly occur next week.

CONNECTOR PROPOSAL REPORT
Stephen Peters reported that connector meetings were held August 14, 21 and 
the 28, with the next one scheduled for Sept 4.  The major topic at these 
meetings have been understanding the three different ways a connector can
be described and which keywords apply in which cases.  In the course of
these discussions we simplified some keywords and eliminated some others.
The connector committee also uncovered an issue with extracting cascaded
matrixes that effects pin order to matrix row mapping.  This will require
additional work to solve.

No connector meeting is scheduled for September 11.

IBIS FUTURES REPORT
Stephen Peters reported that the IBIS Futures group meet on August 16, 23
and 30 with the next meeting scheduled for Sept. 6.  The Futures group has
been concentrating on transmission line matrix format as well as some
documentation issues.  Stephen also reported that a proposal has been made
to the IBIS Futures group to incorporate the IBIS-X 'define' functionality
directly into the current IBIS data template via a BIRD, thus creating a 
relatively straightforward path for adoption of IBIS-X and the macro
language into current IBIS.  This BIRD would be issued sometime after
IBIS 4.0 was voted on by the IBIS Open Forum (i.e. it would not effect the
current progress towards IBIS 4.0).  The Futures committee accepted the
proposal as the best way to move forward with IBIS-X.

Because of the IBIS east summit, no futures committee meeting is scheduled
for September 13.

BIRD72 - ACCOMMODATING PMOS AND NMOS//PMOS SERIES FET MODELS
Tom Dagostino introduced BIRD72 by reporting that he has created Switch
models from measurement.  IBIS Version 3.2 assumes that the Series MOSFET
is an N channel device.  Tom has observed P channel and parallel P/N
channel paths.  Warning and Error messages are now generated for I-V
tables for such devices.

BIRD72 contains some changes in the notation and equations that allow for
describing these additional I-V tables.  The ibischk3 parser would be
revised so that Error messages are not issued for decreasing currents.

Stephen Peters wanted some clarification regarding the Vgs and Voltage.
Tom responded that for P/N MOSFET configurations, the gate voltage was
ambiguous.  So Voltage is used in the table, and the Vgs reference is
removed.  Lynne Green wanted to know if a different I-V table was needed,
and Tom responded that the same I-V table is used.  Raj Raghuram questioned
whether the tables worked for enhanced and depletion mode FETs.  Tom
thought that the I-V tables should still represent the data.  Bob Ross
noted that there were a few editorial corrections needed.

Stephen stated that with some clarifications, a revised BIRD72.1 might be
ready for a vote in October, 2001.

AR - Tom Dagostino will issue BIRD72.1 with the discussed editorial changes
and clarifications.

BIRD73 - FALL BACK SUBMODEL
Bob Ross introduced BIRD73 by noting that IBIS Version 3.2 does not cover
the AVC technology devices offered by about four manufacturers.  This
technology has a stage turn off during the transition to weaken the overall
driver at the end.  This weaker driver may have an output resistance that
provides a better match to the transmission line load.

Bob stated that the existing Bus Hold submodel works in the opposite manner.
It can be triggered to provide a stronger drive.  So a new Fall Back
submodel is introduced.  One complication is that the state changes for
turning off a device are more difficult to describe.  The SIMULATOR RISING
CYCLE: and SIMULATOR FALLING CYCLE: tables in the documentation attempts to
do this.  Both a rising or falling edge transition and a voltage trigger
may cause a buffer state change.  The table attempts to characterize what
the model will do under all conditions including an ambiguous initial state.

Bob indicated that the example really illustrates an application with ideal
50 Ohm submodels configured as Open_drain and Open_source models.  This
assures that the off state is also a high-Z state that provides no load.
He also noted that the V_trigger_* values can be sent out of range to
assure no unwanted triggering can occur.  Unlike the Bus Hold submodel, the 
Off_delay subparameter is not defined.

Stephen Peters noted that BIRD73 incorrectly copied the Fall Back example as
the existing Bus Hold example.  Bob will correct this.  He will also make
a correction to an Off_delay example.  Bob also noted that BIRD73 is a
candidate for prototyping in the macro language.

Stephen also suggested adding a "state" table to the Bus hold example.

AR - Bob Ross will issue BIRD73.1 with the discussed corrections and
changes.

IBISCHK3 BUG TRACKING STATUS
Bob Ross reported that Atul Agarwal has started work on fixing BUGs 48 - 56.
Bob has provided more information on BUG54.  The expectation is that
ibischk3 Version 3.2.8 will be available by the end of September 2001.

BUG59 - Crash with Decimal Points for [Package] Subparameters
Per the discussion at the last meeting, Bob Ross reported that John Angulo
validated that the parser did crash under Windows 2000.

Bob proposed that we upgrade the classification from ANNOYING, LOW, OPEN to
MODERATE, LOW, OPEN.

We still may need Innoveda to help identify the problem and provide a
solution based on several Windows specific issues.  Assuming that Atul
does not have access to a Windows 2000 system, John Angulo took the AR to
contact Matt Flora to see if he can help identify the fix.

BUG60 - Incorrect Series Function Table Order Dependency
Bob Ross introduced BUG60.  An incorrect warning message is issued for
[Series Switch Groups] entries that are not in the same sequence as the
function_table_group entries.  For example, a line

  On 1 2 3 4 /

works, but 

  On 2 1 3 4 /

causes incorrect Warning messages related to undefined switch functions.
The IBIS Version 3.2 specification does not require that the entries follow
the same sequence.

Bob proposed classifying this as MODERATE, MEDIUM, OPEN since the parser
gives an incorrect Warning on a legal IBIS model.  The short term work
around is to carefully order the [Series Switch Groups] entries.  After
some discussion the group agreed with this classification.

NEXT MEETING:
The next meeting will be the IBIS Summit Meeting on Thursday, September 13,
2001 from 8:30 AM to 5:00 PM.  No teleconference connection is planned.

============================================================================
                                      NOTES

IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
            [email-masked]
            Senior Hardware Engineer, Intel Corporation
            M/S JF4-215
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

VICE CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            [email-masked]
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

SECRETARY:  Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN:  Roy Leventhal (837) 797-2152, Fax: (847) 222-2799
            [email-masked]
            Senior Engineer, CommWorks Corp. (a wholly owned 3Com
            subsidiary)
            1800 W. Central Rd.
            Mt. Prospect, IL 60056-2293

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            [email-masked]
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
            [email-masked]
            Development Engineer, Innoveda
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  [email-masked]
      In the body, for the IBIS Open Forum Reflector:
      subscribe ibis <your e-mail address>

      In the body, for the IBIS Users' Group Reflector:
      subscribe ibis-users <your e-mail address>

      Help and other commands:
      help

  [email-masked]
      To join, change, or drop from either the IBIS Open Forum Reflector
      ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
      or both.  State your request.

  [email-masked]
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  [email-masked]
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  [email-masked]
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  [email-masked]
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported
      bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, and
      /pub/ibis/bugs/s2iplt/bugsplt.txt respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results.  You can get on via FTP anonymous.

============================================================================

------------------------------

Date: Thu, 06 Sep 2001 18:13:40 +0300
From: yoked erlich <[email-masked]>
Subject: Ibis_model

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Hi ,

I've got the next warning about [falling Waveform] simulation,

WARNING - Model ipad6wd: The [Falling Waveform]
      with [R_fixture]=50 Ohms and [V_fixture_min]=3V
      has MIN column DC endpoints of  1.29V and  3.00v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 1.27V and  2.94V),
      a difference of  1.64% and  2.18%, respectively.

I understood the first part of the warning , but I can't figure out how
does the checker find the second voltage range
(as it appear in the warning the range is yields from the I/V tables and
I couldn't find any sign to this voltage in I/V tables)

- --

With regards,

Yoked.

_____________________________________
E-mail:           [email-masked]
Tel: 972-9-9522482 Fax: 972-9-9522888
WIRELESS     CIRCUIT  - IO      GROUP
MOTOROLA     SEMICONDUCTOR     ISRAEL

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
<font color="#330000">Hi ,</font><font color="#330000"></font>
<p><font color="#330000">I've got the next warning about [falling Waveform]
simulation,</font><font color="#3333FF"></font>
<p><font color="#3333FF">WARNING - Model ipad6wd: The [Falling Waveform]</font>
<br><font color="#3333FF">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; with [R_fixture]=50
Ohms and [V_fixture_min]=3V</font>
<br><font color="#3333FF">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; has MIN column
DC endpoints of&nbsp; 1.29V and&nbsp; 3.00v, but</font>
<br><font color="#3333FF">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; an equivalent
load applied to the model's I-V tables yields</font>
<br><font color="#3333FF">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; different voltages
( 1.27V and&nbsp; 2.94V),</font>
<br><font color="#3333FF">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; a difference of&nbsp;
1.64% and&nbsp; 2.18%, respectively.</font><font color="#3333FF"></font>
<p><font color="#333300">I&nbsp;understood the first part of the warning
, but I can't figure out how does the checker find the second voltage range</font>
<br><font color="#333300">(as it appear in the warning the range is yields
from the I/V tables and I couldn't find any sign to this voltage in I/V
tables)</font>
<pre>--&nbsp;

With regards,

Yoked.

_____________________________________
E-mail:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; [email-masked]
Tel: 972-9-9522482 Fax: 972-9-9522888
WIRELESS&nbsp;&nbsp;&nbsp;&nbsp; CIRCUIT&nbsp; - IO&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; GROUP&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
MOTOROLA&nbsp;&nbsp;&nbsp;&nbsp; SEMICONDUCTOR&nbsp;&nbsp;&nbsp;&nbsp; ISRAEL</pre>
&nbsp;</html>

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------------------------------

Date: Thu, 6 Sep 2001 13:47:13 -0400 
From: "Ross, Bob" <[email-masked]>
Subject: IBIS SUMMIT MEETING AGENDA 9/13/01

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C136FC.49BF0B00
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To IBIS Participants:

Here is the Agenda for the IBIS Summit Meeting.  We do expect
interactive discussions and some possible Ad Hoc presentations
to fill out the day.

If you plan to come, but have not notified anyone, please let
Kathy Breda know to help us plan the refreshment and free lunch
participation.  E-mail is [email-masked].

We am looking forward to seeing you in Worcester and having a
productive meeting.

Bob Ross
Mentor Graphics

************************************************************

I B I S   S U M M I T   M E E T I N G   A G E N D A

Time/Date:      8:30 AM - 5:00 PM, Thursday, September 13, 2001

Location:       The Crowne Plaza Hotel
                10 Lincoln Square
                Worcester, Massachusetts
                Tel:  (508) 791-1600
                Fax:  (508) 791-1796

Content:        IBIS Presentations and Discussions

Purpose:        Solicit and Exchange IBIS Model Related Information and
                Ideas.

Sponsors:       Mentor Graphics
                North East Systems Associates, Inc.
                IBIS Open Forum
                IBIS Users Group

PCB Conference: September 10-14, 2001
East            Worcester's Centrum Centre
                Worcester, Massachusetts
                See http://www.pcbeast.com/ for more information.

************************************************************

IBIS SUMMIT AGENDA

8:30 AM   MORNING REFRESHMENTS

9:00 AM   Introductions and Business
          Stephen Peters, Intel

9:15 AM   Keynote Remarks
          Ed Sayre, North East Systems Associates (NESA)

9:30 AM   From Model Creator to Model User
          Bob Haller, Cereva Networks

10:00 AM  A Proposal for s2ibis3
          Paul Franzon, North Carolina State University 

10:30 AM  BREAK AND REFRESHMENTS

10:45 AM  Modeling the Radiated Emission of Micro-controllers
          Etienne Sicard, National Institute of Applied Science (INSA)

11:30 AM  Power/Ground Simulation with IBIS Models and Pin Mapping
          Issues
          Raj Raghuram, Sigrity, Inc.  

12:00 PM  LUNCH (Free to Attendees)

1:00 PM   Progress and Update in the Connector Specification
          Stephen Peters, Intel Corporation

1:30 PM   Progress and Issues in IBIS-X
          Stephen Peters, Intel Corporation

2:00 PM   IBIS-X Primitives and Example
          Lynne Green, Cadence Design Systems

2:30 PM   BREAK AND REFRESHMENTS

2:45 PM   Unscheduled Ad Hoc Topics

3:15 PM   Roundtable - Other Topics
          Stephen Peters, Intel, Ed Sayre, NESA

5:00 PM   FINAL BUSINESS AND ADJOURN

************************************************************

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<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2653.12">
<TITLE>IBIS SUMMIT MEETING AGENDA 9/13/01</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>To IBIS Participants:</FONT>
</P>

<P><FONT SIZE=3D2>Here is the Agenda for the IBIS Summit Meeting.&nbsp; =
We do expect</FONT>
<BR><FONT SIZE=3D2>interactive discussions and some possible Ad Hoc =
presentations</FONT>
<BR><FONT SIZE=3D2>to fill out the day.</FONT>
</P>

<P><FONT SIZE=3D2>If you plan to come, but have not notified anyone, =
please let</FONT>
<BR><FONT SIZE=3D2>Kathy Breda know to help us plan the refreshment and =
free lunch</FONT>
<BR><FONT SIZE=3D2>participation.&nbsp; E-mail is =
[email-masked].</FONT>
</P>

<P><FONT SIZE=3D2>We am looking forward to seeing you in Worcester and =
having a</FONT>
<BR><FONT SIZE=3D2>productive meeting.</FONT>
</P>

<P><FONT SIZE=3D2>Bob Ross</FONT>
<BR><FONT SIZE=3D2>Mentor Graphics</FONT>
</P>

<P><FONT =
SIZE=3D2>************************************************************</F=
ONT>
</P>

<P><FONT SIZE=3D2>I B I S&nbsp;&nbsp; S U M M I T&nbsp;&nbsp; M E E T I =
N G&nbsp;&nbsp; A G E N D A</FONT>
</P>

<P><FONT SIZE=3D2>Time/Date:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 8:30 AM - =
5:00 PM, Thursday, September 13, 2001</FONT>
</P>

<P><FONT SIZE=3D2>Location:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; The =
Crowne Plaza Hotel</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; 10 Lincoln Square</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; Worcester, Massachusetts</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; Tel:&nbsp; (508) 791-1600</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; Fax:&nbsp; (508) 791-1796</FONT>
</P>

<P><FONT SIZE=3D2>Content:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
IBIS Presentations and Discussions</FONT>
</P>

<P><FONT SIZE=3D2>Purpose:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Solicit and Exchange IBIS Model Related Information and</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; Ideas.</FONT>
</P>

<P><FONT SIZE=3D2>Sponsors:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Mentor =
Graphics</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; North East Systems Associates, Inc.</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; IBIS Open Forum</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; IBIS Users Group</FONT>
</P>

<P><FONT SIZE=3D2>PCB Conference: September 10-14, 2001</FONT>
<BR><FONT =
SIZE=3D2>East&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp; Worcester's Centrum Centre</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; Worcester, Massachusetts</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; See <A HREF=3D"http://www.pcbeast.com/" =
TARGET=3D"_blank">http://www.pcbeast.com/</A> for more =
information.</FONT>
</P>

<P><FONT =
SIZE=3D2>************************************************************</F=
ONT>
</P>

<P><FONT SIZE=3D2>IBIS SUMMIT AGENDA</FONT>
</P>

<P><FONT SIZE=3D2>8:30 AM&nbsp;&nbsp; MORNING REFRESHMENTS</FONT>
</P>

<P><FONT SIZE=3D2>9:00 AM&nbsp;&nbsp; Introductions and Business</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Stephen =
Peters, Intel</FONT>
</P>

<P><FONT SIZE=3D2>9:15 AM&nbsp;&nbsp; Keynote Remarks</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Ed =
Sayre, North East Systems Associates (NESA)</FONT>
</P>

<P><FONT SIZE=3D2>9:30 AM&nbsp;&nbsp; From Model Creator to Model =
User</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Bob =
Haller, Cereva Networks</FONT>
</P>

<P><FONT SIZE=3D2>10:00 AM&nbsp; A Proposal for s2ibis3</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Paul =
Franzon, North Carolina State University </FONT>
</P>

<P><FONT SIZE=3D2>10:30 AM&nbsp; BREAK AND REFRESHMENTS</FONT>
</P>

<P><FONT SIZE=3D2>10:45 AM&nbsp; Modeling the Radiated Emission of =
Micro-controllers</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Etienne =
Sicard, National Institute of Applied Science (INSA)</FONT>
</P>

<P><FONT SIZE=3D2>11:30 AM&nbsp; Power/Ground Simulation with IBIS =
Models and Pin Mapping</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Issues</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Raj =
Raghuram, Sigrity, Inc.&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>12:00 PM&nbsp; LUNCH (Free to Attendees)</FONT>
</P>

<P><FONT SIZE=3D2>1:00 PM&nbsp;&nbsp; Progress and Update in the =
Connector Specification</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Stephen =
Peters, Intel Corporation</FONT>
</P>

<P><FONT SIZE=3D2>1:30 PM&nbsp;&nbsp; Progress and Issues in =
IBIS-X</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Stephen =
Peters, Intel Corporation</FONT>
</P>

<P><FONT SIZE=3D2>2:00 PM&nbsp;&nbsp; IBIS-X Primitives and =
Example</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Lynne =
Green, Cadence Design Systems</FONT>
</P>

<P><FONT SIZE=3D2>2:30 PM&nbsp;&nbsp; BREAK AND REFRESHMENTS</FONT>
</P>

<P><FONT SIZE=3D2>2:45 PM&nbsp;&nbsp; Unscheduled Ad Hoc Topics</FONT>
</P>

<P><FONT SIZE=3D2>3:15 PM&nbsp;&nbsp; Roundtable - Other Topics</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Stephen =
Peters, Intel, Ed Sayre, NESA</FONT>
</P>

<P><FONT SIZE=3D2>5:00 PM&nbsp;&nbsp; FINAL BUSINESS AND ADJOURN</FONT>
</P>

<P><FONT =
SIZE=3D2>************************************************************</F=
ONT>
</P>

</BODY>
</HTML>
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------------------------------

Date: Tue, 11 Sep 2001 15:24:53 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: Changes to IBIS East Summit

Greetings:

  Due to the disruption in air travel, many of the officers and presenters
will not be able attend Thursday's IBIS East summit in person.
Nevertheless, the IBIS Summit and Users Group meeting WILL be held, albeit
in a scaled down fashion.  Ed Sayer (NESA) has agreed to host a Users Group
meeting with the attendees already at PCB East.  As for the IBIS Summit
itself, Intel has arranged for a teleconference connection to the Users
Group meeting.  The teleconference will be from 6:00am - 9:00am Pacific time
(9:00am - 12:00pm Eastern).  We will conduct whatever IBIS business required
and then work thru the presentations, especially Paul Fanzon's S2IBIS3
presentation and Mr. Sicard's EMI work with IBIS.  We can extend the
teleconference if folks desire and there are topics to discuss.  The dial in
number, bridge number and passcode are as follows:

Dial in number: 1-916-356-2663
Bridge number:  Bridge 3
Passcode:       5127881

Presenters, if you have not already done so please mail your presentation
(electronic format) to [email-masked] for placement on the IBIS web
site.

Thanks everyone for you patience and understanding.

  Regards,
  Stephen Peters
  Intel Corp.
  Chair, EIA/IBIS Open Forum

------------------------------

Date: 
From: 
Subject: [none]

  --------------------------------------------------------------------

Subject: IBIS Open Forum now under Majordomo
From: John Angulo ([email-masked])
Date: Mon Aug 13 2001 - 17:00:01 PDT

   * Next message: Guy de Burgh: "IBIS Open Forum Minutes (8/10/01)"
   * Previous message: Ross, Bob: "IBIS - I/O Buffer Modeling Cookbook"
   * Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

  --------------------------------------------------------------------

Hello,

All members of the IBIS Open Forum will soon receive welcome messages from
the new Majordomo list administration software. There is no change in your
list membership status - this is just an automatic message resulting from
the change in the underlying mail administration.

As the Chair of the EIA/IBIS Open Forum, Stephen Peters, said last week, we

have been having some initial trouble with Majordomo. Unfortunately,
messages posted to [email-masked] since July 24 have not been sent to the
Open
Forum members. These messages have not been lost, but have been archived
at:

http://www.eda.org/ibis/hm/

You can visit this hypermail archive to view all posted messages.

Note that the IBIS Users Group Reflector is still running smoothly under
the
old mail system, and that most of the Open Forum messages are cross posted
there.

New postings to [email-masked] should now be forwarded to all Open Forum
members. For the time being, however, we ask that you cross post all
messages to [email-masked] to [email-masked].

There are several other issues we are working to resolve. Specifically, you

will notice that the title provided by Majordomo in your welcome email and
on the hypermail archive should be changed from "IBIS - EIA IBIS
Standard Activity" to "EIA/IBIS Standards Committee Activity". Also, the
text drawings in messages on the hypermail archive are corrupted by
font/whitespace conversions. Please send any questions about this message
or suggestions for mailing list improvements to:

[email-masked]

Thanks for your patience during this transition,
John Angulo
IBIS Open Forum Postmaster

  --------------------------------------------------------------------

   * Next message: Guy de Burgh: "IBIS Open Forum Minutes (8/10/01)"
   * Previous message: Ross, Bob: "IBIS - I/O Buffer Modeling Cookbook"
   * Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

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------------------------------

End of ibis V1 #1
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