Subject: IBIS BIRD72.3 - ...PMOS//NMOS Series FET Models

From: Bob Ross <[email-masked]>
Date: Fri, 26 Oct 2001 15:00:39 -0700

To IBIS Committee:

BIRD72.3 by Tom Dagostino with a minor editorial correction was approved at
the October 26, 2001 IBIS Meeting and is issued below.

The new correction in a figure is noted by |**** lines.

BIRD72.2 is scheduled for a vote at the October 26, 2001 meeting.

Bob Ross
Mentor Graphics

******************************************************************************
******************************************************************************

BIRD ID#:        72.3
ISSUE TITLE:     Accommodating PMOS and NMOS//PMOS Series FET Models
REQUESTER:       Tom Dagostino, Mentor Graphics
DATE SUBMITTED:  7-26-01, 10-3-01, 10-8-01, 10-26-01
DATE ACCEPTED BY IBIS OPEN FORUM: 10-26-01

******************************************************************************
******************************************************************************

STATEMENT OF THE ISSUE:

The IBIS FET Bus Switch model assumes a series NMOS FET which has its gate
tied to Vdd.  We have come across two other topologies for the FET switches,
specifically: 

1. What appears to be a PMOS device with it's gate tied to ground 
2. Parallel NMOS and PMOS devices with gates respectively tied to Vdd and
   ground.

The IBIS Golden Parser produces warnings and errors with models that describe
this behavior.

******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

These models cause issues with the IBIS Golden Parser and, depending on
assumptions in the simulator's implementations that support the bus switch,
analysis issues.  

For the single PMOS case:

The parser is set up to see increasing current as Vgs increase where Vgs is
defined as Vcc - Vsource.  Given this definition for Vgs the current Id will
decrease as 'Vgs' increases for the PMOS device with its gate to ground.  The
parser gives an error of decreasing current as 'Vgs' increases.

Simulators may make the assumption the FET is a NMOS device and may not handle
the characteristics properly if the model gets parsed in.

For the dual PMOS/NMOS case:

In the case of the dual PMOS/NMOS topology the currents through the parallel
FET's will sum and produce an Id curve that: 

-- starts with significant current at 'Vgs' = 0 (current is flowing through
the PMOS device)

-- decreases by 10 to 90% at about 40% of 'Vgs' range where both the PMOS and
NMOS devices are both on  

-- increases to a larger value at 'Vgs' = Vdd than at 'Vgs" = 0.  This is
where the NMOS device is fully on

This characteristic has been observed in several devices.  This will cause a
non-monotonic warning from the parser.

It is not known how all simulators will handle this non-monotonic behavior.
 
In general the simulators should be able to handle these characteristics.
The IV curves define the device's characteristics and the simulator should
just work with that definition.

******************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

The following changes are proposed:

The definition of Voltage in the IV table changes.  Vgs has been Vcc - Vsource
assuming the gate was tied to Vcc.  IBIS should now assume the voltage in the
IV table is really Vcc minus the FET's source voltage (Voltage = Vcc -
Vsource).  This makes old models compatible and no change in the model format
is required.

Decreasing current vs. Voltage are allowed.

Non-monotonic currents in the table are expected in the parallel case but
warnings can still be issued.  It may be useful to have the modeler note the
type of switch in the model so the user can better understand any
non-monotonic issues.  

******************************************************************************

Changes and additions to the IBIS Specification are shown by the |* lines
More changes are documented by |** and |*** lines.

The figure is corrected as indicated by  |**** lines.

|=============================================================================
|     Keyword:  [Series MOSFET]
|    Required:  Yes, for series MOSFET switches
| Description:  The data points under this keyword define the I-V tables for
|               voltages measured at Pin 2 for a given Vds setting.  Currents 
|               are considered positive if they flow into Pin 1.  Pins 1 and 
|               2 are listed under the [Series Pin Mapping] keyword under
|               [Series Pin Mapping] and pin_2 columns, respectively.
|  Sub-Params:  Vds
| Usage Rules:  The first column contains the voltage value, and the three
|               remaining columns hold the typical, minimum, and maximum
|               current values.  The four entries, Voltage, I(typ), I(min),
|               and I(max) must be placed on a single line and must be
|               separated by at least one white space.
|
|               All four columns are required under these keywords.  However,
|               data is only required in the typical column.  If minimum 
|               and/or maximum current values are not available, the reserved
|               word "NA" must be used.  "NA" can be used for currents in the
|               typical column, but numeric values MUST be specified for the
|               first and last voltage points on any I-V table.  Each I-V 
|               table must have at least 2, but not more than 100, voltage
|               points.
|
| Other Notes:  There is no monotonicity requirement. However the model
|               supplier should realize that it may not be possible to derive
|               a behavioral model from non-monotonic data.
|
|** Delete this Diagram

|               The model is:
|
|                                Table Current
|                                   ------->
|                              +     Vds     -
|                             Pin 1           Pin 2
|                               <---|     |--->  +
|                               d   |_____| - s
|                                    --+-- Vgs   Vs
|                                      | g  +
|                                                -
|                      Vg = [Voltage Range] = Vcc
|                      Vgs = Table Voltage = Vtable = Vcc - Vs
|                      Ids = Table Current for a given Vcc and Vds
|

|** Replace with this Diagram and Text:

|*
|*                                Table Current
|*                                   ------->  Ids
|*                               +     Vds     -
|*
|*                                     Vcc
|*                                      | g
|****                                 __|__
|****                                 -----  NMOS
|*                             Pin 1 |     |    Pin 2
|****                            <---+     +--->  +  Voltage = Vcc - Vs
|****                            d   |_____|   s  
|**                             PMOS  --+--       Vs
|*                                      | g  
|**                                    GND        -
|*
|**            Either of the FET's could be removed (or have zero current
|**            contribution.  Thus this model covers all four conditions, off,
|**            single NMOS, single PMOS and parallel NMOS/PMOS.
|*         
|*                      Voltage = Table Voltage = Vtable = Vcc - Vs
|*                      Ids = Table Current for a given Vcc and Vds
|
|** End of Addition

|** Delete these Sentences:
|**
|              Internal logic that is generally referenced to the power rail
|              is used to set the MOSFET switch to its 'On' state.  Thus the
|              [Voltage Range] settings provide the assumed gate voltages.
|              If the [POWER Clamp Reference] exists, it overrides the
|              [Voltage Range] value.  The table entries are actually the Vgs
|              values referenced to the power rail.  The polarity conventions
|

|** Add these Sentences:

|*              Internal Logic that is generally referenced to the power rail
|*              is used to set the NMOS MOSFET switch to its 'ON' state.
|*              Internal logic likewise referenced to ground is used to set the 
|*              PMOS device to its 'ON' state if the PMOS device is present.
|*              Thus the [Voltage Range] settings provide the assumed 
|*              gate voltages.  If the [POWER Clamp Reference] exists, it 
|*              overrides the [Voltage Range] value.  The table entries are
|*              actually Vgs of the NMOS device and Vcc - Vgs of the PMOS
!*              device, if present.  The polarity conventions

|** End of Addition

|               are identical with those used for other tables that are
|               referenced to power rails.  Thus the voltage column can be
|               viewed as a table defining the source voltages Vs according to
|***            the convention: Vtable = Vcc - Vs.  This convention remains
|***            even without the NMOS device.
|
|               If the switch is used in an application such as interfacing
|               between 3.3 V and 5.0 V logic, the Vcc may be biased at a 
|               voltage (such as 4.3 V) that is different from a power rail
|               voltage (such as 5.0 V) used to create the model.  Just
|               readjust the [Voltage Range] entries (or [POWER Clamp
|               Reference] entries).
|
|               One fundamental assumption in the MOSFET switch model is that
|               it operates in a symmetrical manner.  The tables and
|               expressions are given assuming that Vd >= Vs.  If Vd < Vs,
|               then apply the same relationships under the assumption that
|               the source and drain nodes are interchanged.  A consequence of
|               this assumption is that the Vds subparameter is constrained to
|               values Vds > 0.  It is assumed that with Vds = 0 the currents
|               will be 0 mA.  A further consequence of this assumption that
|               would be embedded in the analysis process is that the voltage
|               table is based on the side of the model with the lowest
|               voltage (and that side is defined as the source).  Thus the
|               analysis must allow current to flow in both directions, as
|               would occur due to reflections when the switch is connected in
|               series with an unterminated transmission line.
|
|               The model data is used to create an On state relationship
|               between the actual drain to source current, ids, and the
|               actual drain to source voltage, vds:
|
|                                    ids = f(vds).
|
|               This functional relationship depends on the actual source
|               voltage Vs and can be expressed in terms of the corresponding
|               table currents associated with Vs (and expressed as a function
|***            of Vtable).
|
|               If only one [Series MOSFET] table is supplied (as a first
|               order approximation), the functional relationship is assumed
|               to be linearly related to the table drain to source current,
|               Ids, for the given Vds subparameter value and located at the
|***            existing gate to source voltage value Vtable.  This table
|***            current is denoted as Ids(Vtable, Vds).  The functional
|***            relationship  becomes:
|

|** Delete this Equation
|                           ids = Ids(Vgs, Vds) * vds / Vds.  
|*

|**** Delete this Equation
|** Add This Equation:

|**                      ids = Idsn(Vtable, Vds) * vds/Vds +
|**                            Idsp(Vcc - Vtable, Vds) * vds/Vds
|

|*** Add This Equation:
|***                       ids = Ids(Vtable, Vds) * vds/Vds.

|** End of Addition

|               More than one [Series MOSFET] table is permitted, but it is
|               simulator dependent how the data will be used.  Each
|               successive [Series MOSFET] table must have a different
|               subparameter value for Vds.  The number of tables must not 
|               exceed 100.
|
|               C_comp values are ignored for [Series MOSFET] models.
|-----------------------------------------------------------------------------
|** An NMOS Example
|**
[On]
[Series MOSFET]
Vds = 1.0  
|  Voltage   I(typ)    I(min)    I(max)
    5.0V    257.9m     153.3m    399.5m    | Defines the Ids current as a
    4.0V    203.0m     119.4m    317.3m |*** function of Vtable, for Vds = 1.0
    3.0V    129.8m      74.7m    205.6m 
    2.0V     31.2m      16.6m     51.0m
    1.0V     52.7p      46.7p     56.7p
    0.0V      0.0p       0.0p      0.0p
|

|** A PMOS/NMOS Example
|**
[On]
[Series MOSFET]
Vds = 0.5
|  Voltage   I(typ)    I(min)     I(max)
0.0 48.6ma NA NA
0.1 47.7ma NA NA
0.2 46.5ma NA NA
0.3 46.1ma NA NA
0.4 45.3ma NA NA
0.5 44.4ma NA NA
0.6 42.9ma NA NA
0.7 42.3ma NA NA
0.8 41.2ma NA NA
0.9 39.7ma NA NA
1.0 38.6ma NA NA
1.1 38.1ma NA NA
1.2 38.6ma NA NA
1.3 40.7ma NA NA
1.4 45.0ma NA NA
1.5 49.2ma NA NA
1.6 52.3ma NA NA
1.7 55.1ma NA NA
1.8 57.7ma NA NA
1.9 58.8ma NA NA
2.0 58.9ma NA NA
2.1 59.2ma NA NA
2.2 59.3ma NA NA
2.3 59.4ma NA NA
2.4 59.8ma NA NA
2.5 60.1ma NA NA
2.6 61.8ma NA NA
2.7 62.3ma NA NA
2.8 63.4ma NA NA
2.9 64.4ma NA NA
3.0 65.3ma NA NA
3.1 66.0ma NA NA
3.2 66.8ma NA NA
3.3 68.2ma NA NA  
|
|=============================================================================

******************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

These models cause issues with the IBIS Golden Parser and, depending on
assumptions in the simulator's implementations that support the bus switch,
analysis issues.  

For the single PMOS case:

The parser is set up to see increasing current as Vgs increase where Vgs is
defined as Vcc - Vsource.  Given this definition for Vgs the current Id will
decrease as 'Vgs' increases for the PMOS device with its gate to ground.  The
parser gives an error of decreasing current as 'Vgs' increases.

Simulators may make the assumption the FET is a NMOS device and may not handle
the characteristics properly if the model gets parsed in.

For the dual PMOS/NMOS case:

In the case of the dual PMOS/NMOS topology the currents through the parallel
FET's will sum and produce an Id curve that: 

-- starts with significant current at 'Vgs' = 0 (current is flowing through
the PMOS device)

-- decreases by 10 to 90% at about 40% of 'Vgs' range where both the PMOS and
NMOS devices are both on  

-- increases to a larger value at 'Vgs' = Vdd than at 'Vgs" = 0.  This is
where the NMOS device is fully on

This characteristic has been observed in several devices.  This will cause a
non-monotonic warning from the parser.

It is not known how all simulators will handle this non-monotonic behavior.
 
In general the simulators should be able to handle these characteristics.
The IV curves define the device's characteristics and the simulator should
just work with that definition.

Changes and additions are noted by |* lines.

BIRD72.1 has some editorial revisions including moving this section from the
beginning to this location.  A new example is added showing PMOS//NMOS
data.  Changes are noted by |** lines

BIRD72.2 has more editorial revision and a correction to an equation which
used Idsn and Idsp.  It turns out that the functional scaling relationship is
retained in terms of the over Ids parameter.  The need to decompose to Idsn
and Idsp only introduced some sign notation confusion and table reference
confusion.  The actual psuedo "gate" is the NMOS gate, even if the NMOS
device does not exist.  So the Vtable could still be considered as only the
NMOS as in IBIS Version 3.2.

New changes are noted by |*** lines.

BIRD72.3 has just one correction to a figure noted by |**** lines.

******************************************************************************

ANY OTHER BACKGROUND INFORMATION:

An Ad Hoc presentation on this topic was initially presented at the IBIS
Summit Meeting on June 21, 2001.

*****************************************************************************