Subject: More on BIRD #???

From: Bob Ward <[email-masked]>
Date: Thu, 2 Dec 1993 10:47:35 -0600

Just One More Thing (tm)  [Promises, promises!]

So I just sent my note about adding weight to the requirement about using
multiple power and ground pin mappings, and Eric Bracken's letter showed up
that indicates I should have elaborated further on our bussing structure.  In
at least one case, we have a chip that will be particularly nasty for things
like simultaneous switching studies, even though that is one thing that ibis
models will be in demand for.

The structure in question is this:

             pwr/gnd                   pwr/gnd
                p                         p     -----------
                i                         i          |
                n                         n      leadframe
                |                         |          |
                +-+-------+------+------+-+     -----------
                  |       |      |      |      bond wire/pad
                  |       |      |      |
                +-+-+   +-+-+  +-+-+  +-+-+     -----------
                |   |   |   |  |   |  |   |          |
                d   d   d   d  d   d  d   d          |
                r   r   r   r  r   r  r   r          |
                i   i   i   i  i   i  i   i       on chip
                v   v   v   v  v   v  v   v          |
                e   e   e   e  e   e  e   e          |
                r   r   r   r  r   r  r   r          |
                |   |   |   |  |   |  |   |     -----------
                |   |   |   |  |   |  |   |      leadframe

The leadframe busses at least two, sometimes four, power or ground pins
together.  This is tapped at several points to provide connections to the
chip, where pairs of drivers are bussed together with on chip metalizing, on
both power and ground sides.  Now it seems to me that if we are trying to
determine this from external measurements made at the pins, we could if the
right combinations of simultaneous switchings were induced while the output
is monitored on the pin of interest.  But without some knowledge of the
circuit to start from, the number of measurements is potentially huge, and
the data potentially confusing.

I guess I toss this out to the group by way of saying "Help!", if anyone has
thoughts on how to handle this, I would like to hear them.  I admit to being
more than a little at a loss how to measure this in general and then also how
to specify it in ibis-isms once measured.  In specific cases it can be
asserted, and I would accept it, that it doesn't matter anyway.  That may the
situation in more cases than I think, and if that is so I am most happy to not
worry about it. But at the moment I am worried about it.  Discussion?

---

From: [email-masked] (Randy Harr)
Date: Thu, 2 Dec 93 15:23:11 PST

For whatever it is worth:

We studied this issue in deciding what to do with the DIE spec work.  See the
files:

	pub/die/wrkshop2/electric.{mif,ps}    (white paper on topic)
	pub/die/wrkshop2/trans_te.{mif,ps}    (viewfoils on topic)

on vhdl.org (use same email request to [email-masked], ftp, etc. as for ibis).

We discovered and analyzed the various forms (even more detailed and
difficult than Bob Ward reports) but discovered most of the power / ground
bounce analysis tools could not handle the complexity.  We decided to
simplify to what Kumar of Cadence (or Eric's extension) is proposing --
one power and one ground pin specification per signal pad.  See the
DIE_PADS_SUPPLY_GROUPING (page 75 of the DIE Format Reference Manual ver 0.9;
in file pub/die/die0-9/die0-9.{rtf,ps} or on floppy given at Summit) for
our method of specification.  By the way, it is a Level 1 setting also!

randy harr
[email-masked]