Subject: Re: Spring VIUF EIA567A tutorial

From: [email-masked] (Larry Saunders)
Date: Tue, 29 Nov 1994 16:35:37 -0800

>On a different note, this may be the time to start considering the marriage
>of 567A and the DIET work.  The intent from the beginning (and a plan of Ed
>Evans) was to generate 567A timing shells from DIET files.  See the
>document on-line in the directory
>gopher://gopher.vhdl.org:70/pub/die/diet0-9/.  Also, the next workshop is
>on the 15-16 Dec in the Bay Area.

Two thoughts:

The current DIET Format spec says nothing about the kind, type, number or
required coverage of the timing specifications that should be included within 
a DIET Format datastream. It's totally left up to the creator to decide what 
to include. Since the EIA 567A spec has a few things to say about simulation 
model content, we should consider somehow linking the two specs so that Ed 
(or anyone else) could write a timing shell generator program secure in the 
knowledge that all the timing information necessary to create a valid and 
complete, EIA 567A compliant simulation model will be right there in the 
DIET datastream, exactly where it should be. No need for last minute chasing 
around looking for timing numbers that somebody forgot to include.     

The DIET Format spec includes a very well researched, widely accepted 
definition of how the various timing specifications (setup, hold, etc.) work. 
Perhaps the EIA should develop some VHDL and/or Verilog models of the DIET 
timing specifications that mirror the standalone nature of the DIET definitions
and somehow include them in the 567A Standard. As I view it the models would
have to be either VHDL concurrent procedure calls or Verilog tasks to 
work properly. I know there are 57 different ways to write these programs
but I am envisioning an implementation where the timing shell generator simply 
needs to create a VHDL/Verilog program call with parameters matching the DIET 
timing_specification settings.

Larry Saunders
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