Subject: BIRD 6.x (regarding tskew)

From: Kellee Crisafulli <[email-masked]>
Date: 02 Feb 94 01:39:49 EST

From: Kellee Crisafulli, HyperLynx
To:   IBISians and Stephen Peters,Intel

Re: Stephen Peters comments on tskew in Bird 6.x

  I believe that tskew for clock buffers is one of those grey
areas.  It is most probably an issue for digital simulation like any
other in-pin to out-pin delay term.  If this is the case than I
believe we should ignore pin-pin skew at least for version 2.0 IBIS.

  On the other hand I believe some people could make a case that for
optimal signal integrity analysis we may wish to analyze multiple clock
nets simutaneously and watch for cross-talk etc.  This would require
knowledge of out-pin to out-pin skew.  However if this is the case than
how about other clock net's relative to each other.  Or what about a
clock buffered by two different clock chips.  This looks like it could
be a venomous snake pit to me!

  I propose we handle tskew for diffential mode outputs and leave
other tskew issues for rev. 3 of the specification or later.

     Best Regards,
     Kellee
     HyperLynx Inc.