Subject: s2ibis (SPICE TO IBIS PROGRAM) Status report

From: [email-masked]
Date: Wed, 09 Feb 94 14:34:23 EST

Dear IBIS Community:

   Hi.  This is a short report to update you on the status of
s2ibis, the SPICE to IBIS conversion program that I am working
on.

   At this point I am able to put out what I think is a
syntactically correct xxxx.ibs file including the header
([IBIS Ver] through [Pin]) and [Model] sections which
include [Pullup], [Pulldown], [GND_clamp], and [POWER_clamp]
tables for TYP conditions.  The hooks are there for doing
the MIN and MAX conditions, and the [Ramp] table. 

   The input to s2ibis consists of a normal [Pin] section
with an extra line after each pin (except NC pins) that helps
s2ibis to set up the simulations followed by a SPICE deck.
The extra line (I will call it the pindata line from now on...)
after each pin in the [Pin] section has the following syntax:

     For input pins:
*  model_type SPICE_NODE polarity vil vih

     For output pins:
*  model_type SPICE_NODE ramp_sim_time input_pin [enable_pin] 

     For POWER pins:
*  model_type SPICE_NODE vpwr_typ [vpwr_min] [vpwr_max]

---------------------------------------------------------------

   s2ibis automatically sets up all the simulation runs, runs
the simulations, extracts the tables from the SPICE output
decks, and writes the xxxx.ibs file.   For Output, I/O, and 3-state 
model types, all the [Model] tables are generated (except Ramp 
at this point).  For Open_drain, all of the above except [Pullup]
and [POWER_clamp] are generated.  For Inputs, only the POWER_clamp
and GND_clamp tables are generated.

   The simulation strategy at this point is simple-minded, and
doesn't always work, but it is easy to modify!:  

   For [Pulldown] tables, the appropriate input is driven to the
vil or vih given on its pindata line depending on whether it is
inverting or not.  If an enable pin is associated with the output
is is also conditioned properly. All other input pins are simply
driven to zero volts to help convergence.  A .DC analysis is used 
with the output under test as the driven pin.

   [Pullup] tables are treated the same as [Pulldown]s,  but 
the associated input is driven the opposite way.

   In [GND_clamp] and [POWER_clamp] simulations all disable-able 
outputs are disabled and all inputs (except the pin under test if
it is an input or I/O) are driven to zero volts.   A .DC analysis
is used with the appropriate range.

   Unfortunately, the simulations I have been running on my simple
test cases have not always converged.  For instance, with a simple
2.3:1 CMOS input buffer with input clamp diodes to both rails, my
GND_clamp simulation on the input pin will not converge (the 
starting input voltage is -5V).  

---------------------------------------------------------------

   I really need some feedback regarding the simulation strategy,
especially with regard to convergence issues.    Are convergence
problems typical among those of you who are generating IBIS
models from SPICE runs or am I doing something wrong?   If they 
are, is it really reasonable to automatically run the simulations?
If they aren't, and  we can address this convergence issue 
effectively, the program could be released fairly soon.

   Also, I have not received any real-world examples from anyone, so
s2ibis can only be tested on my simple test cases.  Is it possible
for someone to send me an example to see if s2ibis gets the 
same results?  Would a non-disclosure agreement help??? 
   
Steve Lipa
[email-masked]
919-515-3947