Subject: IBIS Pending BIRDs 2.0 and 6.1

From: Derrick Duehren <[email-masked]>
Date: Wed, 2 Feb 94 23:54:02 PST

Text item: Text_1

Following are pending BIRDs 2.0 and 6.1.

- Derrick Duehren

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+++ pbird2_0.txt +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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                 Buffer Issue Resolution Document  (BIRD)

BIRD ID#:      2.0
ISSUE TITLE:   Requiring VIH VIL Thresholds for Input Devices
REQUESTOR:     Jon Powell, Quad Desgin

DATE SUBMITTED:                      October 4, 1993
DATE ACCEPTED BY IBIS OPEN FORUM:    {likely to be superceeded}

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STATEMENT OF THE ISSUE:

  The V1.1 IBIS specification does not require the presence of input
  thresholds on input devices. This allows data-generators to omit
  thresholds and still create "IBIS LEGAL" models. Input devices with
  no stated digital logic input thresholds would only be usefull if the
  inputs were totaly analog devices (a condition that is not in the
  main-stream of IBIS targetted devices). Requiring a low and high threshold
  for all input devices is therefor a reasonable requirement that adds
  information without creating undo restrictions.

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STATEMENT OF THE RESOLVED SPECIFICATIONS:

  No new keywords are required.

  The following text to be added to the Other Notes section of the
  [Model] keyword description:

  The sub-parameters Vinl and Vinh are required for Model_types of:
  "Input" and "I/O". Omission of Vinl or Vinh for these devices will
  cause a parser error. Any other device type that contains a Vinl or Vinh
  parameter will cause a parser warning.

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ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

  There are devices that are not Input or Outputs and are not handled by
  our current set of model types. For instance:

  Termination Resistor Packs
  Termination Diode Packs
  Descrete 2 port devices

  I believe that more change is needed in this particular area but that that
  change is large enough that we should discuss it at our meeting as opposed
  to random email messages.

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ANY OTHER BACKGROUND INFORMATION:

  {These documents will be archived, so use this section to carry
  any detail that is not essential to the previous section, but should not be
  lost.}

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+++ pbird6_1.txt +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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                     Buffer Issue Resolution Document  (BIRD)

BIRD ID#:                6.1
ISSUE TITLE:             Differential Pin Specification
REQUESTOR:               Bob Ross, Interconnectix, Inc.
DATE SUBMITTED:                     January 12, 1994
DATE REVISED:                       January 29, 1994
DATE ACCEPTED BY IBIS OPEN FORUM:   {pending}

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STATEMENT OF THE ISSUE:

Several components contain pins which operate in a differential mode with
respect to other pins.  Since this operation in inherent to a component,
the IBIS document should be extended to specify this functionality.

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STATEMENT OF THE RESOLVED SPECIFICATIONS:

An additional optional keyword, [Diff_Pin], is added to the specification.

|==============================================================================
|    Keyword:  [Diff_Pin]
|   Required:  Optional
|Description:  Used to associate differential pins, their peak-to-peak
|              differential voltages and timing skews.
| Sub-Params:  inv_pin, vdiff, tskew_typ, tskew_min, tskew_max
|Usage Rules:  Entries follow these rules: Only differential pin pairs
|              are entered.  The [Diff_pin] column contains a non-inverting
|              pin number and the inv_pin column always contains the
|              corresponding inverting pin number for output and I/O output.
|              The vdiff column contains the specified peak-to-peak voltage
|              between pins if the pins are Input or I/O Model_types.
|              For Output only differential pins, the vdiff entry is 0V.
|Other Notes:  The output pin polarity specification in the table overrides
|              the [Model] Polarity specification such that the pin in the
|              [Diff_pin] column will be Non-Inverting and the pin in the
|              inv_pin column will be Inverting.  This convention allows
|              one [Model] to be used for both pins.
|
|              Column length limits are:
|                      [Diff_Pin]        5 characters max
|                      inv_pin           5 characters max
|                      vdiff             9 characters max
|                      tskew_typ         9 characters max
|                      tskew_min         9 characters max
|                      tskew_max         9 characters max
|
|              Each line must contain either four or six columns.  If "NA" is
|              entered in the vdiff, tskew_typ or tskew_min columns, its
|              entry will be interpreted as 0V or 0ns.  If "NA" appears in
|              the tskew_max column, its value will be interpreted as the
|              tskew_typ value.  When using six columns, the headers
|              tskew_min and tskew_max must be listed.
|-------------------------------------------------------------------------------
[Diff_Pin]  inv_pin  vdiff   tskew_typ tskew_min tskew_max
|
3           4       150mV     1ns       0ns       2ns  | Input or I/O pair
7           8         0V      1ns        NA        NA  | Output* pin pair
9          10         NA       NA        NA        NA  | Output* pin pair
16          15       200mV     1ns    | Input or I/O pin pair
20          19         0V       NA    | Output* pin pair, tskew = 0ns
22          21         NA       NA    | Output*, tskew = 0ns
                                      | * Could be Input or I/O with vdiff = 0V

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ANALYSIS PATH/DATA THAT LED TO SPECIFICATION

Since only a small percentage of components contain differential pins,
[Diff_Pin] is optional.  The component itself may be required to convey the
associations between pins for differential inputs and/or outputs.  Such cases
may occur in practice when pairs of pins are connected using closely-spaced,
coupled nets or twisted-pair cabling.

Pins that provide complimentary outputs should not be associated with
each other when the analysis is normally done using only one pin at a time.
However, there may be cases related to other pending extensions
(package models, power association, etc.) where association of complimentary
pins may be appropriate.

[Diff_pin] should be used for pins designed for differential operation.
Inputs of such components have a differential input sensitivity specification
such as "Vpp" or "VT+" and "VT-" which defines a peak-to-peak voltage between
two input pins.  The vdiff column is introduced for such specification
limits (as a positive value) which would trigger an output transition.  One
application is for timing analysis.

|<-- OUTPUT MEASUREMENT POINT FROM ANOTHER COMPONENT
|
|
|<-- tmax -->|
|            |
|<-- tmin ->||
__________  ||  ____________ __
          \ || /             A0
         __\||/__
            \/    vdiff       DIFFERENTIAL INPUT
         __ /\ __
           /  \
__________/    \____________ A0

For timing purposes, an output is referenced to an equal voltage cross-over
of output pins.  Setting the vdiff entry to 0V is thus chosen when the pins
are for differential outputs only.  Note, the cross-over does NOT mean that
the outputs are at 0V.

The tskew value is the time difference between the mid-point of the two
output transitions.  It is equivalent to the time-delay of one pin relative to
the other pin.  Although an absolute value is specified, either pin can delayed
relative to the other pin.  This specification assumes the outputs are
reasonably identical and the rise and fall transitions are reasonably similar.

Tskew can be shown per National Interface Databook, diagram on pg 1-121:

       3V _______________
         /               \  INPUT TO SAME COMPONENT
 1.5V__ /                 \
       /|                 |\
0V ___/ |                 | \______________
        | tPLH |          |tPHL|

 ___________        __________    _________ __
 ^     ^    \      /          \  /     ^    D0
 |    Vo/2   \    /            \/     Vo/2
Vo     v______\  /__        __|/\|_____v        DIFFERENTIAL OUTPUT
              |\/|            /  \
 |            |/\|           /|  |\
 v____________/  \__________/ |  | \_______ D0
              |  |            |  |
              |  | Tskew      |  | Tskew

Tskew = |tPLH - tPHL|

Conventions similar to those in [Pin] are followed with respect to required
and optional column entries and to column lengths.

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ANY OTHER BACKGROUND INFORMATION:

Introducing a [Tskew] keyword similar to [Package] (used for defaults) was
suggested and could be considered as another method for dealing with skew.

An alternative polarity mechanism for differential outputs could have been
based on the Polarity sub-parameter within the [Model].  This was not done
because Polarity is optional and also because two [Model]s would be required:
one for the "Non-inverting" pin and another for the "Inverting" pin.  In
BIRD6.1, vdiff is used as an absolute difference regardless of polarity for
Input specfication, so "polarity" no longer is applicable for inputs.

However, it still may be reasonable to require two Output or I/O [Model]s
for easier translation into simulator databases.  In this case, the "inv_pin"
name could be changed to "2nd_pin".  Also, with a Polarity sub-parameter,
the possibility exists that the [Models] are in phase with each other.  This
may be useful for double strength buffer options.

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