Subject: General Info

From: "J. C. (Jay) Diepenbrock ((919)-543-8804)" <[email-masked]>
Date: Wed, 16 Feb 94 10:05:56 EST

Hello IBISers,

Being a relative newcomer to this forum, I seem to be lacking understanding
of some basic things.  I'm hoping that there's some document that will
explain them, but I don't see it in the index of 1.0 or 1.1.  Here goes:

1.  What is the circuit topology to be used to extract the DC pin character-
    istics?  If a voltage source that's swept from, say, -5 to +10 V, how
    do the results relate to those when driving a "real" load that has non-
    zero impedance?  I'm a little uncomfortable with the method, but I've
    not seen any specifics about how to do it, so am making assumptions
    (you all know what results from that!).  Is there some general IBIS
    document that addresses this kind of question?

2.  Getting back to a question raised by Lynn Warriner a couple of weeks ago,
    I'd like to ask the signal integrity tool providers how we the prospec-
    tive customers are supposed to choose our tools... claims of "more
    accurate than xyz" are not practical to validate.  I'd feel a lot better
    if there were some standard benchmarks (either net configurations or,
    better still, hardware) by which we could make choices.  I recognize the
    need for tool vendors to differentiate their products, but I'm frankly
    not interested in doing detailed evaluations of several tools before
    starting a project that needs one.  Any thoughts would be welcome.

Thanks for your patience.

Jay Diepenbrock

---

From: [email-masked]
Date: Wed, 16 Feb 94 11:15:50 -0500

Jay,

  With regard to your first question, using a voltage source sweep is
quite adequate for characterizing the "DC" behavior of the gate.

  You're going to get an I-V curve that describes the behavior of
the gate for all voltages "of interest" during the simulation.  With
this curve, you can see how the gate will behave when it's loaded by
any impedance.  For example, suppose your voltage sweep determines
this I-V curve for the pull-down element of an output buffer:

     i ^		*
       |	       *
 100mA -	      *
       |	    *
       |	  *
       |	 *
       |	*
       |       *
       |      *
 0 mA -+*****-------------|----> v
       0V                 5v

  Now suppose that the load is a 50-ohm transmission line initially at
5V, which you wish to pull down to 0V.  The voltage at the driver is
going to be 5V - (50 Ohms)*i (i is the current the driver can sink.)
In other words, if we can only sink 0 mA, the voltage will stay at 5V;
if we can sink a full 100 mA, the voltage will drop to 0V.  The plot
of voltage vs. current for the load is a straight line, called the
"load line".

  You can impose this "load line" on the I-V curve and find the
solution graphically:

     i ^		*
       |	       *                
 100mA o	      *
       |  o         *
       |     o    *
       |        o*  <---- answer is here!
       |	*  o
       |       *      o
       |      *	         o
 0 mA -+*****--------------|---> v
       0V                  5v

The point where the two curves cross gives you the answer because it's
consistent with both of the "constraints."  The CAD tools out there use
numerical methods to find this point of crossing.  So, nonzero impedances
are handled properly.

  With regard to AC behavior, the IV curve alone isn't sufficient.
That's why the IBIS model has the first-order RLC values of the
buffer's pin in addition to IV models.  Enhancements to make the 
models work at still higher frequencies are being discussed in the
forum right now.

--Eric