Subject: RAMP NOTE COMMENT

From: [email-masked] ( Bob Ross)
Date: Thu, 3 Feb 94 18:04:49 PST

Dear IBIS folks:

I enjoyed seeing your responses to the RAMP NOTE.  My purpose for sending
it out originally was for information only.

The first tendency with a ramp rate expressed as dV/dt is to extrapolate
the slope to full voltage swing values - but this is not consistent
with actual device operation.  The second tendency based on examples 
given is to assume the data is expressed as 100% ramp numbers.
For example, dV/dt ramps for Pentium(TM) Processor User's Manual, Vol.2
pg. 8-3 go rail to rail for min and max voltages (dV = 4.5 and 5.5).

The IBIS specification provides clear methodology to derive [Ramp] 
data and what it means.  However, the example is somewhat misleading and
needs to be fixed, expecially for dV/dt_r, since one would not expect
60% of the transition to cover 4.2, 3.5 and 5 volts for VCCs of 5, 
4.5 and 5.5.  So the voltages in the example should be adjusted downward.
Current IBIS data in the Intel directory show lower voltage swings and
could be the basis of a revised example in the Version 2.0 specification.

Version 1.1 example - should be revised

|-----------------------------------------------------------------------
[Ramp]
| variable      typ             min             max
dV/dt_r         4.2/1.8n        3.5/2.5n        5.0/1.1n
dV/dt_f         2.5/1.5n        2.0/2.3n        3.0/0.8n
|=======================================================================

I favor keeping the 20%-80% method for compatibility.  While 10%-90%
is commonly used for validation of specifications, I think it is 
reasonable to use the reduced range for getting parameters for modeling.
The other elements in the model should degrade the response slightly.
Also, some ECL response specifications are based on 20%-80%.  Finally, I
would rather err on the side of being too fast.  The [Ramp] data, as defined,
should provide models which are reasonable and defendable.

Eventually, the real issue is how to get a more accurate model.  Discussions
underway regarding V-I-T (3-D characterization), slew-rate controlled
devices, packaging, and perhaps EMI issues are addressing portions of the
problem.  Full V-T time response data for the measurement conditions
specified (50 Ohm loads) would be one way to accurately present the
response to document its shape.  But, this opens the door for some very
complicated considerations such as:
   (1) Effect of the non-linear DC high state and low state output resistance
       on the response (probably less than expected)
   (2) Effect of the non-linear AC output impedance characteristics on
       the response (probably more that expected when using 50 ohm loads),
       but the only AC impedance parameters modeled are C_comp and the
       package paramaters.
   (3) For some devices, 50 Ohm load is appropriate; but for others, it may
       provide characterizations well out of the normal operating range.
       (On the other hand, some devices work well with 50 Ohm loads, and
       give much different responses with higher resistance loads.)
   (4) Pullup loads to 5V may be appropriate for CMOS logic.  But for one
       TTL device I got significantly different results for dt_f when the 
       load was connected to 5V versus 3.5V and 1.75V.  This may be just
       one case, but the measurement methods may become more of a 
       consideration to provide more accurate models for different 
       technologies.

Given all of the possible variables, I am not convinced that just modifying
the [Ramp] specification in IBIS Version 1.1 will give better models. 
      
Bob Ross,
Interconnectix, Inc.