Subject: high freq effects in i/o models

From: [email-masked] (Ravender Goyal)
Date: Thu, 6 Jan 94 10:29:37 -0800

Sorry, in my last message, it seems that the figures did not come through good. 
Let me make another attempt here.

Ravender
-------------------------------------------------------------------------------
I am starting this discussion to get your inputs on including the high
frequency effects  (4- 5 GHz) in IBIS models. 
As we know the signal integrity analysis accuracy depends as much on
accurately evaluating the electrical characterisitcs (characteristic
impedance, trace velocity, dispersion, to name a few) of interconnects,
as it depends on the accuracy of evaluating or specifying the
terminating impedances- i.e. the i/o models.
For EMI (Electromagnetic Interference) analysis, the frequency of
analysis is upto several GHz, as required by the FCC, European FCC etc.
guidelines. Hence, for EMI analysis upto what ever frequency of
interest, it is critical to have  i/o model that is valid at that
frequency, else results from EMI analysis could be grossly  inaccurate.
In order to include the high frequency effects, it is general
impression (as I have heard in the past) that one may have to give up
the proprietary information about the process. However, just for
accurate impedance presentation, that may not be necessary. To give an
example:
1- Today the i/o model is represented as follows:

                 o Vcc/ Vdd etc.
                 |
                 |
                 |
            _____|_____
           |     B     |
           |     L     |
           |     A     |
           |     C     |
   o-------|     K     |------o output
 input     |           |    |
           |     B     |    |
           |     O     |    |
           |_____X_____|   === pin capacitance
                 |          |   
                 |          |
                 |-----------
                 |
                 o
               Ground

The black box today is an i/v curve which results in a real impedance
only. The  imaginary part of the impedance is contributed by the pin
parasitics only. We all know that the semiconductor devices have
capcitance that will also contribute to the imaginary part of the
impedance.
2- At higher frequencies (5- 6 GHz), the device capacitances can be
accounted for, as a first order approximation, as follows:

                 o Vcc/ Vdd etc.
                 |
       ----------|
       |         |
       |    _____|_____
       |   |     B     |
      ===  |     L     |
       |   |     A     |
       |   |     C     |
   o-------|     K     |------o output
 input |   |           |    |
       |   |     B     |    |
       |   |     O     |    |
       |   |_____X_____|   === pin capacitance
      ===        |          |   
       |         |          |
       ----------|-----------
                 |
                 o
               Ground

There may be another feedback capacitance from supply to ground. How
these capcitances can be estimated, or measured are to be addressed.
Also, what will be the optimum model to include the device
capacitances, needs to be discussed.
However, the primary question to address is, are these effects
important to take into account for signal integrity/ EMI analysis?
Secondly, is it within IBIS's charter to address such effects in the
models?
Thanks & look forward to hear from fellow IBISians......

Ravender