Subject: High freq effects in i/o mo

From: "Ravender Goyal" <[email-masked]>
Date: 6 Jan 1994 09:43:09 -0800

High freq effects in i/o modeling           9:07 AM       1/6/94
Dear IBISers,

I am starting this discussion to get your inputs on including the high
frequency effects  (4- 5 GHz) in IBIS models. 
As we know the signal integrity analysis accuracy depends as much on
accurately evaluating the electrical characterisitcs (characteristic
impedance, trace velocity, dispersion, to name a few) of interconnects,
as it depends on the accuracy of evaluating or specifying the
terminating impedances- i.e. the i/o models.
For EMI (Electromagnetic Interference) analysis, the frequency of
analysis is upto several GHz, as required by the FCC, European FCC etc.
guidelines. Hence, for EMI analysis upto what ever frequency of
interest, it is critical to have  i/o model that is valid at that
frequency, else results from EMI analysis could be grossly  inaccurate.
In order to include the high frequency effects, it is general
impression (as I have heard in the past) that one may have to give up
the proprietary information about the process. However, just for
accurate impedance presentation, that may not be necessary. To give an
example:
1- Today the i/o model is represented as follows:
                                       
                                       |   Vcc/ Vdd/ etc.
                            ____|____
                            |          B             |
                            |           L             |
                            |           A             |
input o--------|            C             |---------o output
                            |            K             |       |
                            |                            |        |
                            |      BOX            |     === pin
capacitance
                            --------------------         |
                                       |                           |
                               Ground
The black box today is an i/v curve which results in a real impedance
only. The  imaginary part of the impedance is contributed by the pin
parasitics only. We all know that the semiconductor devices have
capcitance that will also contribute to the imaginary part of the
impedance.
2- At higher frequencies (5- 6 GHz), the device capacitances can be
accounted for, as a first order approximation, as follows:

                ---------------  |   Vcc/ Vdd/ etc.
               |            ____|____
               |            |          B             |
             ==         |           L             |
               |            |           A             |
input o--------|            C             |---------o output
                 |          |            K             |       |
                 |          |                            |        |
                 |          |      BOX            |     === pin
capacitance
               ==       --------------------         |
                 |                      |                          |
                  ------------   Ground

There may be another feedback capacitance from supply to ground. How
these capcitances can be estimated, or measured are to be addressed.
Also, what will be the optimum model to include the device
capacitances, needs to be discussed.
However, the primary question to address is, are these effects
important to take into account for signal integrity/ EMI analysis?
Secondly, is it within IBIS's charter to address such effects in the
models?
Thanks & look forward to hear from fellow IBISians......

Ravender

---

From: [email-masked] (Chuck Catto @ PCB x5506)
Date: Thu, 6 Jan 94 10:47:17 -0800

Ravender,

Yes, whole heartedly!  Way back when, when I first started using
Quad, the one question I had in mind was freqency dependent char-
acteristics of the output drivers and input receivers.  All mea-
surements are done at DC, without any jw effects taken into ac-
count.  And in doing so, as you have stated below, this would 
lead to an understanding of the modelization or internal char-
acteristics of those devices looking into the output of a driver
or into the input of a receiver.

I feel it is necessary to take the imaginary component into effect,
and not rely simply on a lumped capacitance to a pin are some
"equivalent" series inductance of an io pin.  The modeling becomes
even more important at higher frequencies, as you mentioned.

I did not fully get your drawings, with the BLA K.  I was trying
to make sense, and thought perhaps the L meant inductance, etc.,
but lost it in the BA and K.  A FAX with a sketch would do me 
fine, and would be much appreciated.

I read with much interest your work on producing more accurate closed
form equations for characteristic impedance, etc. I think you are
doing an excellent job, and I am glad we have the right person at
the helm of this 'high-speed' ship.  I have a lot of respect for you.

Any and all inputs with respect to Quad, IBIS modeling, XFX3D and other
new developments, as well as research you are conducting, is much appreciated.

   Take care,
- Chuck Catto -

****************

On Jan 6,  9:43am, "Ravender Goyal" wrote:
> Subject: High freq effects in i/o mo
>-- End of excerpt from "Ravender Goyal"