Subject: More on BIRD #7

From: Stephen Peters <[email-masked]>
Date: Fri, 21 Jan 1994 16:17:49 -0800

Hello fellow IBISans  --

While reading Kellee Crisafulli's e-mail this morning (1/21), regarding
BIRD #7 and detailing how to measure the ramp rates for the various
type of outputs, it stuck me that nowhere have we specified how to measure
the ramp rate when dealing with ECL.  Although ECL has an output type of
Output or I/O, the ramp time is not measured with the same technique as
used for standard totem-pole outputs.  I agree completely with Kellee that
expanding Section 3 on ramp rates is needed and I would add the following:
(my additions to Kellee's list are shown with a "++").

-------------
 Section 3 on Ramp rates:
  ------------------------
  3) Ramp Rates:
     The ramp rates (listed in AC characteristics below) should be derived
     as follows:

       1)Start with the silicon model, remove all packaging.

       2)If: The model type is one of the following: Output, I/O, or 3-state
          ++ and is not ECL.
         Then: Attach a 50 ohm resistor to GND to derive the rising edge 
               ramp.
	       Attach a 50 ohm resistor to POWER to derive the falling
               edge ramp.

     ++  If: the output type is Output or I/O and is ECL
     ++  Then:  Attach a 50 ohm resistor to the termination voltage 
     ++         (Vterm = VCC - 2v).  Use this load to derive both the
     ++         rising and falling edges.

	 If: The model type is either (Open_drain or I/O_open_drain) and 
             the Pullup V/I table is missing.
         Then: Attach either a 50 ohm resistor or the vendor suggested 
               termination resistance to either POWER or the vendor suggested
               termination voltage.  Use this load to derive both the rising
               and falling edges.

         If: The model type is either (Open_drain or I/O_open_drain) and
             the Pulldown V/I table is missing.
         Then: Attach either a 50 ohm resistor or the vendor suggested
               termination resistance to either GND or the vendor suggested
               termination voltage.  Use this load to derive both the rising
               and falling edges.

	4-6) renumber these 3-5

	7) **** Delete item 7 ******
----------------------

     Best Regards,
     Stephen Peters
     Intel Corp.