Subject: VERSION1.1Y 3 OF 4

From: [email-masked] ( Bob Ross)
Date: Fri, 6 May 94 10:16:29 PDT

|       Points for each curve must span the voltages listed below:             |
|                                                                              |
|       Curve                   Low Voltage             High Voltage           |
|       -----------             -----------             ------------           |
|       [Pulldown]              GND - POWER             POWER + POWER          |
|       [Pullup]                GND - POWER             POWER + POWER          |
|       [GND_clamp]             GND - POWER             GND + POWER            |
|       [POWER_clamp]           POWER                   POWER + POWER          |
|                                                                              |
|       For example, a device with a 5 V power supply voltage should be        |
|       characterized between (0 - 5) = -5 V and (5 + 5) = 10 V;               |
|       and a device with a 3.3 V power supply should be characterized         |
|       between (0 - 3.3) = -3.3 V and (3.3 + 3.3) = 6.6 V for the             |
|       pulldown curve.                                                        |
|
|******************************************************************************
|*                       BIRD4 ADDITION FOR VERSION 1.1X
|*     When tabulating output data for ECL type devices, the voltage points 
|*     must span the range of VCC to VCC - 2.2V.  This range applies to both the
|*     pullup and pulldown tables.  Note that this range applies ONLY when
|*     characterizing an ECL output.
|******************************************************************************
|                                                                              |
| 3) Ramp Rates:                                                               |
|       The ramp rates (listed in AC characteristics below) should be          |
|       derived by:                                                            |
|       1.  Start with silicon model, remove all packaging.                    |
|       2.  Attach 50 Ohm resistor to GND to derive rising edge ramp.          |
|       3.  Attach 50 Ohm resistor to POWER to derive falling edge ramp.       |
|       4.  Due to the resistor, output swings will not make a full            |
|           transition as expected.  However the pertinent data can still      |
|           be collected as follows:                                           |
|              a)  determine the 20% to 80% voltages of the 50 Ohm swing       |
|              b)  measure this voltage change as "dv"                         |
|              c)  measure the amount of time required to make this swing "dt" |
|       5.  Post the value as a ratio "dv/dt", the simulation tool vendor      |
|           will extrapolate this value to span the required voltage swing     |
|           range in the final model.                                          |
|       6.  Typ, Min, and Max must all be posted, and are derived at the       |
|           same extremes as the V/I curves, which are:                        |
|                                                                              |
|       Ramp times for CMOS devices:                                           |
|           typ = nominal voltage,  50 degrees C, typical process              |
|           min = low voltage tol, 100 degrees C, typical process, minus "Y%"  |
|           max = hi voltage tol,    0 degrees C, typical process, plus  "Y%"  |
|                                                                              |
|       Ramp times for bipolar devices:                                        |
|           To be determined by manufacturer.                                  |
|                                                                              |
|           Note that the derate factor, "Y%", may be different than that used |
|           for the V/I curve data.  This factor is similar to the X% factor   |
|           described above.  As in the case of V/I curves, temperatures are   |
|           junction temperatures here also.                                   |
|                                                                              |
|       7.  The rise time of an open-drain device must be measured into        |
|           a 50 Ohm pullup resistor tied to the power pin.                    |
|                                                                              |
|******************************************************************************
|*                 BIRD7.2 REPLACEMENT OF 3) FOR VERSION 1.1X
|* NOTE, Items 3. and 7. above deleted, Items 4. thru 6. renumbered 3. thru 5.
|*
|* 3) Ramp Rates:
|*      The ramp rates (listed in AC characteristics below) should be derived
|*      as follows:
|*
|*      1.  Start with the silicon model, remove all packaging.
|*
|*      2.  If: The Model_type is one of the following: Output, I/O, or
|*              3-state (not open or ECL types);
|*              Then: Attach a 50 ohm resistor to GND to derive the rising edge 
|*              ramp.  Attach a 50 ohm resistor to POWER to derive the 
|*              falling edge ramp.
|*
|*          If: the Model_type is Output_ECL or I/O_ECL;
|*          Then:  Attach a 50 ohm resistor to the termination voltage 
|*              (Vterm = VCC - 2v).  Use this load to derive both the
|*              rising and falling edges.
|*
|*          If: The Model_type is either an open_sink type or open_drain type;
|*          Then: Attach either a 50 ohm resistor or the vendor suggested 
|*              termination resistance to either POWER or the vendor suggested
|*              termination voltage.  Use this load to derive both the rising
|*              and falling edges.
|*
|*          If: The Model_type is an open_source type;
|*          Then: Attach either a 50 ohm resistor or the vendor suggested
|*              termination resistance to either GND or the vendor suggested
|*              termination voltage.  Use this load to derive both the rising
|*              and falling edges.
|*
|*      3.  Due to the resistor, output swings will not make a full         
|*          transition as expected.  However the pertinent data can still  
|*          be collected as follows:                                     
|*             a)  determine the 20% to 80% voltages of the 50 Ohm swing    
|*             b)  measure this voltage change as "dv"                        
|*             c)  measure the amount of time required to make this swing "dt"
|*      4.  Post the value as a ratio "dv/dt", the simulation tool vendor     
|*          will extrapolate this value to span the required voltage swing   
|*          range in the final model.                                        
|*      5.  Typ, Min, and Max must all be posted, and are derived at the     
|*          same extremes as the V/I curves, which are:                      
|*                                                                           
|*      Ramp times for CMOS devices:                                         
|*          typ = nominal voltage,  50 degrees C, typical process            
|*          min = low voltage tol, 100 degrees C, typical process, minus "Y%"
|*          max = hi voltage tol,    0 degrees C, typical process, plus  "Y%" 
|*                                                                          
|*      Ramp times for bipolar devices:                                      
|*          To be determined by manufacturer.                               
|*                                                                           
|*          Note that the derate factor, "Y%", may be different than that used
|*          for the V/I curve data.  This factor is similar to the X% factor  
|*          described above.  As in the case of V/I curves, temperatures are  
|*          junction temperatures here also.                                  
|******************************************************************************
|
| It is expected that this data will be created from silicon vendor            |
| proprietary silicon-level models, and later correlated with actual device    |
| measurement.                                                                 |
|==============================================================================|

|******************************************************************************|
|           ADDITIONAL NOTES FOR IBIS EXTENSIONS     (BIRDS)                   |
|******************************************************************************|

*******************************************************************************

NOTES ON BIRD2.2

3) Add the following requirements to [Model]: 

The model types Input, I/O, I/O_open_drain, I/O_open_sink,
I/O_open_source must have Vinl and Vinh defined. If
they are not defined, the parser will issue a warning and the default
values of Vinl=.8V and Vinh=2.0V will be assumed.

The model types  Input_ECL and I/O_ECL must have Vinl and Vinh defined. If
they are not defined, the parser will issue a warning and the default
values of Vinl=-1.475V and Vinh=-1.165V will be assumed.

ECL defaults derived from FAIRCHILD F100K ECL
data book specification of Guaranteed input HIGH and LOW.

4) The following is added to the differential specification to clarify
Differential input threshold:

If a pin is a differential input pin the differential input threshold
(vdiff) overrides and supercedes the need for Vinh and Vinl. 

If vdiff is not defined for a pin that is defined as requiring a Vinh by
its [Model] type, the parser will issue a warning and vdiff will be set to
the default value of 200mV.

5) The golden parser must be modified to allow "Terminators" and (4) and
check for (3) and (4).

******************************************************************************

NOTES ON BIRD9.3

  A set of terminator components is useful to be formatted using IBIS because
they are found as packaged components.  All of the options can support (typ),
(min) and (max) specifications.

(1) Parallel Resistor Termination:

  The additonal elements [Rpower] and [Rgnd] provide terminations to Vcc, Gnd
or both.  Devices such as the Motorola MCC142233 to MCC142236 Switchable SCSI
Passive Bus Terminator series would be modeled with these elements. 

  At least two other techniques could be used in IBIS Version 1.1.  The 
[POWER_clamp] or [GND_clamp] tables could be used (with as few as two data
points each) to represent resistors.  Another method could be to use R_pkg
(or R_pin) with [POWER_clamp] or [GND_clamp] structures configured as a 
very low impedance.  Processing tabular data for these purposes would be less
efficient and less obvious than working with resistive elements directly.  

(2) RC (or AC) Termination:

  R_pkg (or R_pin) and C_comp can provide RC terminations.  This proposal
specifies [Rac] connected to [Cac] elements.  This will allow packaged RC
terminations which include built in clamping diodes to be modeled directly.

  Diode terminators already can be modeled using IBIS Version 1.1:

(3) Diode Termination:

  Devices such as the TI SN74S1050 thru SN74S1056 Schottky Barrier Diode
Bus-Termination Arrays can be modeled using existing [POWER_clamp] and
[GND_clamp] structures. 

  The total context model is attached showing the proposed additions. 

                        |<-------------TERMINATOR Model--------------->|

                            VOLTAGE RANGE or
                            POWER_CLAMP REF
                                   o
                                   |
                        POWER_ |---o---|
                        CLAMP  |       |
                            |--o--|    \
                            |     |    /
                            | VI  |    \ RPOWER    PACKAGE Keyword
                            |     |    /              Parameters
                            |--o--|    |        |<----------------->|
                               |       |            
                               |       |                               PIN
                         o-----o-------o-----o-----/\/\/\--UUUUUU---o--o 
                         |     |GND_   |     |      R_PKG   L_PKG   |
                         |     |CLAMP  |     |                      |
                         |  |--o--|    |     |                      |
                         |  |     |    \     |                      |
                         |  | VI  |    /RGND |                      |
                         |  |     |    \     \                      |
                         |  |--o--|    /     / RAC                  | 
                         |     |       |     \                      |
                         |     |---o---|     /                      |
                         |         |         |                      |
                 C_COMP ---        o        --- CAC          C_PKG ---
                        ---     GND or      ---                    ---
                         |   GND_CLAMP REF   |                      |
                         |                   |                      |
                         |-------------------o----------------------|
                                             |
                                             o
                                            GND

                                      |<-------->|
                                        Proposed 
                                       Terminator
                                        Keywords

******************************************************************************

NOTES ON BIRD10.1

Refer to BIRD10.1 for the complete specification and description

STATEMENT OF THE RESOLVED SPECIFICATIONS:

Summary: 
-------

A new keyword, [Package Model], is added to the .ibs file.  This
keyword is used within a [Component] to indicate (by name) the package
model that should be used for a part.  Package models can be found
either in separate package model files, which bear the .pkg extension,
or within the same .ibs file as the [Component].  An additional new
keyword, [Define Package Model], is also added to the specification;
this is used to mark the beginning of the actual package model data.
The purpose of breaking up the package model and the component model
is to make associations between the two more flexible: several
components may share a single package model, or one component may have
several different incarnations which use different packages (and thus,
different package models).

Use of [Package Model] is OPTIONAL.  If it is not provided, then the
table of RLC values listed in the [Pin] section of the [Component] is
used as the "package model" for the part.  On the other hand, if the
[Package Model] IS given, then the R_pin, L_pin and C_pin values in
the [Pin] section may either be ignored, or may be used for less
detailed simulations without coupling.  Probably this data will simply
be left out of the [Pin] section when a [Package Model] is used;
this practice is permitted by the IBIS Ver. 1.1 specification since 
[Pin] data may contain either 3 or 6 columns.

A .pkg file is just an ordinary IBIS file, with the restriction that
it cannot contain [Component]'s or [Model]'s.  Only package models
declared by the [Define Package Model] keyword may be contained within
these files.  Of course, all of the necessary components of an IBIS
file ([IBIS Ver], [File Name], [File Rev], etc. through [End]) must
still be included within a .pkg file.

The package model to be used treats every package as a collection of
current carrying "paths," which lead from the board, through the
packages pins, leadframe traces and bonding wires to a bonding pad on
the die itself.  Each path has a self-resistance, self-inductance and
self-capacitance associated with it.  In addition, there is the
flexibility to describe mutual inductance, mutual resistance and
coupling capacitance drops between every path.  This data can be
listed concisely as three RLC parameter matrices.  This BIRD describes
how these matrices are to be formatted.

******************************************************************************

NOTES ON BIRD11.2 ... THESE NOTES REFER TO CHANGES IN THE IBIS_CHK PROGRAM

   ***************************************************************************
Change 2- Add detection to IBIS_CHK program for V/I table 'I' sign errors.
   ***************************************************************************
For each of the following V/I tables: Pullup, Pulldown, POWER_clamp, GND_clamp

  1) Find the minimum and maximum voltage points (Vmin, Vmax) in the table.

  2) IF:The current in the TYPICAL column corresponding to Vmax is less than
        the current in the TYPICAL column corresponding to Vmin than the table is
        assumed to have decreasing current.
     ELSE IF:The current in the TYPICAL column corresponding to Vmax is greater 
        than the current in the TYPICAL column corresponding to Vmin than the
        table is assumed to have increasing current.
     ELSE: The table is assumed to have equal current."

     Note: This works for all cases of discontinuities unless the magnitude of
           discontinuity is such that this model is in all probability competely
           unrealistic.

     Examples:
        *** example with non-monotonic data at the end point
        V:      I:
        0.00    0.0
        4.90   50.0ma
        4.91   49.9ma
        4.93   56.7ma
        5.00   3.0ma  -> V/I table has increasing current (3.0 > 0)
                             Vmax = 5.0, I =3.0mA
                             Vmin = 0.0, I =0.0

        *** example with negative to positve voltages with negative first	
        V:      I:
       -5.00   -0.1ma
        0.00    0.0
        5.00  100.0ma  -> V/I table has increasing current (100 > -0.1)
                             Vmax = 5.0,  I=100mA
                             Vmin = -5.0, I=-0.1mA

        *** example with table data entered postive voltages first
        V:      I:
        5.00   10.1ma
        0.00    0.0
       -5.00   -10.1ma  -> V/I table has increasing current (10.1 > -10.1)
                             Vmax = 5.0,  I=10.1mA
                             Vmin = -5.0, I=-10.1mA

        *** example with only two entrys
        V:      I:
        0.00    0.0
       -5.00   10.1ma  -> V/I table has decreasing current (0 < 10.1)
                             Vmax = 0.0,  I=0
                             Vmin = -5.0, I=10.1mA
        *** ECL example
       [Pullup]
       Voltage   I(typ)    I(min)    I(max)
        0.0       0         0         0
        0.7       -0.2m     -0.2m     -0.2m
        0.73      -0.4m     -0.4m     -0.4m
        0.75      -0.8m     -0.8m     -0.8m
        0.76      -1.2m     -1.2m     -1.2m
        0.77      -1.6m     -1.6m     -1.6m
        0.8       -4.4m     -4.4m     -4.4m
        0.82      -7.6m     -7.6m     -7.6m
        0.85     -14.2m    -14.2m    -14.2m
        0.9      -30.0m    -30.0m    -30.0m
        1.0      -58.0m    -50.0m    -68.0m  -> V/I table has decreasing current ( -58 < 0)
                                                 Vmax = 1.0,  Ityp=-58mA
                                                 Vmin = 0,    Ityp=0

       [Pulldown]
       Voltage   I(typ)    I(min)    I(max)
        0.0       0         0         0
        1.6       -0.2m     -0.2m     -0.2m 
        1.62      -0.4m     -0.4m     -0.4m
        1.64      -0.6m     -0.6m     -0.6m
        1.65      -0.8m     -0.8m     -0.8m
        1.66      -1.2m     -1.2m     -1.2m
        1.67      -1.6m     -1.6m     -1.6m
        1.68      -2.4m     -2.4m     -2.4m
        1.69      -3.2m     -3.2m     -3.2m
        1.70      -4.4m     -4.4m     -4.4m
        1.72      -7.4m     -7.4m     -7.4m
        1.75     -14.2m    -14.2m    -14.2m
        1.8      -30.5m    -30.5m    -30.5m 
        1.9      -65.0m    -60.0m    -75.0m  -> V/I table has decreasing current ( -65 < 0)
                                                  Vmax = 1.9, Ityp=-65mA
                                                  Vmin = 0.0, Ityp= 0

        *** An abreviated INTEL model for a CMOS output
        
  |****************************************************************************
        [Pulldown]
        |  Voltage         I(typ)          I(min)          I(max)
	   -5.00V         -38.70mA        -29.47mA        -51.22mA
	   -1.00V         -24.88mA        -19.18mA        -32.90mA
	   -0.50V         -14.35mA        -11.06mA        -19.05mA
	    0.00V         -11.84pA       -554.66pA        -11.03pA
	  100.00mV          3.20mA          2.47mA          4.27mA
	  200.00mV          6.24mA          4.80mA          8.30mA
	    4.90V          38.68mA         29.45mA         51.18mA
	    5.00V          38.70mA         29.47mA         51.22mA
	   10.00V          39.96mA         30.37mA         53.06mA -> V/I table increasing
        [GND_clamp]
        | Voltage         I(typ)          I(min)          I(max)
	   -5.00V        -680.00mA      NA              NA
	   -1.10V         -75.50mA      NA              NA
	 -600.00mV       -950.00uA      NA              NA
	 -500.00mV        -78.00uA      NA              NA
	 -200.00mV          0.00pA      NA              NA
	 -100.00mV          0.00pA      NA              NA
	    0.00V           0.00pA      NA              NA