Subject: EGG2 COMMENTS

From: [email-masked] ( Bob Ross)
Date: Sat, 9 Apr 94 18:13:03 PDT

To Stephen Peters and IBIS Committee:

Stephen, I am pleased to see a start in describing in more detail the time
domain characteristics of the buffer.

Since the status of EGG2 is in the prehatch stage, my comments relate to
preferences as to what should be included.  My overall position is that
the response data should be presented from well defined test conditions 
without any further processing.  As a reasonable approximation, that
could define the response shape of the generator - as a tabular or piecewise
representation.  The simulator vendors may choose to do further processing
and reformatting of the data such as into %voltage vs %time tables in a manner
consistent with their data structures and internal algorithms.  This 
transformation would cover the edge rate control buffer response which
uses phased turn on of multiple transistors that you described.  Furthermore,
the simulator vendors may choose to convert this data through "optimization"
or other processes such that a MODIFIED table reproduces the original,
specified data when All elements of the simulator specific internal model and
high-to-low and low-to-high transition algorithms are considered.  This
could provide more accurate models for other types of devices as well.

Alternatively, the simulator company may choose to use this data as the
basis for deriving the dV/dt_r and dV/dt_f ramp rates that best produce
and match the specified response, rather than just base them on 20-80% 
points.  Thus a tabular representation of the time response is valuable
to those vendors which do not have full support of V-T tables.  Fixed ramps
may be fully adequate for the types of analysis done by that simulator.

So, the emphasis if this comment is that if V-T tables are given, they come
directly from extractions and be formatted in Voltage vs Time Tables.

Bob Ross,
Interconnectix, Inc.