Subject: Pullup/down data

From: Tareq Shahwan <[email-masked]>
Date: Mon, 13 Nov 1995 16:04:27 -0600 (CST)

All,

 I need some clarification on the following :

 (1) When running simulations on an "input buffer with Bus-Hold" to extract clamp
     data, should the bus-hold circuitry be disconnected ?.  In other words,
     should we include the contribution from the Bus-Hold circuit in the clamp data.
     I would think not, any suggestions ?
 (2) Similarly, some of our devices have the so called Power-on-demand (POD) feature
     on the output buffer.   In a BiCMOS device, this feature works to reduce the
     base current in the pulldown transistor when the output voltage is below a preset
     level, thereby reducing power consumption.  While this circuitry can be
     disconnected in a simulation, it is always present in real-life.  Again, should
     the effect of such circuit be incorporated into the pulldown data ?. 

  Please advise !

Regards,
Tareq Shahwan, ABI Applications

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From: Arpad Muranyi <[email-masked]>
Date: Mon, 13 Nov 95 15:11:00 PST

Text item: 

Tareq,

These are very good questions!

1)  I think this kind of an input must be handeled as if it would be an output 
or an I/O buffer.  However, a lot depends on how it works.  If the HOLD circuit 
is always on, model it as if it would be an OUTPUT buffer.  If the HOLD circuit 
is getting turned on after a certain amount of time (from when it saw a 
transition), I would model it as if it was an I/O buffer which starts driving 
shortly after it saw an edge.  I know, this is a simplistic answer and there 
might be more to it than that.  More complicated cituations might not be 
possible in IBIS as of right now.

2)  The answer to this depends on how this power saver works.  Does it 
immediately turn off if it sees that pre-determined voltage level, or later?  If
this save mode does not come into effect untill the reflections are settled, I 
would not worry about modeling it.  However, if it reduces the drive strength 
while the signal is still bouncing back and fourth, it might be important to 
model it, since the reflection coeffitients depend on the driver impedance 
(=strength).  How you do it, is another question.  Not knowing the guts of your 
buffer, I am just guessing, but using the V-t curves might be one possible way 
of doing it if it is time dependent.  If it is only voltage dependent, it would 
most likely show up in the shape of its I-V curve.

Arpad Muranyi
Intel Corporation
================================================================================

All,

 (1) When running simulations on an "input buffer with Bus-Hold" to
extract clamp
     data, should the bus-hold circuitry be disconnected ?.  In other words,
     should we include the contribution from the Bus-Hold circuit
in the clamp data.
     I would think not, any suggestions ?
 (2) Similarly, some of our devices have the so called Power-on-demand
(POD) feature
     on the output buffer.   In a BiCMOS device, this feature works
to reduce the
     base current in the pulldown transistor when the output voltage
is below a preset
     level, thereby reducing power consumption.  While this circuitry can be
     disconnected in a simulation, it is always present in real-life.
 Again, should
     the effect of such circuit be incorporated into the pulldown data ?.

  Please advise !

Regards,

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Date: Mon, 13 Nov 1995 16:04:27 -0600 (CST)
To: [email-masked] (ibis @vhdl.org)
Subject: Pullup/down data
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From: Tareq Shahwan <[email-masked]>
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From: Stephen Peters <[email-masked]>
Date: Mon, 13 Nov 1995 17:46:56 -0800

Hello Tareq, Arpad, others:

     Yes, very good questions.  I read Arpads answer to your first
question below, but I assumed that the BUS HOLD feature
you refered to is just a weak current source (maybe a resistor?)
that pulls the input to a know voltage level if nothing else 
is driving that input.  In that is the case, I belive that the extra 
current belongs in one of the clamp curves and the input should be modeled
as an input, not as an output or I/O.

        Regards,
        Stephen Peters
        Intel Corp.

Tareq,

Arpad Muranyi
Intel Corporation

All,

  Please advise !

Regards,

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From: Andy Ingraham <[email-masked]>
Date: Tue, 14 Nov 95 08:54:03 EST

>     I would think not, any suggestions ?

"Bus-hold" circuits typically use two weak inverters connected in a
positive feedback loop.  Modeling this with any V/I simulator will be
problematic, because the static V/I curves depend on past history, not
just on present voltage.  It is impossible to do this with a V/I
simulator.  (Not to mention the implication of negative resistance,
which even some SPICE-like simulators have trouble dealing with.)

In principle you should include everything.  You would have to pick one
of the states, for the region where the two V/I curves don't overlap. 
If the contribution to current is small, you might justify omitting it;
but then your simulations could be in error if the feature is used.

Regards,
Andy Ingraham