Subject: Re: Use of IBIS

From: Fred Vance <[email-masked]>
Date: Tue, 19 Sep 95 15:41:35 -0700

>Who are the vendors that support IBIS for
>static timing analysis and/or logic simulation?

I believe that any tool that simulates interconnect delay could be  
used to provide input for any static timing analysis and/or logic  
simulation. Some tools may integrate the two analyses to a higher  
degree than others.

As for the quotation:

>" From all the EDA vendors that I know that are
>supporting IBIS, their targte is not logic synthesis,
>it is not static timing analysis, it is not logic simulation,
>it is not floorplanning, etc. IBIS is primarily a modeling
>of the exterior of the Chip I/O targeted to support intra-chip
>delays, noise, and waveform propagation."

This is a statement that might be argued either way. If a design is  
running slow enough or (PCB traces are short enough), then the  
interconnect delay may be inconsequential. However with core logic  
driving nets external to the ASIC at clock rates of 66MHz and higher,  
the interconnect delay is significant.

If you accept the premise that interconnect delay is significant,  
then any tool that uses IBIS models will be of value in timing  
analysis, logic simulation, floorplanning, etc.

Fred
FirePower Systems, Inc.