Subject: Use of IBIS

From: [email-masked] (MR RONALD J CHRISTOPHER)
Date: Tue, 19 Sep 1995 15:39:31 EDT

-- [ From: Ron Christopher * EMC.Ver #2.10P ] --

I understood IBIS is used as the circuit model to support delay
calculation which  in turn supports static timing verification and/or
dynamic delay logic simulation.  I know it is also used for noise
analysis or signal integrity.

I picked this up over on the CFI/OVI reflector.
" From all the EDA vendors that I know that are supporting IBIS, their
targte is not logic synthesis, it is not static timing analysis, it is
not logic simulation, it is not floorplanning, etc. IBIS is primarily a
modeling of the exterior of the Chip I/O targeted to support intra-chip
delays, noise, and waveform propagation."

Who are the vendors that support IBIS for static timing analysis and/or
logic simulation?  I thought at least EPIC and Quad do.  Am I correct,
and are there more?

Ron Christopher

---

From: [email-masked] (Jon Powell)
Date: Mon, 25 Sep 95 09:04:30 PDT

Quad supports IBIS for static timing verification in the following manner
(which we consider the right way to do it, by the way):

XTK uses IBIS to model transmission line effects for highly accurate analog
simulations. From these Simulations and knowledge of Time to VM for the driver
and logic thresholds for the receiver we calculate min max pin to pin delay data
which is communicated to MOTIVE (our static timing analysis tool) thourgh IDD or
SDF file formats.

Regards,
jon powell
quad design