Subject: GND Plane Bounce Question

From: Samie Samaan <[email-masked]>
Date: Mon, 21 Aug 95 11:22:00 PDT

Text item: Text_1

     All IBISians (SI experts by Default !!)
     
     I would like to pose the following SI question, and solicit help from 
     those who actually know the answer or have a very good idea of how to 
     estimate it by scaling from previous experience:

     Assume one GND and one power plane in a PCB separated by say 10 mil, 
     with a dielectric constant of say 4. assume that the power plane has a 
     via opening where current is injected thru the via down to the GND 
     plane. Let's say that the current is 10 Amps. with a riserime of 1 ns. 
     Assume nominal via diameter. The drawing below shows the structure:

                      |        Vcc
     ---------------- | ------------------
                      |        GND         10 mil, Er=4
     -----------------|-------------------

     What I would like to hear from anybody who actually has experienced 
     GND plane bounce, is: 
     
     *howmuch do you expect the GND plane (not the via stem) to bounce up 
     (locally) given the above assumptions, and
     
     *howfar away from the via (radially) do you expect the bounce to drop 
     to 10% of the peak which occurs right where the via meets the plane ?
     
     I would apprciate a good guess (and Why: perhaps from previous 
     experience), or direction as to "who ?" you think could answer such a 
     question. I know that I might need to do a 3-D or radial transmission 
     line analysis of the system, but I'm really just looking for a quick 
     answer.

     Thanks for taking the time to read or answer this question.
     
     Samie Samaan
     Intel Corp.

---

From: Nirmal Jain <[email-masked]>
Date: Tue, 22 Aug 95 10:53:01 EDT

Samie

>
>
>Text item: 
>
>     
>     
>     Nirmal,
>     
>     Thank you for the help. I do not think that knowing the source and where 
>     its retrun is are crucial to answering the question as I posed it !
>     
>     Simply assume that I magically could inject 10 amps in 1 ns to the GND 
>     plane thru the via, my question is what voltage spike would you see on that 
>     plane ?? 
>     
	The above would be the case if the ground plane in your design is an 
	ideal GND plane and is sinking all the current. Then the Leff would be
	due to the via only and the SSN would be
		
		Vssn = Lvia * 10A/1ns

	If the above plane is NIGP ( Non-ideal Gnd plane ) then the current flow
	is going to depend on how this GND plane is connected to other reference	GNDs in the design. The L due to the NIGP would depend upon
	this current flow. If you have more terminal on the GND plane your
	L due to GND plane will be lower ( becos now you have more number
	of current paths).

	Hope it makes sense. If it does not we can discuss it further 
	or may be you can call me at (412-261-3200 X29).

	Regards
	
	Nirmal
	ANSOFT

>     Am I missing something ? Does one really have to know the rest of teh 
>     topology to answer the question ?
>     
>     Thanks again
>     
>     Samie Samaan
>
>______________________________ Reply Separator _________________________________
>Subject: Re: GND Plane Bounce Question
>Author:  [email-masked] at SMTPGATE
>Date:    8/21/95 4:10 PM
>
>
>>
>>
>>Text item: Text_1
>>
>>
>     The ground bounce depends on the inductance presented to the path of
>     current. The correct approach is to treat the plane as multi-terminal
>     conductor and solve for L matrix for all those current paths.
>
>     So in the above fig you have to have another terminal or terminals
>     on the GND plane which would define the current path and hence
>     ground bounce. So we need the information about how the current
>     flows on the gnd plane. If you have more current terminals onthe GND
>     plane your effective inductance will be lower and hence GND bounce.
>
>
>     Best regards
>
>     Nirmal
>
>>
>>
>_______________________________________________________________________________
>Nirmal Jain                             ANSOFT CORPORATION
>(412) 261-3200 X29 (W)                            Four Station Sq., Suite 660
>(412) 471-9427(FAX)                           Pittsburgh, PA 15219
>_______________________________________________________________________________

---

From: Samie Samaan <[email-masked]>
Date: Tue, 22 Aug 95 08:43:00 PDT

Text item: 

     Frank,
     
     Thank you very much for taking the time to address this problem. In 
     fact I would like to know more about this tool, if you can send me 
     some info on it. My address is with Quad, and also at the bottom. The 
     numbers you give me are a big help. With a formula provided by someone 
     else, I will have a good idea of what to expect.

     I would like to comment on this whole issue a bit, and address what 
     prompted my question in the first place:-
     
      Some of the colleagues who answered my inquiry, correctly indicated 
     that I should designate the source of the current and not just its 
     sink. So I answered one of them by saying the following: Assume that I 
     can magically inject the current into the GND plane thru the 
     via...etc. The reason I say that is because I was really interested in 
     local bounce, with the closest discontinuity to the GND plane being a 
     few inches away. Such a case arises when you are dealing with, say, 
     open collector buffers, where the collector is tied to a signal trace 
     on the top layer of my hypothetical board, while the emitter pumps the 
     GND plane thru the via. The source of the current has to tie back to 
     the plane at some distant point, but that is not very relevant (in my 
     opinion) during the first few 100 ps's of the transient around the 
     via.
     
      The real reason I asked the above question has not been stated by me 
     yet. Well, here it goes: If one is trying to measure Clk-out delay 
     (Tco) of a buffer using a scope, and places the scope ground near my 
     via, while placing the scope's active lead at the bit of interest, 
     then, I believe, that if many bits are switching, that the waveform 
     seen by the scope would be distorted by the GND plane bounce. Say you 
     have a falling edge (while many bits toggle down), then since the GND 
     bounces up, the scope would read a smaller voltage (its gnd lead is 
     moving up too), and show the edge to be just as fast as when a single 
     bit switches (or nearly so) even though the edge has --in reality-- 
     slowed down due to SSO. So one has to be more clever as to where to 
     measure Tco is such situations.
     
     Do others agree with my assesment ??
     
     Sincerely,
     
     Samie Samaan
     Intel
     2111 NE 25th Ave
     Hillsboro, OR 97124.

______________________________ Reply Separator _________________________________
Subject: Re: GND Plane Bounce Question
Author:  [email-masked] at SMTPGATE
Date:    8/21/95 6:31 PM

   Hi, Samie,

   I did some quick and simple simulations for your GND plane bounce problem
   using the power/ground plane simulation tool we have at Quad Design.
   The PCB is same as yours, and the size is 10x10 inch.  Assume the current
   is 10 mA (instead of 10 Amps in your message), and there are no de-caps or
   other loads between the power/ground plane, the local ground bound is about
   8 ~ 10 mV, assuming the current source has a 50 ohm internal resistance.
   The ground noise propagates all over the plane, so the bounce away from the
   via is lower but not too much than that at the vis. Depending on location,
   the bounce is 2 ~ 6 mV. The location of the via also have some effects on
   bounce, but is usually small.

   Note that if you really have a 10 Amps current, the bounce would be 8 ~ 10
   volts. That will be a truly unusual or extrame situation.

   The above results assuming the power/ground planes are open (or no other
   terminations), This usually gives higher estimate of GND bounce because of
   the resonance of the plane. From my experice, the things affect the ground
   bounce mostly are your loads, especially decoupling capacitors. Proper
   placement of de-caps of 10~100 nf can significantly reduce the GND bounce
   in the above situation, by 5 ~ 10 times.  Resistive loads have little
   effects on the GND bounce unless it is really small ( about 0.1 ohm for
   the above example).

   Our tool can do a much better job in extimating GND bounce if you have
   more information about the geometry, the ternimation or load conditions,
   and the source or device characteristics. Hope this is useful for you.

   Regards

   Frank Yuan
   Quad Design Technology
   (805) 988-8250

> From uunet!ccm2.jf.intel.com!Samie_Samaan Mon Aug 21 13:11:20 1995
> Date: Mon, 21 Aug 95 11:22:00 PDT
> From: Samie Samaan <uunet!ccm2.jf.intel.com!Samie_Samaan>
> To: uunet!vhdl.org!ibis
> Subject: GND Plane Bounce Question
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Cc: [email-masked], [email-masked]
Subject: Re: GND Plane Bounce Question
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From: [email-masked] (Frank Yuan)
Date: Mon, 21 Aug 95 18:31:04 PDT
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From: [email-masked]
Date: Tue, 22 Aug 95 13:43:59 MST

Samie,

I agree. However, it is not a matter of where you measure.
As soon as your prober touches the bit of interest, SSO noise will
be reduced because of the current through the prober capacitor 
to the ground plane. In that case, true Tco will be in question.

Regards,

Sung Oh
VLSI Technology, Inc.
 
 >>From [email-masked] Tue Aug 22 09:11 MST 1995
 >>Date: Tue, 22 Aug 95 08:43:00 PDT
 >>From: Samie Samaan <[email-masked]>
 >>To: [email-masked], [email-masked],
 >>        [email-masked]
 >>Subject: Re[2]: GND Plane Bounce Question
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 >>     Frank,
 >>

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From: [email-masked] (Frank Yuan)
Date: Tue, 22 Aug 95 19:52:01 PDT

Samie,

I agree with your assesment.  Also, if you only care about the bounce
during the first few 100 ps's of the transient around the via, I have 
the following numbers you might be interested. 2 - 3 inch away from the 
via, the bounces are about 1.0 mV, 1.5 mV and 2.0 mV at 100 ps, 200 ps,
and 400 ps, respectively. 5 - 6 inch away from the via, they are 0.1 mV,
0.4 mV and 1.0 mV, respectively, and about 10 inch away, the bounce is less
than 0.1 mV at 400 ps. (all assuming 10 mA current).

I will also send you some information about our power/ground simulation tool 
later (the tool is still under development and has not been released jet).

Regards,

Frank

> From uunet!ccm2.jf.intel.com!Samie_Samaan Tue Aug 22 09:16:17 1995
> To: uunet!vhdl.org!ibis, uunet!fyuan%qdt.com%uunet,
>         uunet!uunet!uunet!ccm2.jf.intel.com!Samie_Samaan
> Cc: uunet!uunet!qdt.com!jonp, uunet!uunet!qdt.com!fyuan

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From: Arpad Muranyi <[email-masked]>
Date: Wed, 23 Aug 95 10:14:00 PDT

Text item: 

Sung,

I have a hard time to believe that an active probe with a few tenths of pF will 
have an effect like that.  On the other hand, the GND lead of the probe might 
give an extra path to the GND currents, which might reduce the bounce some.

Arpad
===============================================================================

Samie,

Regards,

Sung Oh
VLSI Technology, Inc.

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Subject: Re: Re[2]: GND Plane Bounce Question
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From: [email-masked]
Date: Wed, 23 Aug 95 10:51:00 MST

Arpad,

Actually, it depends on the parasitic inductance and capacitance between
the driver ground and ground plane. Not only the maximum magnitude of the 
ground bounce but also the pulse duration is dependent on the parasitics.
However, if you are using an active probe and the capacitance is small 
compared to the parasitic capacitance, the probing effect can be safely
ignored.

Sung

 >>From [email-masked] Wed Aug 23 10:27 MST 1995
 >>Date: Wed, 23 Aug 95 10:14:00 PDT
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