From: [email-masked] (MR RONALD J CHRISTOPHER)
Date: Thu, 17 Aug 1995 10:18:59 EDT

-- [ From: Ron Christopher * EMC.Ver #2.10P ] --

I am working as an independent with CFI, EDAC, and Sematech on a 10
year roadmap for electronic CAD standards.  Our work is described on
the WWW at http://www.cfi.org/roadmap/roadMap-eii-report.html.

Our 10 year roadmap should show how we are going to do delay above the
chip.  I thought we would be able to state IBIS, but it doesn't handle
the basic CMOS IV .5um IBM ASIC drivers.  Bob Ward says Version 2.x
does not handle all the TI drivers either.  Can we establish some steps
in the IBIS group to correct this which we could refer to in our
roadmap?

Will Hobbs said, 
" IBIS can handle non-monotonic data.  The parser will detect such data
and issue a warning in the possibility the data is in error, but will
correctly  parse the data.  Whether a given simulator will treat the
data correctly is a  question that should be posed to the forum at
large, as it will generate a good  discussion, as well as answers to
your concerns."

Is it really just the parser when both Bob Ward and my IBM contacts say
Version 2.1 will not handle the non monotonic drivers?  Is there a way
to prove that Version 2.1 of IBIS will truly handle the non monotonic
case as in the IBM CMOS IV drivers?  If IBIS 2.1 can handle it, perhaps
these circuits should be part of a certification plan.

Ron Christopher

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From: [email-masked] (Jon Powell)
Date: Thu, 17 Aug 95 09:49:16 PDT

The problem isn't that IBIS cannot handle non-monotonic drivers. The problem is
more that the silicon vendors have not yet supplied the necessary information about
their devices that would let anyone figure out how to model them. Detailed SPICE
models that reliably predict behavior would be necessary in order for the IBIS committe
to come up with an acceptable methodology to perform behavioral modeling. Current versions
of these drivers are so secret that we are not even sure we can admit that we know they
are secret.

jon powell
Quad Design

---

From: [email-masked]
Date: Fri, 18 Aug 95 08:02:26 PDT

>Quad Design

  The secrecy evidenced by silicon vendors is paralleled by the vendors of design tools 
using IBIS data. The mathematical usage of IBIS data is shrouded in mystery. Indeed, no part
of the IBIS standard indicates how the data is to be used to insure that an adequate analytic
representation of the silicon is made during signal integrity simulation. "Methodology" above
refers to the acquisition of data, not modeling in the sense that occurs for circuit simulation
such as with Spice. 

  In the realm of Spice simulation, the design community, academia and CAD software suppliers
debate at great length the analytic adequacy of representative equations. Strategies for
mathematical representation lie at the core of model evolution. Within IBIS, public strategies
appear to be data focused, generating great arguments concerning what measurements to make
and how to format these for general distribution. In such an arena, engineers cannot decide
whether the IBIS data contains the information and the tools contain the analytic horsepower
to lead to a successful prediction of system performance.   

  For CFI, EDAC orSematech to fashion a meaningful roadmap for addressing signal integrity 
issues for the next ten years I would suggest the move to the analytic focus that has proven 
so fruitful for integrated circuit design. Assemble university representatives, designers and 
suppliers of tools to debate a suitable mathematical representation for behavioral modeling of 
interconnect, packaging and silicon drivers and receivers.