Subject: Re: IBIS EGG9 - Stored Charge

From: [email-masked] ( Bob Ross)
Date: Mon, 11 Dec 95 10:58 PST

Jon:

The RS that appears in Spice models would be modeled inside the IBIS Clamp
tables.  The package Resistance is not shown.  RS should be small, but
is not always 0.

Bob Ross
Interconnectix, Inc.

> Do we already have a place for the Rs? The experiments I did last year when we
> were talking about this indicate that Rs is essential (for at least) scientific
> study of TT. It is unclear if Rs is ever very much bigger that 0 for real circuits.

> jon

> If people are looking for a good mathematical expression of this they can look in
> any text book on SPICE under diode behavior. Working (and simple) equations are
> presented.

>                           
>                    Intrinsic
>              RS      Diode                        +-----+
>                       |\ | ----> Id               |     | ----> Id
>        o---/\/\/\--+--| >|--+----o          +-----|Clamp|-----+
>                    |  |/ |  |               |     |     |     |
>                    |        |          o----|     +-----+     |----o
>                    |   | |  |               |       | |       |
>                    +---| |--+               +-------| |-------+
>                        | |                          | |

>                      Cj + Ct                     C_comp + Ct

---

From: [email-masked] (Jon Powell)
Date: Mon, 11 Dec 95 11:17:37 PST

Bob,

If you are suggesting that the Rs be a part of the IV table itself and just
restrict the current, I believe that this will not work. The Voltage that contrains
the current is actually across the (what is now) voltage controled capacitor and
and Rs is external to this effect. I have done tests with behavior models both ways
and believe I can show the difference.

jon powell
quad design