Subject: IBIS MINUTES 12/01/95

From: [email-masked] ( Bob Ross)
Date: Tue, 5 Dec 95 16:01 PST

DATE:    December 5, 1995
 
 SUBJECT: 12/1/95 EIA IBIS Open Forum Meeting Minutes
 
 VOTING MEMBERS:
 AT&T Global Info Solutions     Dave Moxley*
 Cadence Design                 Sandeep Khanna, C. Kumar*
 Contec CAE, Ltd.               Dileep Divekar*
 HyperLynx                      Kellee Crisafulli
 IBM                            Jay Diepenbrock
 INCASES                        Werner Rissiek, Olaf Rethmeier*
 Intel Corporation              Stephen Peters*, Will Hobbs*, Arpad Muranyi,
                                Derrick Duehren
 Interconnectix, Inc.           Bob Ross*
 Meta-Software                  Les Spruiell, Mei Wong, You-Pang Wei, 
                                John Sliney
 Motorola                       Ron Werner
 National Semiconductor         Syed Huq*, Atul Agarwal, Cheng-Yang Kao
 NEC                            Hiroshi Matsumoto, Eldar Yazbashevz
 Quad Design                    Jon Powell*, Chris Myles, Chris Rokusek*
 Quantic Labs                   Mike Ventham*
 Tanner Research, Inc.          Scott Wedge, Ed Miller, Peter Parrish
 Texas Instruments              Roger Cline, Ben Andresen
 Thomson-CSF/SCTF               Jean LeBrun
 UniCAD Canada Ltd.             Stephen Lum
 VLSI Technology                Dick Ulmer, Sung Oh*
 Zuken-Redac                    John Berrie
 
 OTHER PARTICIPANTS:
 AMP                            Hank Herrmann*
 ARPA                           Randy Harr
 Anacad                         Steffen Rochel
 Ansoft                         Henri Maramis
 Atmel Corporation              Dan Terry
 Cadlab                         Ralf Bruning
 CFI                            Ron Christopher, Don Cottrell*
 Digital Equipment Corp.        Barry Katz
 EIA                            Patti Rusher*
 High Design Technology         Michael Smith, Dr. Ing. Cosso
 Hewlett Packard                Tom Langdorf, Karl Kachigan, Henry Wu
 Integrated Silicon Systems     Eric Bracken
 Intergraph                     Ian Dodd, David Wiens, Walter Katz
 IntuSoft                       Charles Hymowitz
 LSI Logic Corp.                Satish Pratadneni
 Mentor Graphics                Ravender Goyal, Greg Doyle
 Micron Technology              Brian Johnson                       
 MicroSim                       Arthur Wong
 North Carolina State U.        Steve Lipa, Michael Steer
 OptEM Engineering, Inc.        Benny Leveille, Ken Ehn
 Pacific Numerix                Paul K. U. Wang
 Symmetry                       Martin Walker
 Synopsys, Logic Modeling G.    Bill Lattin
 Univ. of Illinois, Urbana      Raj Mittra 
 Zeelan Technology              George Opsahl, Hiro Moriyasu
 (Independent)                  Bob Ward

 In the list above, attendees at the meeting are indicated by *.
 
 Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as 
 follows:

      Date       Bridge Number    Reservation #    Passcode  
      12/15/95   (916) 356-9200   2-41859          7747258
      1/12/96    (916) 356-9200   2-41860          1918954

 All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
 7 days before each open forum and meeting minutes out within 7 days after.  
 When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
 Hobbs and give the reservation number and passcode.
 
 NOTE: "AR" = Action Required.
 
 -------------------------------- MINUTES -------------------------------------
 
 INTRODUCTIONS
 Hank Herrmann of AMP, Inc. indicated his interest in IBIS as a result of
 of meeting Stephen Peters at a JEDEC JC-15 meeting.  

 Don Cottrell of CFI joined us to discuss the DCL and Roadmap relationship
 with IBIS. 

 EIA MEMBERSHIP AND TREASURER'S REPORT
 No change in the treasury was reported.  TI did purchase the ibischk2 source
 code.

 MINUTES REPORT, MISC.
 The October 27, 1995 Minutes have been changed to include Kellee Crisafulli
 as an attendee.

 MISCELLANY/ANNOUNCEMENTS
 None.

 PRESS UPDATES
 Patti Rusher reported that the press release announcing the ratification
 of IBIS as EIA-656 was sent out last week.  Will Hobbs indicated that
 he has already had discussion from a United Kingdom publication editor.
 Will Hobbs also reported the EE Times article of November 27, 1995
 "Group eyes 'free' VHDL sim models", by Richard Goering, mentioned IBIS
 and quotes by Will in the article.  The article discussed the Free
 Model Forum activity which is seeking to acquire, develop and distribute
 IBIS models as well.  C. Kumar indicated that representatives were visiting
 Cadence to seek funding from Vendors for modeling efforts.

 NEW MODELS
 The PentiumPro (P6 Models) were made publically available November 1.

 OPENS FOR NEW ISSUES
 Free Model Foundation
 Depletion Capacitance Discussion

 EIA-656 ANSI RATIFICATION
 Patti Rusher has been pushing EIA-656 ratification as an ANSI standard.
 She still expects a 1995 date on the ANSI Standard.  No further action
 is needed by the IBIS committee.

 EIA/IBIS 1996 MEMBERSHIP
 Patti Rusher will send out EIA/IBIS 1996 membership renewal forms in
 December. Annual membership is $500 per company.  Bob Ross indicated that
 for the purposes of meeting quorums existing memberships will be carried 
 through the end of January to give time for the membership fees to be paid.
 No additional golden parser fee is needed for those who have already purchased
 the source code of Version 2.1, and the same 50% discounts apply for those
 who have not purchased the source code.  Will Hobbs indicated that there
 are 22 parser licencees.

 WEB UPDATE (AND EIA)
 Patti Rusher reported that the Web page issue is still under discussion
 and is of concern to many groups.  Uniformity of content and security are
 issues, and EIA has hired a consultant to help out.  She is pushing hard for
 a resolution at the Monday, December 4 internal meeting.  Syed Huq needs to
 know what can be published.  Everything is in place to be copied.

 Jon Powell indicated he received copies of logo permission letters from
 10 companies.  This needs to be checked since Quad Design was not included.
 Jon will work with Syed Huq to provide the Logos in a common format (probably
 GIF) so that a collage of logos can be created by pointers.  We also 
 discussed the possibility of linking the logos to their respective 
 companies' home pages.

 Unless the EIA web issues are resolved, further discussion on web plans
 including the possibility of setting up one separately on vhdl.org will
 occur at the next meeting.

 USERS' GROUP
 Bob Ross reported that the IBIS USERS' GROUP reflector [email-masked]
 is active.  No real activity has occurred to date, but discussion issues
 are expected.  Over 240 members are in this and the [email-masked] groups.
 No membership breakdown is available.  Many countries are represented.

 Also there is a new "wip" directory for work in progress under /pub/ibis
 on vhdl.org to be used for temporarily storing working documents.  Currently
 a draft of Version 3.0 exists which includes approved BIRD28.3 and BIRD30.2.

 FACE TO FACE MEETING
 Syed Huq has made arrangements for National to host the meeting on Monday,
 January 29 before SuperCon96.  He has scheduled a room, equipment and food.
 He is planning for about 35-40.  This meeting will be focused on technical
 discussions.  A group dinner is planned to celebrate the standardization
 of IBIS.

 AR - Syed Huq post details on meeting and request an RSVP for planning 
 purposes.  [Done]

 Will Hobbs discussed devoting a portion of time to the modeling validation
 concerns that exist in semiconductor companies, particularly in relations
 to on-going production testing.  The problem is how to verify in the 
 testers that the components meet the predictions of the models - what to
 measure, how many points on a V/I curve are sufficient, etc.  Can and/or
 should IC vendors guarantee by test that the models accurately bracket
 the silicon characteristics?   Intel and National will participate in this,
 but other vendors are encouraged to give their experiences and concerns as
 well.

 Another important segment is to seek actual users of IBIS models and ask
 them to present their experiences and problems.  IBIS participants who
 are users or who have worked with users are encouraged to seek their
 participation.  Several members indicated that they will follow through
 on this.

 Syed Huq did a direct polling of roster members and found that 7 supported
 IBIS Version 2.1 and 7 supported Version 1.1.  His concern was that some
 Version 2.1 level models will not work properly at lower levels and 
 encouraged EDA Vendor Discussion of their IBIS Verison 2.1 plans.  Such
 a discussion can also be tied in with the general modeling issue discussion.

 People who have topics to present should summit them to Bob Ross, Syed Huq
 or Will Hobbs.  Bob, Syed and Will will coordinate the agenda.

 AR - Everyone solicit participation by IBIS Users.
 
 AR - Anyone who wants to present notify Bob, Syed or Will.
 
 MODEL USAGE TRACKING
 Will Hobbs mentioned Intel has IBIS models on their bulletin board, but
 is not aware of any usage tracking activities.  Syed Huq stated that
 National IBIS models are available from the external National Web site:

   //www.nationalsemi.com

 They are trying to find a way to track models usage.

 GOLDEN PARSER UPDATE
 Jon Powell created the executables for ibischk2, and Bob Ross put them
 on vhdl.org.  Will Hobbs has sent out the final version of source code.

 Several problems have been discovered by Bob Ross and Chris Rokusek which
 will require a revised bug-fix release.  Our intent is to capture all
 of the bugs and do an update in January.   These problems will be sent to
 Paul Munsey for review and a quote on fixing the problems.

 AR - Anyone finding Parser bugs submit them to Bob Ross.  Include a test
 case, if possible.

 So far the bugs are (1) not accepting multiple [Disclaimer] keywords,
 (2) giving an incorrect Warning message when metric unit multipliers
 are used for [Define Package Model] matrix entries, and (3) not detecting
 a syntax error for incorrect [Model] sub-parameters "Model_type=", 
 "Polarity=", and "Enable=".

 SPICE TO IBIS VERSION 2.1
 Bob Ross reported that he has submitted some bugs and enhancement requests
 on s2ibis-v2.091 (a Beta version).  Since this is a Beta version an update
 is expected.

 BIRD31 - Connector Models
 Bob Ross introduced BIRD31.  The primary aspects are that it relies on
 existing syntax and introduces no new keywords or sub-parameters.  It
 is a new section which will follow the Package Modeling Section in the 
 Specification.  The controversial aspect of this proposal is that 
 connectors would be split into two parts for each board.  They would
 be joined by Simulator specification which "mates" the models by 
 series concatenation.  

 Hank Herrman of AMP expressed concern that "mated models" representing
 connectors are not easily split, nor are they necessarily meaningful
 in a split mode, which represents unconnected connector.  So an alternative
 proposal will be a "mated connector model" by itself.  Dave Moxely suggested
 that Components which are for connector pins could be designated by a
 "mated model" keyword.

 The BIRD did not address cables, but one possiblility is that cables could 
 be represented by mated models as longer connectors.

 Hank also would like to see a parameter that specifies the bandwidth
 or minimum time response for which a connector is valid because models
 of increased complexity are needed for higher speed applications.

 Bob Ross will write up some of the discussion and carry this on the
 reflector and at the Face-to-Face Meeting.

 BIRD28.3+  PACKAGE MODEL ENHANCEMENT
 Stephen Peters has reviewed C. Kumar's extension and now sees the merits
 of adding a pin ordering file and Matrix name parameter for extending
 the package model.  Kumar reported that one benefit will be to call
 smaller matrices that are used often, for a more compact description.
 This would allow a more general set of coupling relationships.

 C. Kumar plans to submit to Will Hobbs a new BIRD on this.

 Another discussion included generalizing the loss model to include the
 G matrix, since it may become more factor in MCMs, package models,
 cables with dielectric losses.  This would take another BIRD.

 EGG8 - PHYSICAL PACKAGE DISCUSSION
 Bob Ross introduced the subject of EGG8 which would be a significant
 departure for just the IBIS I/O models scope.  Will Hobbs expressed the
 concern that one of the biggest modeling issues is how to describe MCMs
 and SIMM packages.  So this proposal is of great interest to the IBIS
 community and needs to be pursued.  A discussion at the next meeting 
 can be reserved for this issue.

 DCL RELATIONSHIP WITH IBIS
 Don Cottrell of CFI reported that Ron Christopher has identified areas where
 the Delay Calculation Language (DCL) and IBIS may be related.  DCL needs
 loading conditions for correct delays, and IBIS can be of help.  DCL focuses
 on delays within an MCM or Chip.

 He requested that someone on the IBIS committee be identified to work
 with him and the DCL community on any joint common ground issues and help
 generate possible proposals.  Stephen Peters voluteered to get involved
 and report back on progress.

 EGG6 - TTL and CMOS
 Chris Rokusek indicated that the efforts to distinguish technologies by
 the data itself suggested by Arpad Muranyi and others does not always work.
 His major concern is that to simulate the rising edge of a TTL model,
 it is voltage source driven, versus a current source driven for CMOS and
 pulldown characteristics.  ECL type structures are already differentiated
 by Model_type.  He will present his findings on the reflector to stimulate
 discussion an consideration of alternatives.

 DEPLETION CAPACITANCE
 Bob Ross indicated that the depletion capacitance issue which has been
 discussed in the past is ripe for an Egg to generate more discussion.  He
 plans to submit one.

 NEXT MEETING:
 It is set on Friday, December 15, 1995, and the following meeting is on
 Friday, January 12, 1996 after the Christmas and New Years Holidays.

 ==============================================================================
                                       NOTES
 
 IBIS CHAIR: Will Hobbs (503) 264-4369, Fax (503) 264-4210
             [email-masked]
             Server Chipset System Validation Manager, Intel Corp.
             2111 NE 28th M/S JF1-57, Hillsboro, OR 97124 USA
 
 VICE CHAIR: Jon Powell (805) 988-8250, Fax: (805) 988-8259
             [email-masked]
             1385 Del Norte Rd., Camarillo, CA 93010
 
 SECRETARY:  Bob Ross (503) 603-2523, fax (503) 639-3469
             [email-masked]
             10220 SW Nimbus Ave, K4, Portland, OR 97223
 
 The following email addresses are used:

   [email-masked]
       To join, change, or drop from either the IBIS Open Forum Reflector
       ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
       or both.  State your request.

   [email-masked]
       To obtain general information about IBIS, to ask specific questions
       for individual response, and to inquire about joining the EIA-IBIS
       Open Forum as a full Member.

   [email-masked]
       To send a message to the general IBIS Open Forum Reflector.  This
       is used mostly for IBIS Standardization business and future IBIS
       technical enhancements.

   [email-masked]
       To send a message to the IBIS Users' Group Reflector.  This is 
       used mostly for IBIS clarification, current modeling issues, and
       general user concerns.

 Check the pub/ibis directory on vhdl.org for more information on previous 
 discussions and results.  You can get on via ftp anonymous, "guest" login from 
 telnet or dial-in (415-335-0110), or send an email request to the automatic 
 archive server, [email-masked].
 
 "IBIS Spoken Here" placards are available from Jon Powell ([email-masked]) for 
 use at trade shows.
 ==============================================================================

---

From: Herrmann Hank <[email-masked]>
Date: Wed, 06 Dec 95 08:29:00 E

Bob,

First I want to congratulate you on spelling my name correctly.   That 
almost never happens.  Also, you have done an excellent job of capturing all 
the discussions that took place in the last meeting.

There are two points that I think were discussed that I did not see in the 
minutes.  Perhaps they were too small to include but I would like to clarify 
and confirm them.

First, I thought someone mentioned the desire to discuss connector modes at 
the Face-to-Face Meeting in January.  I wonder if anyone has any specific 
points they would like to discuss.  Since I am considering trying to attend, 
this could significantly influence my decision.  (Cross country trips for a 
one day meeting are not popular with me or my management.)

Second, when BIRD 31 was discussed, I recognized the need for many users to 
have unmated models to simulate "not-fully-populated busses".  They would 
not be used for such analyses as cables or I/O connectors when there is a 
complete interconnection.  While we do not routinely supply unmated models 
now, there is no reason that they could not be provided.  They would even be 
simpler than "part of the mated model" which the BIRD suggests.  What I 
recommend is that two types of connector models be defined.  First, mated 
models for most interconnection applications.  Second, unmated models that 
have no through connection for situations that demand simulations of 
 "not-fully-populated busses".

I hope these points are helpful to the forum.  I enjoyed participating with 
you all and look forward to future work together.

Regards,

Hank Herrmann
Technical Staff Member
AMP Incorporated, Electro-Magnetic Technology
M.S. 106-14
P.O. Box 3608
Harrisburg, PA 17105-3608

            Phone:  717-986-5534
                 FAX:  717-986-5643
   INTERNET:  [email-masked]

---

From: Herrmann Hank <[email-masked]>
Date: Wed, 06 Dec 95 10:43:00 E

Thank you for your observation and question.

My concept of "unmated" is that the model should be self-sufficient (i.e., 
work properly without extra 'patches and band aids' and have connections at 
one side only.   So it would look like this ...

     Board1--> conn_model (unmated)

There would be no additional load required outside of the model.

For SPICE type simulators there may have to be some standard DC path, or 
'assumed load' to enable an unmated connector model to function properly. 
 That would not likely be required by most models, however, because there 
would already be the necessary DC paths to satisfy SPICE within the model 
itself or the bus.  A standard load may be something that should be defined 
for stand-off type stacking connectors that are long relative to the models' 
minimum applicable edge rate.

At this point I have only proposed, for consideration, the concept of both 
mated and unmated connector models as opposed to a mated model with an 
interface connection such as is proposed in BIRD 31.  Many details need to 
be worked out until that is finally accomplished if the concept is 
acceptable to everyone.

Hope this is helpful.

Regards,

 Hank
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 ----------
From: cpk
To: amp03847
Subject: RE: IBIS MINUTES 12/01/95
Date: Wednesday, December 06, 1995 9:51AM

Clarification:

Does unmated mean that you assume some kind of load at the other end

Board1--> conn_model --> assumed load  (unmated)
Board1 -> conn_model->board2 - full model

Thanx
 - kumar