Subject: EGG9 and C_comp

From: Stephen Peters <[email-masked]>
Date: Mon, 11 Dec 1995 13:39:57 -0800

Hello Bob, and others:

    In your diagram in EGG9, you show C_comp and being in
parallel with Ct (the circuit representation of transit time).

         Pad  X------------------------|  DEVICE
                      |           |    |
                      |           |    |
                     ---         ---   +------
                  Ct ---  C_comp ---         
                      |           |
                      |           |
                      -------------
                      gnd        gnd

For the [TTgnd] case that is how I would draw it, but what about the 
[TTpwr] case?  I've always thought of C_comp as between the I/O
node and ground.  Could C_comp be also modeled between the pad and Vcc?
Does it make a difference (at least as far as our black box
representation goes)?  Just wondering.....

          Thanks,
          Stephen Peters
          Intel Corp.

---

From: [email-masked] ( Bob Ross)
Date: Mon, 11 Dec 95 17:30 PST

Arpad, Stephen and Jon and All:

My IBIS model diagram is in error since C_comp does go to 
ground in all cases.  However, for the purposes of Time response
simulation, the C_comp and/or Ct could go to any reference voltage.
The main idea is that both the [Gnd Clamp] and [Power Clamp] diodes may
independently contribute to stored charge effects.

The discussion that is taking place is showing the importance of 
understanding the details and assumptions of the Spice and IBIS models.
I do not think we are in technical disagreement.  I think the value and 
position of Rs or its effective value within tables can be important for 
properly handing the stored charge effects and time constants.  The
real concerns are: is the proposed approach accurate enough?, or what
alternative approach would be better - within the IBIS framework?  

Bob Ross,
Interconnectix, Inc.