Subject: IBIS Open Forum 1/6/95 Meeting Minutes

From: Derrick Duehren <[email-masked]>
Date: Fri, 13 Jan 95 10:35:07 PST

Text item: Text_1

Date:    Jan 13, 1995

From:    Will Hobbs (503) 696-4369, fax (503) 696-4210
         [email-masked]
         XTG Modeling Manager, Intel Corp., Chairperson, IBIS Open Forum
         Intel Corporation
         5200 NE Elam Young Pkwy, Hillsboro, Oregon 97124 USA
         and
         Derrick Duehren (503) 696-4299, fax (503) 696-4904
         [email-masked]
         Intel Program Manager

Subject: Minutes from IBIS Open Forum Meeting 1/6/95

To:
ARPA                          Randy Harr*
AT&T Global Info Systems      Dave Moxley
Anacad                        Steffen Rochel
Ansoft                        Henri Maramis
Atmel Corporation             Dan Terry
Cadence Design                Sandeep Khanna, C. Kumar*
Cadlab                        Ralf Bruning
Contec                        Dileep Divkar
Digital Equipment Corp.       Barry Katz
EIA                           Patty Rusher
High Design Technology        Michael Smith, Dr. Ing. Cosso
HP Palo Alto                  Tom Langdorf* 
HyperLynx                     Kellee Crisafulli*
IBM                           Jay Diepenbrock, Joseph Flanigan
IBM-Motorola alliance         Lynn Warriner*, John Burnett
INCASES                       Werner Rissiek, Olaf Rethmeier*
Integrated Silicon Systems    Eric Bracken
Intel Corporation             Stephen Peters*, Don Telian, Will Hobbs*
                              Arpad Muranyi*, Derrick Duehren*
Interconnectix, Inc.          Bob Ross*
Intergraph                    Ian Dodd, David Wiens, Walter Katz
IntuSoft                      Charles Hymowitz
Mentor Graphics               Ravender Goyal, Greg Doyle
Meta-Software                 Mei Wong, You-Pang Wei, John Sliney
MicroSim                      Arthur Wong
National Semiconductor        Syed Huq*
NEC                           Hiroshi Matsumoto
North Carolina State U.       Steve Lipa, Michael Steer
OptEM Engineering, Inc.       Benny Leveille, Ken Ehn
PC Ware                       Paul Munsey, Ron Neville*
Quad Design                   Jon Powell*
Quantic Labs                  Mike Ventham*
Racal-Redac                   John Berrie
Stree Co.                     Mon Seng(sp?)
Symmetry                      Martin Walker
Synopsys, Logic Modeling G.   Bill Lattin
Texas Instruments             Bob Ward*
Thomson-CSF/SCTF              Jean Lebrun
UniCAD Canada Ltd.            Stephen Lum
Zeelan Technology             George Opsahl, Hiro Moriyasu

CC:
Intel Corporation             Randy Wilhelm, Jerry Budelman,
                              Intel IBIS team

In the list above, attendees at the meeting are indicated by *.

Upcoming Meetings: The room and bridge numbers for future IBIS teleconferences 
are listed below:
     Date       Bridge Number    Reservation #
     TBD        (916) 356-9999   TBD 

All meetings are 8:00 AM to 10:00 AM PDT (16:00 to 18:00 UTC).  We try to have 
agendas out 7 days before each open forum and meeting minutes out within 7 days 
after.  When you call into the meeting, ask for the IBIS Open Forum hosted by 
Will Hobbs and give the reservation number.

NOTE: "AR" = Action Required.

------------------------------------------------------------------------------

Check-in, Intros, Announcements
New participant: Tom langdorf at Hewlett Packard at Palo Alto memory 
procurement.  He is converting the IBIS spec to an HP internal format.

The following correction was made to the 12/9/94 meeting minutes: 
Bob Ross pointed out that Paul Munsey attended the 12/9/94 meeting.

Will commented that IBIS is now being used as a means for system design groups 
to communicate buffer design needs to I/O buffer design engineers, establishing 
a 2-way conduit of information flow to converge on workable designs at both 
ends.

Will reported that there are now 10 paid subscribers to the 2.1 Golden Parser.

New Agenda Items: 
Status of new updates to the Golden Parser.

Press Updates: 
Derrick started the draft press release before the Christmas holidays and has 
updated the roster document for attachment.  Will submitted Derrick's draft to 
Intel's MarCom with no response.  Kellee volunteered to release the Press 
Release, but suggested that someone with a stronger relationship with some 
industry editors do it.  Kumar will check with Cadence's marketing group and 
respond to Will.  [update: Intel MarCom is involved, Cadence MarCom has offered 
to help]

AR Will/Derrick: Post press release to the reflector. [DONE]

AR Derrick: Check on EDN IBIS article status.  [DONE, It is scheduled to appear 
in the 3/16/95 issue of EDN magazine.  Derrick is also in contact with the 
editor to ensure he has the 2.1 press release as well.]

Progress toward enlisting new IC vendors
Derrick reported that Zeelan is planning to post a text message to vhdl.org 
advertising their IBIS model library.  Lynn Warriner reported that he is ready 
to post PowerPC IBIS models and asked about non-ftp methods of posting them.  
Derrick referred him to Mike Steer's instructions posted yesterday.  Mike 
Venthum asked if VLSI Technology is participating - No.  He will contact them to
see if they will get involved, and post their ASIC IBIS models.

Golden Parser 2.1 progress and release date
Ron reported that the original 2.0 work is done and he will distribute a disk on
Monday.  There are 4 minor changes to be done.  Ron and Paul will provide an 
estimate to Will, approval of the work will be done via the reflector. {Update: 
The disk has been distributed.]

AR Ron/Paul:  Post an estimate of the work to be done to the reflector.

Who are the simulator vendors that can support v2.1 and when will this support 
be available? - S. Huq
Kellee thinks support will gradually trickle out in the coming months.  Several 
EDA vendors shared their roll-out plans off record.

Two models from Intel (under NDA) are the only two test models available.  
Simulator vendors can contact Syed Huq ([email-masked]) for National's 2.1 
models that are being verified now.

Compliance
Will pointed out that the V/T table can be used to as a type of compliance 
test/sanity check.  Kumar would like to see a DC check as well.

AR Kumar: Post an EGG for DC checking.

Status of EIA affiliation
Will reported that he attempted to get Patty Rusher of the EIG (Electronic 
Information Group of the EIA) to join us today.  Randy Harr said from his 
experience, we need to send the spec, a description of our balloting method, 
list of who voted on the final spec, and a transfer of copyright to the EIA.  
They mail the ballot document and the document out, for 60 day ballot time.

Once affiliated, we can make the spec available on-line as well as printed.  
There can be a fee for the printed copy to cover production and  EIA to 
distribution costs.  As an example, EIA 567 will be freely available on-line.

The balloting process costs about $1,000 per ballot.  If changes are needed 
after the first ballot, it'll cost anther $1,000.

Kellee suggests allowing open, free participation, but limiting votes to paid 
members.  Paid members can have the parser code as a benefit.  1 vote per 
company (EIA rule).  Kellee would like to distribute the spec with the models 
they distribute.

AR Derrick/Will: Post draft operating procedure, copyright ownership, membership
costs, benefits, and structure.

FYI, Ron Werner of Motorola heads the Design Automation Division of EIA.

Rev 2.1 Fallout
The following items need to be updated to support/reflect the updated spec.  
Will has no bandwidth to work on these.  Kellee suggested that if any of the EDA
vendors are writing manuals that include an appendix on how to create IBIS 
models, they could offer it to the forum (silence).  
  o Overview.  Will suggests that someone could write an article on 2.1, retain 
the copyright, and provide chunks for updating the Overview.
  o Cookbook
  o S2IBIS 2.1.  Kumar reported that Cadence is working with and funding NCSU to
update the utility.  The updated conversion utility should be available in about
three months.  Kumar said anyone can work with them on it.  Cadence is providing
some funding because it serves their interests.

IBIS General Session/Summit (face-to-face)
Derrick had 14.5 responses, he rated the responses for dates and places, and 
found 2/6 and Santa Clara were best. 

  Location: Santa Clara (Intel Robert Noyce Building, 
                        5-story building at 2200 Mission College Blvd.
                        Visitor parking is to the right of the main entrance.)

            Intel-recommended hotels:
              The Westin Hotel
              Santa Clara Marriott
              Biltmore Hotel & Suites
              Residence Inn by Marriott
              Sunnyvale Hilton

  Date:     2/6/95

  Time:     9:30 am - 5:00 pm  (If you come early, you can tour the Intel 
                               museum on your own.  Allow about 30 min.
                               Enter the museum from the main lobby.)

  Focus:    What people are doing with IBIS, technically as well as 
            politically, brainstorming, future direction (3.0 possibilities), 
            and relationship building.

            Kumar suggested discussing series termination.
            Stephen wants to discuss alternative packaging representations.
            Will and Jon suggested diode storage effects.

AR All -- Send agenda items and requests for time to Derrick and Will 
          by 1/27/95.

AR All -- Send a request to Derrick with your fax number if you want a map.

Wrap-up, Next Meeting Plans
Our next meeting is 1/27/95.  

AR Will -- Ask Patty Rusher to attend the meeting.  Also ask Intel's 
Architecture Design Lab personnel to discuss their interest in diode storage 
effects.

==============================================================================
                                      NOTES
If you know of someone new who wants to join the e-mail reflector 
([email-masked]), send e-mail to [email-masked].

Check the pub/ibis directory on vhdl.org for more information on previous 
discussions and results.  You can get on via ftp anonymous, "guest" login from 
telnet or dial-in (415-335-0110), or send an email request to the automatic 
archive server, [email-masked].
==============================================================================

---

From: Arpad Muranyi <[email-masked]>
Date: Mon, 16 Jan 95 08:32:19 PST

Text item: Text_1

Hello IBIS gurus,

In the last minutes Kumar suggested DC checking (see quote below).  I am not 
sure what he means, but just as we can use V-T tables for AC checking, couldn't 
the I-V curves be used for DC checking?

Arpad
Intel Corporation

> AR Kumar: Post an EGG for DC checking.

Text item: External Message Header

The following mail header is for administrative use
and may be ignored unless there are problems.

***IF THERE ARE PROBLEMS SAVE THESE HEADERS***.

Subject: IBIS Open Forum 1/6/95 Meeting Minutes
To: [email-masked], [email-masked],
        [email-masked], [email-masked]
From: Derrick Duehren <[email-masked]>
Date: Fri, 13 Jan 95 10:35:07 PST

---

From: Will Hobbs <[email-masked]>
Date: Mon, 16 Jan 95 11:56:15 PST

Text item: Text_1

Arpad,

This was suggested at the meeting.  Since we felt Kumar may have meant something
else that we didn't grasp when he said it, we asked him to generate an EGG to 
clarify it and generate discussion.

Will
Intel Corp.

Hello IBIS gurus,

Arpad
Intel Corporation

Subject: Re: IBIS Open Forum 1/6/95 Meeting Minutes
To: [email-masked]
From: Arpad Muranyi <[email-masked]>
Date: Mon, 16 Jan 95 08:32:19 PST

---

From: [email-masked] (C. Kumar)
Date: Tue, 17 Jan 95 09:55:15 -0500

The problem with I-V checking is that there is no  "standard" load as 
with V-T curves. We already went through this i-v standard load  discussion 
and dropped it because
of controvorsey. The reason I raised it because that I think that in 
signal integrity situations the dc I-V characteristic has more has a dominant 
effect on the resulting waveforms and we have no reference to check against.

> Message-Id: <[email-masked]>
> Received: by ccm.hf.intel.com (ccmgate 3.0) Fri, 13 Jan 95 10:35:07 PST
> Received: from ccm.hf.intel.com by relay.jf.intel.com
> 	(Smail3.1.28.1 #2) id m0rSqq5-000twhC; Fri, 13 Jan 95 10:35 PST
> Received: from relay.jf.intel.com by ormail.intel.com with smtp
> 	(Smail3.1.28.1 #7) id m0rSqq7-000Ug3C; Fri, 13 Jan 95 10:35 PST
> Received: from ormail.intel.com by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet)
> 	id AA09335; Fri, 13 Jan 95 10:40:26 PST
> Received: from vhdl.vhdl.org by hermes.intel.com (5.65/10.0i); Fri, 13 Jan 95 10
> Received: from hermes.intel.com by relay.jf.intel.com with smtp
> 	(Smail3.1.28.1 #2) id m0rSrDN-000twfC; Fri, 13 Jan 95 10:59 PST
>

---

From: Arpad Muranyi <[email-masked]>
Date: Tue, 17 Jan 95 10:43:13 PST

Text item: 

Kumar,

I am still not sure what you mean by "standard load".  When you do a voltage 
sweep on a device, you are forcing the voltage while you are measuring the 
current.  When yo do this sweep, you are actually "loading" the device with the 
voltage source.  You can look at that voltage source as an ideal, 0 Ohm source 
or as a Thevenin combination of an ideal source with a series resistor.  Either 
way, you are sweeping between a certain voltage range at the output of the 
device to get an I-V curve, regardless of what R is in your Thevenin circuit.  
Your I-V curve will be the same whether R in the Thevenin circuit is small or 
large.  You will just have to increase the sweep range of the voltage source 
inside the Thevenin circuit for larger R values to get the same sweep range at 
the pin of the device.

What is the probelem?  Am I missing something obvious?

Arpad

Subject: Re: IBIS Open Forum 1/6/95 Meeting Minutes
To: [email-masked], [email-masked]
From: [email-masked] (C. Kumar)
Date: Tue, 17 Jan 95 09:55:15 -0500

---

From: [email-masked] (C. Kumar)
Date: Tue, 17 Jan 95 14:04:03 -0500

By standard load, I waa trying to indicate the following.

The ac v-t specifications include loads under whcih the measurements were taken.
So if the siumulations reproduce the v-t behavior at those load conditions then
they are self verifying and are pracically meaningful.

For a practically meaningful v-i verification, we have to drive a reference load with the
device and then compare the resulting v-t with some reference waveform. What is a useful refernce load. Is it daisy chain transmission line with ten loads? Or is it a simple capacitor? In the past we have been unable to come to agreement on identifying both the reference load and waveforms.  

This is what I meant by refernce loads for v-i verification. 
> Message-Id: <9501171455.AA14781@hot>
> Received: by hot (5.65+/1.5)
> 	id AA14781; Tue, 17 Jan 95 09:55:15 -0500
> Received: from hot by cadence.Cadence.COM (5.61/3.14)
> 	id AA05113; Tue, 17 Jan 95 06:54:58 -0800
> Received: from cadence.cadence.com(158.140.18.1) by mailgate.cadence.com via sma
> 	id sma028434; Tue Jan 17 06:55:24 1995
> Received: (from smap@localhost) by mailgate.Cadence.COM (8.6.8/8.6.8) id GAA2844
> Received: from mailgate.Cadence.COM by vhdl.vhdl.org (4.1/SMI-4.1/BARRNet)
> 	id AA29044; Tue, 17 Jan 95 07:00:29 PST
> Received: from vhdl.vhdl.org by aurora.intel.com (5.65/10.0i); Tue, 17 Jan 95 07
> Received: from aurora.intel.com by relay.jf.intel.com with smtp
> 	(Smail3.1.28.1 #2) id m0rUFcT-000tweC; Tue, 17 Jan 95 07:14 PST
>

---

From: Arpad Muranyi <[email-masked]>
Date: Tue, 17 Jan 95 16:26:01 PST

Text item: 

Kumar,

Now I am starting to understand your thought process.  However, I don't agree 
with your suggestion, quote: "For a practically meaningful v-i verification... 
...compare the resulting v-t with some reference waveform".

If you are trying to verify the I-V curve, don't use waveforms, because the 
waveforms are not directly effected by the I-V curve.  Waveforms are dependent 
on rise/fall times, transmission line models (lossy or lossless), T-line length,
load capacitances, etc...  None of which have much to do with DC.  The only 
thing you can do to verify an I-V curve is to look at the ledge voltage (if you 
have a distinct one) of a waveform.  However, you can get the same ledge voltage
with a pure resistor as the load (if its value represents your loading 
impedance).  Once you are at this point, you might as well just match the I-V 
curve to a known Referece I-V curve, and be done.

Arpad

The ac v-t specifications include loads under whcih the measurements
were taken.
So if the siumulations reproduce the v-t behavior at those load conditions
then
they are self verifying and are pracically meaningful.

For a practically meaningful v-i verification, we have to drive a
reference load with the
device and then compare the resulting v-t with some reference waveform.
What is a useful refernce load. Is it daisy chain transmission line
with ten loads? Or is it a simple capacitor? In the past we have been
unable to come to agreement on identifying both the reference load
and waveforms.

Subject: Re: Re[2]: IBIS Open Forum 1/6/95 Meeting Minutes
To: [email-masked], [email-masked]
From: [email-masked] (C. Kumar)
Date: Tue, 17 Jan 95 14:04:03 -0500