Subject: IBIS and SSO

From: [email-masked] (Dileep Divekar)
Date: Wed, 1 Mar 1995 14:05:25 +0800

I have been reading the discussion about using
IBIS models for modeling simultaneous switching noise (SSN).
When the outputs are transitioning, the current thru
supply or ground leads causes a voltage drop in the
corresponding inductors, giving rise to SSN.
IBIS provides information about these parasitic inductors.
But based on my limited understanding of IBIS models,
they do not provide information as to the supply and
ground currents for each buffer when it is making a
transition. These currents will be different from
the dc I-V information provided for the output stage.
Perhaps some one who knows more about the IBIS specification
can provide a pointer to that information if it is already
available in the present IBIS specification.
Thanks.
------------------------------------------------------------
Dileep Divekar
Contec Microelectronics
2188 Bering Drive
San Jose, CA 95131

Phone - (408)-434-6767 x 126
Fax   - (408)-434-6884
Email - [email-masked]
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From: [email-masked] (Jon Powell)
Date: Wed, 1 Mar 95 17:07:24 PST

>available in the present IBIS specification.

There are, of course, different levels of accuracy, but the 2.1 IBIS
spec (with AC waveforms and pin connection maps) does give enough data
to model much of the risetime effects and current starvation effects of SSO
on output devices. There is more information that we could add to increase the
accuracy but in general I think you quickly get to a point where the most important
issues become sub nano-second skew time between drivers and the actual physical description of
the  power routes which are not attainable in the IBIS level of information (and probably,
to the common customer, not at all in any format ever).

So it behoves us to make a good guess. (sorry, engineering approximation)

jonp