Subject: Minutes from EIA IBIS Meeting 4/7/95

From: Derrick Duehren <[email-masked]>
Date: Thu, 13 Apr 95 16:00:40 PST

DATE:    April 13, 1995

FROM:    Will Hobbs (503) 264-4369, fax (503) 264-4210
         [email-masked]
         Modeling Manager, Intel Corp., Chairperson, EIA IBIS Open Forum
         5200 NE Elam Young Pkwy, Hillsboro, OR 97124 USA
         and
         Derrick Duehren (503) 264-4299, fax (503) 264-4904
         [email-masked]
         Intel Program Manager, IBIS Secretary

SUBJECT: Minutes from EIA IBIS Open Forum Meeting 4/7/95

PARTICIPANTS:
ARPA                          Randy Harr
AT&T Global Info Solutions    Dave Moxley*
Anacad                        Steffen Rochel
Ansoft                        Henri Maramis
Atmel Corporation             Dan Terry
Cadence Design                Sandeep Khanna, C. Kumar*
Cadlab                        Ralf Bruning
Contec [M]                    Dileep Divekar*
Digital Equipment Corp.       Barry Katz
EIA                           Patty Rusher
High Design Technology        Michael Smith, Dr. Ing. Cosso
HP Palo Alto                  Tom Langdorf
HP EESof                      Karl Kachigan, Henry Wu
HyperLynx [M]                 Kellee Crisafulli*
IBM                           Jay Diepenbrock, Joseph Flanigan
IBM-Motorola alliance         Lynn Warriner, John Burnett
INCASES [M]                   Werner Rissiek, Olaf Rethmeier*
Integrated Silicon Systems    Eric Bracken
Intel Corporation             Stephen Peters*, Don Telian, Will Hobbs*
                              Arpad Muranyi*, Derrick Duehren*, Tim Schreyer
Interconnectix, Inc. [M]      Bob Ross*
Intergraph                    Ian Dodd, David Wiens, Walter Katz
IntuSoft                      Charles Hymowitz
Mentor Graphics               Ravender Goyal, Greg Doyle
Meta-Software                 Mei Wong, You-Pang Wei, John Sliney
MicroSim                      Arthur Wong
National Semiconductor [M]    Syed Huq, Raj Raghuraum, Atul Agarwal
NEC [M]                       Hiroshi Matsumoto
North Carolina State U.       Steve Lipa, Michael Steer
OptEM Engineering, Inc.       Benny Leveille, Ken Ehn
Pacific Numerix               Paul K. U. Wang
Quad Design                   Jon Powell*
Quantic Labs [M]              Mike Ventham
Symmetry                      Martin Walker
Synopsys, Logic Modeling G.   Bill Lattin
Texas Instruments [M]         Bob Ward
Thomson-CSF/SCTF [M]          Jean Lebrun
UniCAD Canada Ltd.            Stephen Lum
Zuken-Redac [M]               John Berrie
Zeelan Technology             George Opsahl, Hiro Moriyasu

In the list above, attendees at the meeting are indicated by *.  Voting members 
are indicated by [M].

Upcoming Meetings: The bridge numbers for future IBIS teleconferences are as 
follows:
     Date       Bridge Number    Reservation #
     5/5/95    (916) 356-9999    461609
     5/26/95   (916) 356-9999    485256 

All meetings are 8:00 AM to 10:00 AM Pacific Time.  We try to have agendas out 
7 days before each open forum and meeting minutes out within 7 days after.  
When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
Hobbs and give the reservation number.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------

CHECK-IN, INTROS, ANNOUNCEMENTS
There were no corrections made to last month's minutes.
New participant: David Johnson ([email-masked]), of Micron 
Technology, applications engineering.  Micron Technology is supplying Spice 
models to customers and wants to send IBIS models instead for greater accuracy 
and so they don't have to worry about intellectual property issues.

AR Derrick -- Publish an explanation of how to join the EIA IBIS group. [Done 
-- below]

  To become a voting member of the forum, send $500 annual dues to:
    EIA/Electronic Information Group
    c/o Patti Rusher
    2500 Wilson Blvd.
    Arlington, VA 22201
    (703) 907-7545  Fax: (703) 907-7501
    Email: [email-masked]

  The source code to the Golden Parser is available for $500 (or $250 for 
  voting members).  Send requests for the parser to Patti Rusher.

EIA IBIS MEMBERSHIP UPDATE:
The following companies have become voting members of the EIA IBIS Open Forum.
Contec Microelectronics         $750.00 (licensed parser)
HyperLynx                       $250.00 (licensed parser)
INCASES Engineering GmbH        $250.00 (licensed parser)
Interconnectix                  $250.00 (licensed parser)
National Semiconductor          $250.00 (licensed parser)
NEC Corporation                 $500.00 
Quantic Labs                    $250.00 (licensed parser)
Texas Instruments               $500.00 
Thomson-CSF                     $0 (DAD Member)
Zuken-Redac                     $500.00 

Intel appears to have lost its membership letter.  Pattie is sending a 
replacement.

FYI: The IBIS ANSI Project Number is 3527.  That will also be its Standards 
Proposal number.

NEW AGENDA ITEMS: 
None.

PRESS UPDATES: 
The March 16 EDN Magazine has a feature article on IBIS by Derrick, Will, 
Arpad, and Robin Rosenbaum.

NEW MODELS AVAILABLE:
Arpad will be posting some models soon.  

Micron Technology has some preliminary IBIS models for 32-bit cache SRAMs for 
Pentium(R) processors that they are willing to post.  David Johnson will work 
with Kellee and Bob Ross to get his files checked and posted to vhdl.org.  

PROGRESS TOWARD ENLISTING NEW IC VENDORS
Will has been getting three times the requests on ibis-info since the EDN 
article came out.

GOLDEN PARSER 2.1 PROGRESS AND RELEASE DATE
Stephen reported a GP error with N/As in the typ. column.  

GP Release date:  Will recommended that we release the GP `now' (with know bugs 
fixed), rather than continuing to do turns.  

Paul Munsey was not available to comment.

AR Arpad -- Contact Paul, determine status of the release, and post it to the 
reflector.  [Update: Paul and Ron want another beta with all previously 
paid-for fixes incorporated.  After verification, they will add the subsequent 
changes, such as case and ^M.]

EIA AFFILIATION STATUS
Eight companies have joined the EIA IBIS subcommittee (10 as of 4/12/95).  We 
decided to allow Design Automation Div. members to waive the $500 dues.  They 
will get the same discount on purchasing the GP source code as other paid 
members.  Derrick pointed out that the Design Automation Div., as our parent 
organization, insures our finances, so it's not such a bad deal.  

We need a Press Release announcing our EIA affiliation and Spec balloting.

Derrick is putting the boilerplate fluff around the spec so it meets the EIA's 
voting standards, due 4/10 to Pattie Rusher [Done 4/13/95], with an expected 
quick turnaround for balloting.

AR Derrick -- Talk to Pattie Rusher.  [Done]
o Clarify DAD parser licensing ($250), non-member GP licensing ($500), and the 
  fee for DAD membership.  [DAD membership is $1,000 - $15,000 
  depending on size of company.] 

o Clarify process/schedule for the vote on IBIS 2.1 Spec.  [Spec will go 
  out for ballot about 1 week after Pattie receives the "fluffed" spec from 
  Derrick.  We will need to decide how we will process responses/change 
  requests.  Do we need a subcommittee?]

o Inform her of the need for a Press Release.  [Pattie will do.]]

o Does EIA have a WWW home page?  We'd like to have one.  [YES.  Contact 
  Cecilia Fleming (703) 907-7554, [email-masked].]

o Best way to roll in our passed BIRDs into the election.  Should we ballot 
  on a Version 2.2?  [Pattie recommends keeping it as 2.1 with erratta calling 
  out the updates.  Derrick will implement this in his "fluffed": spec.]

PLANS FOR IBIS MEETING AT DAC (JUNE 2ND - 16TH)
We will have a face-to-face meeting at DAC to elect officers and conduct other 
business Thurs. 6/15/95, 8:30 - 1:00.

Jon has drafted an "IBIS Spoken Here" placard.  He asked for feedback on how 
fancy they should be.  Consensus was something in the $25 range (8.5" x 11" on 
foamboard backing).  Each participant will pay for their own placard.  Kellee 
wants to use the placard design at WinEDA.

AR Jon -- Send placard file to Derrick for posting to vhdl.org. 

Birds of Feather.  Jon Powell will put together a BOF poster following the same 
motif as the placards.  He also volunteered to present some overview foils (30 
min.) to get the BOF conversation going.

AR Jon -- Sign us up for a BOF session and prepare the foils. 

REV 2.1 UPDATES
o S2IBIS 2.1  No discussion.

o Cookbook    Kelley and Bob Ross have done very little, but expect to 
              work on it in the coming weeks.

o Overview    No discussion.

SGML/HTML SUPPORT?
Syed was not present to comment, although we briefly discussed our desire to 
have a WWW home page.  Derrick will follow up with Pattie Rusher.

BIRD 26 - TAB CHARACTERS DISCOURAGED IN .IBS FILES
Vote taken, BIRD 26 APPROVED UNANIMOUSLY. (Unofficially, since only 4 
`official' membership companies were present -- we need 5.  We will reconfirm 
at the next meeting when more companies have officially joined the EIA IBIS 
subcommittee.)

BIRD 27 - NEW KEYWORD FOR DIFFERENTIAL I/O
BIRD 27 adds a capability that is already there.  It is a convenience only.  
The forum agrees that we should not add things just for convenience and 
recommends not approving BIRD 27 at this point.

DIODE TRANSIT TIMES
Tim Schreyer will attend the next meeting to discuss this topic.

ENHANCEMENT TO THE TIMING SPEC
Stephen lead a discussion on how to model packages with transmission line 
effects.  Two ways proposed:  Stephen suggested we use the existing matrix 
methodology with extensions, and Kellee suggested using a PCB type of 
description.

Kellee suggested allowing bonding pad to board rlc and board to pin rlc for 
bonding wires and PCB description for the in-package board.  Jon said that many 
off-shore ASIC vendors hand draw the circuit boards, so there is no path in 
those cases for getting this data.  Jon does like the PCB description because 
it improves the ability to discern crosstalk between the traces and wires, etc.

MCMs, SIMMs, complex packages, multi-cavity packages, hybrids, etc. can all be 
described with PCB approach.  This may be revealing proprietary info, and 
eliminates level 1 modeling capability in those cases.

Some had concerns that many semiconductor companies won't be willing to put 
this level of package details in the models.  After a lengthy discussion, we 
acknowledged that the existing capabilities in the spec are better than 
nothing.  Kellee wants to keep the number of new descriptions to a minimum, 
since we already have 3 descriptions. (single rlc, rlc per pin, rlgc).  The 
question is, do we need 2 additional descriptions (1. transmission line segment 
description or coupled rlgc matrix  2. full PCB description.) or will one 
additional description suffice? 

Any vendor that would like to experiment with Intel's complex package models, 
send a request to [email-masked] (Jon, Kellee, Bob R.).

AR Derrick/Stephen: Send the complex package models to Jon, Kellee, Bob R. 
[Done]

David J. informed us that a Jedec package measurement spec (JCB-95-10) is being 
voted on now that may give us some ideas. 

AR Stephen -- Evaluate the Jedec proposal.

WRAP-UP, NEXT MEETING PLANS
Our next meeting is a teleconference 5/5/95 (pushed out one week due to WinEDA 
and other events that week). 

==============================================================================
                                      NOTES
To become a voting member of the EIA IBIS Open Forum, send email to 
[email-masked] for instructions.

If you want to join the e-mail reflector ([email-masked]), send e-mail to the 
IBIS secretary at [email-masked].

Check the pub/ibis directory on vhdl.org for more information on previous 
discussions and results.  You can get on via ftp anonymous, "guest" login from 
telnet or dial-in (415-335-0110), or send an email request to the automatic 
archive server, [email-masked].
==============================================================================

---

From: [email-masked] (C. Kumar)
Date: Fri, 14 Apr 95 09:51:46 -0400

> From [email-masked] Thu Apr 13 19:12:06 1995
> Return-Path: <[email-masked]>
> From: Derrick Duehren <[email-masked]>
> To: [email-masked]
> Subject: Minutes from EIA IBIS Meeting 4/7/95
> Content-Length: 12025
> X-Lines: 289
> 

> additional description suffice? 
A transmission line description is a rlgc description plus length. The only difference between lumped RLGC and transmission line RLGC is the RLGC in transmission line are per unit length parameters. RLGC per unit length + length of the transmission line is a complete description.