Subject: IBIS PARSER ENHANCEMENT BUG REPORTS

From: [email-masked] ( Bob Ross)
Date: Wed, 6 Nov 96 16:40 PST

Hello:

As part of the ibischk parser enhancement discussions, Chris Rokusek has
formally filed the BUG REPORT forms showing the proposed changes.  I have
concatenated the three BUG REPORTs for background related to the IBIS
meeting discussion on this subject this Friday.  The reports are also
filed on vhdl.org under /pub/ibis/bugs.

Bob Ross
Interconnectix

******************************************************************************
********************* IBIS GOLDEN PARSER BUG REPORT FORM *********************
******************************************************************************

INSTRUCTIONS

To report a bug in the IBIS golden parser.  Please fill out the top part
of the following form and send the complete form to [email-masked].

A list of reported bugs will be maintained on vhdl.org.

******************************************************************************

PARSER VERSION NUMBER: 2.1

PLATFORM (SPARC, HP700, PC, etc.): ALL

OS AND VERSION: ALL

REPORTED BY: Chris Rokusek, Quad Design

DATE: 961105

DESCRIPTION OF BUG: Additional value checking

For the following parameters print a warning if they value exceeds the
limit.

     Ramp Times   1 ms 

     R_pkg        1 k
     R_pin        1 k

     L_pkg        1 uH
     L_pin        1 uH

     C_pkg        1 nF
     C_pin        1 nF

     C_comp       1 nF

INSERT IBIS FILE DEMONSTRATING THE BUG:

[IBIS Ver]      2.1
[File name]     big_rlc.ibs
[File Rev]      2.0
|
[Component]     p54c
[Manufacturer]  fake
[Package]
|
|               typ             min             max
R_pkg 1002 1001 1003
L_pkg 1.2E-06 1.1u 1.3E-06
C_pkg 1.2E-09 1.1n 1.1n
|
|------------------------------------------------------------------
|
[Pin]   signal_name     model_name      R_pin   L_pin   C_pin  
|               
1       sig1 fake_out 1005 1.4u 1.3n
2       sig2 fake_out 999  .99u  .99n
3       sig3 fake_out 1008 1.4E-06 1.3E-09
|
[Model]         fake_out
Model_type      Output
Vinh = 2.0V
Vinl = 0.8V
|               typ             min             max
C_comp          1.01nF          1.02nF          1.03nF
|
|                       typ     min     max
[Voltage range]         5.0 4.0 6.0
|
|
[Pulldown]
|       voltage         I(typ)          I(min)          I(max)
        0.0             0.0             0.0             0.0
        3.3V            1mA .5mA 2mA
[Pullup]
|       voltage         I(typ)          I(min)          I(max)
        0.0             0.0             0.0             0.0
        3.3V            -1mA  -.5mA -2mA
|               
|Ramp data
[Ramp]
|               typ             min             max
|
dV/dt_r         3/1.1m  3/1.2   3/1.3
dV/dt_f         3/1.4m  3/1.5   3/1.6
|
|
[end]

******************************************************************************
******************** BELOW FOR ADMINISTRATION AND TRACKING *******************
******************************************************************************

BUG NUMBER: 5

SEVERITY: [FATAL, SEVERE, MODERATE, ANNOYING, ENHANCEMENT]  ENHANCEMENT

PRIORITY: [HIGH, MEDIUM, LOW]                               MEDIUM

STATUS: [OPEN, CLOSED, WILL NOT FIX, NOT A BUG]             OPEN

FIXED VERSION:

FIXED DATE:

NOTES ON BUG FIX:

******************************************************************************
******************************************************************************

******************************************************************************
********************* IBIS GOLDEN PARSER BUG REPORT FORM *********************
******************************************************************************

INSTRUCTIONS

To report a bug in the IBIS golden parser.  Please fill out the top part
of the following form and send the complete form to [email-masked].

A list of reported bugs will be maintained on vhdl.org.

******************************************************************************

PARSER VERSION NUMBER: 2.1

PLATFORM (SPARC, HP700, PC, etc.): ALL

OS AND VERSION: ALL

REPORTED BY: Chris Rokusek, Quad Design

DATE: 961105

DESCRIPTION OF BUG: Output control

Added control where ouput is going rather than stdout.
Providing ability to re-direct output to a specified file handle.
Default file handle would be 'stdout' to retain backward compatability
and not require use of the added function.

Please contact me for a new (cleanly) modified errlog.c, [email-masked]

INSERT IBIS FILE DEMONSTRATING THE BUG:

******************************************************************************
******************** BELOW FOR ADMINISTRATION AND TRACKING *******************
******************************************************************************

BUG NUMBER:  6

SEVERITY: [FATAL, SEVERE, MODERATE, ANNOYING, ENHANCEMENT]  ENHANCEMENT

PRIORITY: [HIGH, MEDIUM, LOW]                               LOW

STATUS: [OPEN, CLOSED, WILL NOT FIX, NOT A BUG]             OPEN

FIXED VERSION:

FIXED DATE:

NOTES ON BUG FIX:

******************************************************************************
******************************************************************************

******************************************************************************
********************* IBIS GOLDEN PARSER BUG REPORT FORM *********************
******************************************************************************

INSTRUCTIONS

To report a bug in the IBIS golden parser.  Please fill out the top part
of the following form and send the complete form to [email-masked].

A list of reported bugs will be maintained on vhdl.org.

******************************************************************************

PARSER VERSION NUMBER: 2.1

PLATFORM (SPARC, HP700, PC, etc.): ALL

OS AND VERSION: ALL

REPORTED BY: Chris Rokusek, Quad Design ([email-masked])

DATE: 961105

DESCRIPTION OF BUG: Check of VI curves against waveforms

   This check would look at the beginning and ending voltages of a VT
   Waveform which indicate DC settling points and compare each of these
   voltages to the given DC VI curves using the load specified for the 
   waveform data.

   For example, given...

     [Rising Waveform]
     R_fixture = 50
     V_fixture = 2.5
     C_fixture = 50.0pF  /* not important for this test */

   ...and a waveform like...

         +V

          |
          |
          |
    4.2V  |                      ********
          |                   ****      |
          |                  *          |
          |  first point    *           |
          |    |           *            |
    2.5V  |    |           *            |
          |    |          *        last point
          |    V          *
          |              *
    0.5V  |    **********
          |
          |
          ------------------------------------- +Time

   Can use the first point (see above) at 0.5V to check against the
   low VI curve (see below)...

        +I

         |                      Low State VI Curve
         |                           |
         |                           V
         |    x               LLLLLLLLLLLLLLLLLLLL
         |     x       LLLLLLL
         |      x   LLL
         |       xLL
         |     LLvx
         |    L  v x
         |   L   v  x
         |  L    v   x
         | L     v    x
         |L      v     x  <--- slope = -50.0 = R_fixture
         |L      v      x
         L       v       x   _------ Voltage = V_fixture
         L       v        x /
     ----L-------v---------x----------------------  +V
        L|       |         |              |
       L
        0.0V    ?=?       2.5V           5.0V
               0.5V?

    The load line "xxxx" should intersect the low state VI curve "LLLL" 
    at ~= 0.5V indicated by the first point of the [Rising Waveform].

    Similarly, the High VI curve can be correlated to the last point
    of the Rising Waveform.  This should be repeated for all waveforms.

    ** Note that this check requires LOW curve = [PullDown] + [GND_Clamp].

   A percentage or some other type of tolerance (TO BE DETERMINED)
   will be defined as an example of a 2% tolerance for agreement...

   > > Example Waveform:
   > >
   > >    Begins: (0ns, 0.0V)
   > >    Ends:   (9ns, 4.0V)
   > >    Load:   50 Ohms, 0.0V
   > >
   > >
   > > For 2% agreement, the v_tolerance = 2% * (4.0 - 0) = .08V
   > >
   > >   So model passes if...
   > >
   > >       -0.08 < v_dc_low_for_load < 0.08
   > >
   > >                AND
   > >
   > >        3.92 < v_dc_high_for_load < 4.28
   > >

I ([email-masked]) have made changes or added additional modules as follows:

   Module    Did
   ------    ---

   ibis.c    Added call to acdc_CheckAllModels() within IBIS_Test()

   acdc.c    Added
   acdc.h    Added

   qry.c     Added
   qry.h     Added

   makefile  needs to be updated to include new modules
	     (will not provide as mine is make environment dependent).

INSERT IBIS FILE DEMONSTRATING THE BUG:

To be provided with code modules after percentage or other method is
determined.

******************************************************************************
******************** BELOW FOR ADMINISTRATION AND TRACKING *******************
******************************************************************************

BUG NUMBER:  7

SEVERITY: [FATAL, SEVERE, MODERATE, ANNOYING, ENHANCEMENT]  ENHANCEMENT

PRIORITY: [HIGH, MEDIUM, LOW]                               MEDIUM

STATUS: [OPEN, CLOSED, WILL NOT FIX, NOT A BUG]             OPEN

FIXED VERSION:

FIXED DATE:

NOTES ON BUG FIX:

******************************************************************************
******************************************************************************