Subject: [Fwd: s2ibis2 question?]

From: Huang <[email-masked]>
Date: Wed, 16 Oct 1996 21:49:51 +0800

Hi,

  Thank Mark and I have the following solution for my previous question
for s2ibis2.  I just post here for future reference.

Arthur

[email-masked] wrote:
> 
> Arthur,
> 
>       You have a little of both going on.  There is a way to the
> process more automatic AND the s2i file is incomplete.  You need to
> add termination to the TN and A nodes in the .sp file since s2ibis2
> does not always terminate them to a voltage source (avoid no dc path
> to ground and ensure the TN node is in it's proper state to generate
> the pullup/down).  The s2i file needs the [Model File] statement to
> know which process corner to use.  I copied your files, modified them
> and created .ibs files using s2ibis2.sparc and hspice.  See the
> attached modified .s2i, .sp and lib files.
> 
> Good luck
> 
> Mark Simpson
> 
> ------------   TEXT ATTACHMENT   --------
> SENT 10-14-96 FROM SIMPSON_MARK @ESP
> 
> ::::::::::::::
> bd4t.s2i
> ::::::::::::::
> | TEST IBIS characterization
> [IBIS Ver]      2.1
> [File rev]      1.0
> [Date]  Mon Oct 14 15:56:30 1996
> [Disclaimer]    for characterization purpose only
> [Spice type]    hspice
> | [Iterate]
> | [Cleanup]
> [Component]     bd4t
> [Manufacturer]  Arthur
> | [Package model]       pkg_type
> [Spice file]    bd4t.sp
> [Temperature range]     50      100     0
> [Voltage range]         3.3     3.0     3.6
> [R_pkg]                 1.0m    0.5m    1.5m
> [L_pkg]                 2.5nH   2.0nH   3.0nH
> [C_pkg]                 4.0pF   3.5pF   4.5pF
> | [Diff pin]
> | describe the differential pin list
> 
> | [Pin mapping]
> | currently just neglect this command
> 
> [Pin]
> A       A       s_A     A
> TN      TN      s_TN    TN
> IO      IO      s_IO    bd4t
> -> A TN
> VDD     vdd     s_p     POWER
> pGND    g       GND     GND
> 
> [Model] A
> [Model type]    Input
> [Polarity]      Non-Inverting
> [Model File]    proc.typ   proc.min   proc.max
> [Vinl]  0
> [Vinh]  3.3
> 
> [Model] TN
> [Model type]    Input
> [Polarity]      Non-Inverting
> [Model File]    proc.typ   proc.min   proc.max
> [Vinl]  0
> [Vinh]  3.3
> 
> [Model] bd4t
> [Model type]    I/O
> [Polarity]      Non-Inverting
> [Model File]    proc.typ   proc.min   proc.max
> [sim time]      10n
> [C_comp]        2.0pF   3.0pF   1.0pF
> [Rising waveform] 50 0 NA NA NA NA NA NA NA
> [Falling waveform] 50 3.3 NA NA NA NA NA NA NA
> [Vmeas]         1.5V
> [Cref]          10pf
> [Vref]          0V
> 
> ::::::::::::::
> bd4t.sp
> ::::::::::::::
> * input termination  (TN low if active high, TN high if active low)
> *RTN    TN      VDD     1E9
> RTN     TN      0       1E9
> RA      A       0       1E9
> 
> * testing spice deck for bd4t IBIS 2.1 model characterization
> 
> * change the following line to your library file
> *.inc 'junk.lib'
> .global vdd gnd vpp
> 
> xCKT A IO ZI TN bd4t
> 
> .subckt bd4t a io zi tn
> xnd1 a tn n1 nand
> xnd2 n1 tn n2 nand
> xiv1 n2 n3 inv
> mpio io n1 vdd vdd p w=60u l=1u m=1
> mnio io n3 gnd gnd n w=30u l=1u m=1
> xiv2 n4 zi inv
> xiv3 io n4 inv
> .ends bd4t
> 
> .subckt nand a b z
> mpa z a vdd vdd p w=6u l=1u m=1
> mpb z b vdd vdd p w=6u l=1u m=1
> mna z a mid gnd n w=3u l=1u m=1
> mnb mid b gnd gnd n w=3u l=1u m=1
> .ends nand
> 
> .subckt inv a z
> mp z a vdd vdd p w=6u l=1u m=1
> mn z a gnd gnd n w=3u l=1u m=1
> .ends inv
> 
> ::::::::::::::
> proc.max
> ::::::::::::::
> .lib './junk.lib' BEST
> ::::::::::::::
> proc.min
> ::::::::::::::
> .lib './junk.lib' WORST
> ::::::::::::::
> proc.typ
> ::::::::::::::
> .lib './junk.lib' TYPICAL