Subject: Re: Egg10 Implementation

From: "C. Kumar" <[email-masked]>
Date: Thu, 31 Oct 1996 13:04:21 -0500

That is a relative check. I have seen models which do not settle to anything anything near the dc voltage. I mean the dc voltage defined by the VI table. (it should be the true dc , isn't it?). I think it is necessary explicitly clarify whether you are talking about dc voltage or steady state settling voltage.

> From [email-masked] Wed Oct 30 16:17 EST 1996
> Received-Date: Wed, 30 Oct 1996 16:17:17 -0500
> From: Chris Rokusek <[email-masked]>
> To: [email-masked]
> Subject: Egg10 Implementation
> Content-Type: text
> Content-Length: 1505
> X-Lines: 58
> 
> Hi All,
> 
> I've got a working version of ibischk2 that compares AC waveform
> endpoint voltages against the (DC) VI curves and the correspond test
> fixture.
> 
> I need to define a tolerance of some sort to which the voltages agree.
> This relates to prior discussion of how long a waveform needs to
> settle.  The spec does not provide a tolerence...
> 
> 
>      Keywords:     [Rising Waveform], [Falling Waveform]
>      .
>      .
>      .
>                    A waveform table must include the entire waveform;
>                    i.e., the first entry (or entries) in a voltage column
>                    must be the DC voltage of the output before switching
>                    and the last entry (or entries) of the column must be
>                    the final DC value of the output after switching.
> 
> 
> 
> I think we need to define a % voltage that the first/last entries must
> lie within (e.g. 2.0%).  
> 
> Percent of what, though?  Well, how about percent of 0% to 100% of the
> waveform endpoint voltages difference itself.  This would require a
> highly loaded waveform to settle to a more absolute voltage since it
> would have a smaller voltage swing.  Is this a good thing? 
> 
> 
> Also, this is easy to implement!! :)
> 
> 
> Example Waveform:
> 
>    Begins: (0ns, 0.0V)
>    Ends:   (9ns, 4.0V)
>    Load:   50 Ohms, 0.0V
>    
> 
> For 2% agreement, the v_tolerance = 2% * (4.0 - 0) = .08V
> 
>   So model passes if...
> 
>       -0.08 < v_dc_low_for_load < 0.08   
> 
>                AND
> 
>        3.92 < v_dc_high_for_load < 4.28
> 
> 
> Is this reasonable?
> 
> -Chris R.
> 
> 
>

---

From: Chris Rokusek <[email-masked]>
Date: Thu, 31 Oct 1996 10:50:02 -0800

Kumar,

> That is a relative check. I have seen models which do not settle to anything anything near the dc voltage. I mean the dc voltage defined by the VI table. (it should be the true dc , isn't it?). I t…

The test is designed to enforce what the spec says:

      A waveform table must include the entire waveform;
      the first entry (or entries) in a voltage column
***   must be the DC voltage of the output before switching
      and the last entry (or entries) of the column must be
      the final DC value of the output after switching.

The spec says "MUST BE", I think the spec should be more explicit and
say something more along the lines of...

The first/last waveform point voltages must lie within X Volts of the
given fixture loads interection with the appropriate (TYP/MIN/MAX) VI
curve where X = (first Waveform voltage point - last Waveform voltage
point) * 2%.

The models you mention that don't settle to anything near dc appear to
be in violation of the current spec.  Correct?  If we can decide on a
percentage, be it .01%, 1%, or 5%, then ibischk2 can enforce the spec
with the added code.

In the orginal example below, "v_dc_for_load" refers to the intersection
of the load line with the DC vi curve and thus would enforce a
correlation between each AC waveform endpoint and the VI curves.