Subject: Re: Rising Waveform Loading Effects

From: [email-masked] ( Bob Ross)
Date: Thu, 24 Oct 96 11:14 PDT

Ed:

Your concern about accuracy of IBIS models in simulation environments
is valid.  I do not want to get totally bogged down here in an 
accuracy debate, but I want to make a few points:

1. The IBIS models might be positioned at a higher level of abstraction
than Spice models.  IBIS models are based on actual measured or Spice
derived information.  So to the extent that the IBIS model is accurate
depends only on the source information.  IBIS models do not carry all
of the parameters that are contained in a Spice model.

2. IBIS models have performed very well in PCB design and simulation
environments.  The EDA vendors have algorithms which treat transmission
lines and vias and otehr effects very well.  Many times these elements
provide the dominant characteristics rather than the model details.

IBIS models are very suitable with large sized physical data bases (the
whole board) containing thousands of nets and many components.  Just
getting Spice models that are compatible (e.g., are of equal accuracy,
do not have conflicting options such as scaling factors, and are actually
available from the vendors, etc.) is in practice usually unrealistic.
Physical databases capture the layout of each net and locations of nearby
nets.  So board level analysis where random interactions can occur
is one area where IBIS models (or behavioral models in general) are
appropriate.

Spice analysis might be better for a detailed investigation of some
critical nets to validate a design or to really test some variations.
The network topology may be easier to describe here.

3. Regarding the Waveform extraction methodology, the objective is to
provide test loads which create the best model.  They need to be as
close as possible to the simulation enviroment.  In high speed applications
the transmission line load looks initially resistive, but may be at any
voltage from low state to high state (and beyond) based on the dynamic
reflection characteristics.  So I feel for CMOS technology that resistive
test loads to ground and Vcc of approximately 50 to 100 ohms (or whatever
the characteristic impedance) will provide the best model.  This set
spans the voltage range and provides the load resistance seen by the 
device.  Simulators properly handle any added capacitance and inductance
that is seen by the device.  

The IBIS mode architecture is a simplified representation of most 
devices for the purposes of modeling.  To the extent that the Spice model
architecture functions in the same manner, the IBIS model will be very
accurate.  A fixed percentage (such as 5%) accuracy when comparing
a Spice model and IBIS model directly under a test suite may not be
achieved, in my opinion, for many devices because of the internal non-linear
switching characteristics of actual Spice models (and devices).  However,
for timing and signal integrity analysis of real networks, the accuracy
is very good compared to a similar Spice analysis and measurements.

Best Regards,
Bob Ross
Interconnectix, Inc.

> Hello to all,

> I am concerned about the validity of using IBIS models for general
> printed circuit board signal analysis in an environment of various types
> of loads, transmission lines, vias, pads, connectors, various
> terminations, etc.

> According to the IBIS specification V2.1 dated Dec. 13, 1995,  for a
> rising waveform (for example), there are various loads specified as
> L_dut, R_dut, L_fixture, R_fixture, C_dut, and C_fixture.  In addition
> data is to be taken with the effects of C_comp included.  There is
> however no provision for generating curves with a transmission line load
> which is more typically the case, especially for high speed circuits. in
> actual circuit boards.

> It is well known however, that the ramp rate and levels reached will be
> affected by the loads. For example, changing  the values of R_fixture
> and V_fixture on a typical buffer. (The s2ibis2 program will generate
> different curves for different values of R_fixture, for example IBIS
> curves for  50 ohms and 100 ohms is generated from a command file that
> specified curves for 50 and 100 ohms.)

> My question is this:  If in an actual simulation environment we really
> have a different loading condition with transmission lines , vias, etc.,
> how can we legitimately use an IBIS model that was generated with a
> different lumped element loading condition ?

> I hope someone can help me to understand how the IBIS models will
> accurately produce the correct physical response with an arbitrary but
> realistic loading condition, different from the test fixture, at least
> to a level of accuracy close to that which would result from the
> original transistor level spice model, say within 5%.

> Ed Boeckmann,  "My comments reflect solely my own opinion!"
> Intergraph Corp.
> Huntsville AL 35894
> tel. (205)-730-6219
> fax (205)-730-6000
> email [email-masked]

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From: Brock Hannibal <[email-masked]>
Date: Fri, 25 Oct 1996 13:43:49 -0700

Hi all,

Let me add a thought. Ed Boeckman asks:

"I hope someone can help me to understand how the IBIS models will
accurately produce the correct physical response with an arbitrary but
realistic loading condition, different from the test fixture, at least
to a level of accuracy close to that which would result from the
original transistor level spice model, say within 5%."

I've found that board level simulation accuracy is difficult to quantify
as a percentage number. There are a number of contributing factors such
as etch width and thickness variations along the length of the interconnect
line, cross-section variations(dielectric thickness), dielectric constant
variation with frequency, humidity, temperature, etc. Most FR-4 type boards
are themselves about 10% components. Holding the boards to a tighter tolerance
is both expensive and difficult. 

It turns out that if the IBIS model is derived into a nominal resistive
load that is representative of the transmission line characteristic
impedance that the dominant effect in the simulation is usually the
transmission line formed by the interconnect. 

I have verified this by actual measurement in a number of cases. This is
not to say that the model is irrelevant, only that the model's  
output impedance curves and risetimes are not as critical as one might
think in predicting the performance of the system.

Brock Hannibal
Design Engineer
Tektronix, Inc.

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From: Jon Powell <[email-masked]>
Date: Mon, 28 Oct 1996 09:10:36 -0800

> think in predicting the performance of the system.

I must disagree with this statement. Though accurate transmission line
characteristics are crucial for simulation, risetime and IV curve
accuracy is also important. The IV curve vs line impedance directly
determines the incident wave height (and thus incident switching and/or
number of round-trips to switch) and crosstalk and overshoot are a
function of risetime/falltime as much as line coupling and impedance.

Jon Powell
Quad Design

---

From: Brock Hannibal <[email-masked]>
Date: Mon, 28 Oct 1996 17:01:28 -0800

Hi all,

Well Jon, I don't think we fundamentally disagree. It's more a matter of degree.
For instance, if I can hold tolerance of characteristic Z, losses, L and C of
vias, L and C of package pins, stability of power supplies, etc. to really
tight tolerances then I can make use of extremely accurate IBIS models which
have V@t curves which are derived into my known load. Unfortunately all these
other factors are extremely difficult to hold to tight tolerances. All I
was saying was that an IBIS model derived into a resistive load is probably
sufficient for most signal integrity work. 

The current crop of IBIS models are a far cry from being accurate enough 
to really predict the kinds of things Jon is talking about, but many of
them are good enough to ensure that I don't drastically mis-terminate
the transmission lines on my boards.

Another question to think about: do Ibis models derived from Spice models
really have the kind of accuracy that Jon needs?

Brock Hannibal
Design Engineer
Tektronix, Inc.

Jon Powell says,