Subject: Re[2]: Interpretation of I/O data

From: Arpad Muranyi <[email-masked]>
Date: Mon, 22 Jan 96 13:03:00 PST

Text item: 

John,

Sorry that I didn't respond for so long, but I was very busy the last few weeks.
Here are my answers to your EMAIL:

>OK. My question was to confirm that the static I/V curve
>could be extracted from an IBIS file.
>I think so, but two cases are unclear for me (due
>to the lack of examples?): FAST-type inputs and Bus-hold inputs.

What are you referring to when you say FAST-type?
Shouldn't the Bus-hold circuit be modeled as an output rather than an input?

>If there is more than one power-supply, and one supply fails,
>it would be useful to predict the input impedance of an unpowered
>input buffer.

Inputs usually clamp below and above the supply rail.  If the failing power 
supply shorts to GND, the input will clamp below -0.6 volts and above +0.6 
volts.

>Can a buffer which doesn't clamp when powered, clamp
>when unpowered (for applied voltages in the range 0 to Vcc)?

If the power on the input disables the clamping somehow, I can see that it could
clamp when it is not powered.  But it would be helpful if you would state what 
kind of input you are referring to.  Regular CMOS, or something unusual, which I
don't know about?  CMOS DOES clamp ewen when it is powered (0.6 volts above 
Vdd).

>Then I have misunderstood the use for "Vinh" and "Vinl". Are these not
>used to decide if a simulated signal is acceptable or not? Specifying
>the minimum hysteresis would correctly allow noisier signals to pass,
>(this is often the reason for choosing a buffer with hysteresis).

These two keywords are not there to define the hystereris.

>I'd hope a simulator would warn me if any signals risk crossing
>a threshold too slowly.

Valid point, but there is no keyword in IBIS yet to base this warning on.  If it
is important to you, you might want to raise this (and the hysteresis) issue in 
the Open Forum Meeting.  I brought it up last time, and people are open to these
kinds of comments, requests.

Sincerely,

Arpad
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Subject: Re: Interpretation of I/O data
To: Arpad Muranyi <[email-masked]>
Organization: Alcatel CIT, 22304 Lannion, France
From: FITZPATRICK John <[email-masked]>
Date: Thu, 14 Dec 1995 19:59:27 +0100
Sender: [email-masked]
c 1995 15:37:57 GMT
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---

From: Andy Ingraham <[email-masked]>
Date: Mon, 22 Jan 96 22:33:05 EST

I wasn't the one who asked the questions, but I'll throw in my two bits,
if for no other reason than to give another opinion.

> Shouldn't the Bus-hold circuit be modeled as an output rather than an input?

Bus-hold circuits are typically used on bi-directs, but because they
come into play when the output is disabled, one tends to think of them
as being part of the input circuit rather than the output.  It seems to
make more sense to model them as input currents, since they are always
there whether the output drives or not.

Since IBIS is predicated on modeling static I/V characteristics, and
since the I/V curves of bus-hold circuits depend on past history (a
bi-stable state), there is a problem of how to model them.  Anyway,
they may be problematic because of their positive feedback.

> supply shorts to GND, the input will clamp below -0.6 volts and above +0.6 

Not necessarily.  Many IC inputs do not clamp in the positive direction,
or if they do, it is not at Vcc +0.6 volts.

CMOS inputs need not clamp at all, in principle.  Generally speaking,
clamps are added for their protection.

Some IC inputs are designed not to conduct when power is removed;
important for hot-swapping boards or running independent units on a
common bus.  I think this is the question John Fitzpatrick is getting
at.  Will the clamp characteristics be the same (relative to Vcc) with
the power removed as when it is present?  I can't say, though I think
there is a good likelihood that the gross behavior would be similar. 
It is probably best to contact the IC manufacturer or IBIS model writer
to see under what conditions those parameters apply.

Regards,
Andy

---

From: Arpad Muranyi <[email-masked]>
Date: Tue, 23 Jan 96 08:02:00 PST

Text item: 

Andy,

I agree with your response.  The main problem I see in this discussion is that 
we are talking about something, but we don't really know what we are talking 
about.  We need a definition what that "INPUT" really is.  True CMOS input, a 
CMOS I/O in receiving mode, Bipolar, etc...  The answer might be quite 
different.

This kind of holds for the bus-hold circuits as well.  Whether we can model it 
or not with IBIS depends on how it is built.  Is there feedback or other fancy 
stuff in it?  Is it just a static pullup or pulldown structure?  etc...

Arpad
===============================================================================

Regards,
Andy

Subject: Re[3]: Interpretation of I/O data
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From: Andy Ingraham <[email-masked]>
Date: Mon, 22 Jan 96 22:33:05 EST
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