Subject: BIRD38 Maximum Voltage

From: [email-masked] ( Bob Ross)
Date: Thu, 4 Jul 96 11:19 PDT

Below is a proposal to include maximum input voltage specifications in an 
IBIS model. 

The key elements are:

   i) A new keyword [Maximum Voltage] is added per buffer model

  ii) Maximum inputed voltage tolerated as a function of time is given in
      a table

Two examples are included to explain why this information might be
useful to a board designer.
 
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BIRD ID#:      38
ISSUE TITLE:   Maximum Voltage
REQUESTER:     John Fitzpatrick, Alcatel
DATE SUBMITTED:                       July 03, 1996
DATE ACCEPTED BY IBIS OPEN FORUM:     Pending

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STATEMENT OF THE ISSUE:

IBIS can be extended to allow a component supplier specify maximum positive
and negative voltages (or currents) that can safely be applied to 
an I/O buffer.
These limits are expressible as a function of time to give maximum 
flexibility to board designers.

Note: Because IBIS simulation data is provided from -Vcc to 2Vcc, a
non-specialist might wrongly believe that these are the limits on
the applied voltage.

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STATEMENT OF THE RESOLVED SPECIFICATIONS:

Add the following keyword after the [Model] keyword:

|=====================================================================
|
|    Keywords: [Maximum Voltage]
|
|    Required: Yes, unless the component works for all simulation points
|
| Description: Defines the maximum positive and negative voltages
|              that can safely be applied to an I/O buffer.
|
|  Sub-params: POWER_Clamp_Reference, Pullup_Reference
|
| Usage Rules: This keyword defines a table of voltage versus time points.
|              The table contains a minimum of three and a maximum of five
|              columns:            
|                  1- time
|                  2- maximum positive voltage for hi-Z state (tri-state)
|                  3- maximum negative voltage for hi-Z state 
|                  4- maximum positive voltage for lo-Z (active) state 
|                  5- maximum negative voltage for lo-Z state 
|              Entries for lo-Z (active) state are included only if the limits
|              are different than in hi-Z state (3-state).
|
|              Negative voltage are referenced to GND.
|
|              Positive voltages are referenced to either the positive supply
|              rail or to GND, according to the following rules:
|
|                If POWER_Clamp_Reference=yes then the maximum positive
|                voltage for hi-Z state is referenced to [POWER Clamp 
|                Reference].
|                Otherwise it is referenced to GND.
|
|                If maximum voltages are specified for the lo-Z (active) state:
|                 If Pullup_Reference=yes, then the maximum positive voltage
|                 for the active state is referenced to [Pullup Reference].
|                 Otherwise it is referenced to GND.
| 
|              The last entries in the table are the static absolute maximum
|              voltages. 
|
|              When a waveform exceeds a static voltage, the simulator will 
|              set time=0, then check that the rest of the waveform is 
|              within the dynamic limits given in the table. 
|
| Other Notes: 
|
|           A) How to specify/calculate maximum current
|
|              It is not possible to directly specify the maximum applied
|              current. However, as the [Pullup], [POWER Clamp], [Pulldown]
|              and [GND Clamp] are known, the input impedance (R) can be 
|              calculated. Using Ohm's law, the maximum voltage which 
|              correspond to a maximum current is easily found (I=V/R).
|
|           B) What values to specify
|
|              When specifying limits, the component supplier might take
|              into account the following situations where the static
|              maximum ratings will be exceeded:
|
|              1) Reflections:
|                 - An over- or undershoot can last for less than 20ns.
|                 - If there are no clamping diodes, the buffer should
|                   tolerate applied voltages from -Vcc to 2Vcc (CMOS buffer)
|                 - If there are clamping diodes, the buffer should tolerate
|                   applied currents from -Vcc/Z to Vcc/Z (CMOS buffer),
|                   where Z is the track impedance. Usually Z > 40 ohms.
|
|              2) Power supply failure
|                 - In a multi-supply design (e.g. mixed 5V/3V bus), a
|                   buffer should tolerate excess applied voltages(dV)
|                   and currents(I) from the time its power supply fails until
|                   all connected outputs are disabled (time Tfail later).
|                       Tfail < 50us 
|                           I < 250mA 
|                          dV < 3.3V  (e.g. 5V buffer on mixed 5V/3V bus)
|
|                 Note: The simulator will assume that the section of the
|                 [POWER clamp] table above Vcc can be used (shifted?) for all
|                 values of supply voltage from 0 to Vcc.
|
|           C) Relationship with RAIL
|              
|              The RAIL standard allows for a single-value dynamic undershoot
|              and overshoot to be specified. A single value overshoot
|              value can be extracted from an IBIS file by averaging the
|              maximum voltage over a short timeframe e.g. 20 ns.
|
|           D) Examples
|
|              The example below could represent a CMOS output, with a
|              permanent clamping diode to GND, and a clamping diode to
|              Vcc in active state only:
|
[Maximum Voltage]
|
Pullup_reference=yes
POWER_clamp_reference=no
|
|   Time        Vpos(3-state)   Vneg(3-state)   Vpos(active)  Vneg(active)
     0              7              -2             2        -2
     20ns           7              -2             2        -2
     30ns           5.5            -1.5           1.5      -1.5
     50us           NA             -1             1        -1
    100us           5.5            -0.5           0.5      -0.5
 
|
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ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

The manner in which absolute maximum ratings are given in paper databooks
is extremely conservative. Typically, the board designer is expected to
guarantee that the voltage V applied to a buffer be in the range
      -0.5V < V < Vcc+0.5V. (*)

Most board designers know that these limits are often exceeded in their
designs due to reflections, without any harm being done to the component.
They would however like to have real risks flagged by a simulator.

In multiple power supply designs (e.g. mixed 3.3V/5V), it is possible
to have "5V tolerant" 3.3V buffers. But what happens if one of the
power supply fails? The designer would like to know if it is sufficient
to disable all output buffers, and if so, within what time-frame.

Some suppliers specify the absolute max voltage as a function of Vcc,
others tolerate any voltage up to a limit (usually 7V), even if Vcc
is set to 0V. The sub-parameter POWER_Clamp_Reference allows this
distinction to be taken into account.

Some 3.3V CMOS components (e.g. 74LVCxxx, 74LCXxxx) have output clamping
diodes in the active state only.  Optional columns are included to allow
this fact be taken into account.

This proposal is simply an extension of the existing absolute maximum
ratings, with the additional parameter: time. Any supplier who wishes
to be "customer-unfriendly" by continuing to specify (*) can write:

[Maximum Voltage]
|
POWER_clamp_reference=yes
|
|   Time        Vpos(3-state)   Vneg(3-state)
     0              0.5             -0.5

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ANY OTHER BACKGROUND INFORMATION:

This BIRD has been inspired by the PCI bus specification.
The relevant references are (Rev 2.0):

   4.2.1.3 Maximum AC ratings and Device Protection (5V)
   4.2.2.3 Maximum AC ratings and Device Protection (3.3V)
   4.3.2   Reset
 
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