Subject: Stored Charge by Peivand Tehrani

From: [email-masked] ( Bob Ross)
Date: Tue, 23 Jul 96 11:20 PDT

Peivand and IBIS Committee:

I tried your sample MOS Spice model regarding stored charge.  There
is a small negative preshoot glitch below zero volts before the
output rises to the high state.  For several reasons I believe that
these effects are related to the normal distribution of model
elements.  (Similar comment as Arpad's, which I just received.)

Bob Ross
Interconnectix, Inc.

---

From: [email-masked]
Date: Tue, 23 Jul 1996 11:19:36 -0700

Arpad,

I agree with you. 
I believe what Peivand saw is a well-known Miller effect, which
is related to the gate to drain capacitance of the CMOS inverter.

Sung

 >>From [email-masked] Tue Jul 23 11:03 MST 1996
 >>Date: Tue, 23 Jul 96 10:34:00 PDT
 >>From: Arpad Muranyi <[email-masked]>
 >>To: [email-masked]
 >>Subject: Re: Stored Charge by Peivand Tehrani
 >>
 >>Peivand,
 >>
 >>I looked at your simulation example, and I think that you are referring to a 
 >>phenomena as the "glitch" which is unrelated to the "kickback effect", 
commonly 
 >>associated with the charge storage effects (discussed in BIRD34) of clamping 
 >>diodes, ESD structures, etc.
 >>
 >>In my opinion the glitch you are observing is related to the parasitic 
 >>capacitances between Drain-Source, Gate-Source, and Gate-Drain.  When the 
gate 
 >>voltage of the inverter begins to switch, there is a time period when none of 
 >>the output transistors are (fully) on.  The changing voltage on the gate 
bleeds 
 >>through the parasitic capacitances to the output untill the transistor to be 
 >>turned on gets turned on.  Since we are talking about an inverter, this 
causes a
 >>glitch that goes the opposite direction of the intended edge.  If you try to 
 >>reproduce the same effect with a "voltage follower" circuit, you will see 
that 
 >>the "glitch" will go in the same direction with the intended edge.
 >>
 >>Arpad Muranyi
 >>Intel Corporation
 
>>==============================================================================
==
 >>
 >>
 >>
 >>Author:  [email-masked] at SMTPGATE
 >>Date:    7/19/96  5:50 PM
 >>Priority: Normal
 >>TO: [email-masked] at SMTPGATE
 >>CC: [email-masked] at SMTPGATE
 >>BCC: Arpad Muranyi at FMCCM28
 >>Subject: Stored Charge
 >>------------------------------- Message Contents 
-------------------------------
 >>Hello IBIS fans,
 >>
 >>   I was reviewing the stored charge BIRD 34.1 . I have observed the
 >>same glitch effect even with ESD diodes removed. So I think this glitch
 >>is not just created by the stored charge in the diodes. This glitch can
 >>easily be observed with a simple CMOS invertor with a fast (100 psec)
 >>ramp as the input of the invertor, I think this glitch is because of the
 >>stored charge in the depletion region of upper and lower devices.
 >>
 >>   I will send a simple SPICE file that I have been using to simulate this
 >>effect. The SPICE version which I am using runs into convergence problems
 >>if I remove Cd1 capacitor. This capacitor presents the die capacitor in
 >>IBIS models. After the simulation the voltage at node 2 should be probed.
 >>
 >>Best Regards,
 >>Peivand Tehrani.
 >>
 >>
 >>**************************SPICE file************************
 >>
 >>
 >>
 >>Driver Device Transitions For Gate Transition
 >>*************************************************************
 >>VDD 3 0 5
 >>*************************************************************
 >>M1   2   1    0   0   QN   L=1.5E-6   W=136.4E-6
 >>M2   2   1    3   3   QP   L=1.5E-6   W=341E-6
 >>*************************************************************
 >>.MODEL QN NMOS(LEVEL=1 VTO=1.0 TOX=250E-10 NSUB=1E16 UO=500 )
 >>.MODEL QP PMOS(LEVEL=1 VTO=-1.0 TOX=250E-10 NSUB=1E16 UO=200)
 >>*************************************************************
 >>VIN1   1    0  PULSE(5 0 0 .01n 0 100E-9 1E-3)
 >>*************************************************************
 >>Cd1    2    0   4p
 >>R11    2    0   50
 >>*************************************************************
 >>.tran .001n 1n
 >>.END
 >>

---

From: Arpad Muranyi <[email-masked]>
Date: Tue, 23 Jul 96 13:38:00 PDT

Text item: 

Sung, Peivand, and IBIS fans,

Here is a simulation example for what I wrote about in my previous EMAIL.  I did
two things to Peivand's original simulation example:

1)  Added a voltage-follower circuit, which is an N-channed pullup.  A 50 Ohm
    resistor is connected between its output and GND.  Observe nodes 10 and 20
    (Gate and Source).
2)  Added a CAPOP parameter and a bunch of 0 values to turn of all (or most?)
    capacitance modeling that is given by HSPICE automatically.

(I am using HSPICE here).

To see the glitch with the non-inverting output, plot nodes 10 and 20.  Notice 
that the glitch goes in the same direction as the output is switching, that is, 
rising edge output causes a positive glitch.  (In Peivand's example the glitch 
goes negative while the output is going positive).  However, in both cases, the 
glitches follow the direction of the input signal.  This proves that the glitch 
is related the input signal through parasitic capacitances.

To see that these glitches go away without parasitic capacitance, uncomment the 
lines starting with "+ CAPOP ... " in both .MODEL statements.  The glitches 
should go away completely.

Arpad

Driver Device Transitions For Gate Transition
*************************************************************
.tran .001n 3.0n
.OPTIONS POST=1
VDD  3  0  DC=5.0V
*************************************************************
VIN1   1    0  PULSE (5 0  1.0ns 0.01ns 0.01ns 100E-9 1E-3)
M1   2   1    0   0   QN   L=1.5E-6   W=136.4E-6
M2   2   1    3   3   QP   L=1.5E-6   W=341E-6
*Cd1    2    0   4p
R11    2    0   50
*-----------------------------------------------------------*
VIN10  10   0    PULSE (0  5  1.0ns 0.01ns 0.01ns 100E-9 1E-3)
M10    3    10  20   0   QN   L=1.5E-6   W=136.4E-6
R10    20   0   50
*************************************************************
.MODEL QN NMOS(LEVEL=1 VTO=1.0 TOX=250E-10 NSUB=1E16 UO=500 )
*+ CAPOP=0 CF1=0 CF2=0 CF3=0 CF4=0 CF5=0 CF6=0 CGBEX=0
.MODEL QP PMOS(LEVEL=1 VTO=-1.0 TOX=250E-10 NSUB=1E16 UO=200)
*+ CAPOP=0 CF1=0 CF2=0 CF3=0 CF4=0 CF5=0 CF6=0 CGBEX=0
*************************************************************
*************************************************************
.END

----------------------------------------------------------------------
Arpad,

I agree with you.

Sung
----------------------------------------------------------------------
 >>Driver Device Transitions For Gate Transition

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Subject: Re: Stored Charge by Peivand Tehrani
To: [email-masked]
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---

From: "Peivand F. Tehrani" <[email-masked]>
Date: Wed, 24 Jul 1996 11:34:58 -0400 (EDT)

Arpad, Bob and Sung,
 
  This is a good observation, my point was that the "glitch" exists
and may propagate along a signal line. As arpad has shown, depending 
on the value of the parasitic capacitors, the loading and the gate
risetime, magnitude of this glitch will change.
  This effect is a device property and although it is small, in order 
to get accurate device simulation, it has to be modeled.
  The[xxxxing waveform]s can only provide the magnitude of this glitch 
under a certain loading condition. Note that in the invertor case, the
glitch causes the buffer low to high transition trajectory (id(m1)-id(m2) 
vs. v(2)) to jump out of the device [pullup] and [pulldown] I/V 
characteristics. This is dynamic effect and without knowing the exact 
gate transition waveform (which is the case in IBIS), the values of the
parasitic capacitors can not be extracted from the provided information.
  The glitch has a current associated with it which is provided by either
one of upper and lower devices. Without knowing the value of the parasitic
caps. it is hard to divide this current between the devices.
  Do you have any suggestions as to how I can approach this problem using
the provided IBIS information?
  
Best regards
peivand

---

From: Arpad Muranyi <[email-masked]>
Date: Thu, 25 Jul 96 11:53:00 PDT

Text item: 

Peivand,

Your observation is correct.  The problem is that this is a difficult phenomena 
to model behaviorally (as far as I know).  However, in my opinion, this effect 
is rather small, so I would not worry too much about it in system level 
simulations.

If you think this an important issue and it needs to be addressed by the IBIS 
standard, bring it up for discussion in one of the future open forum meetings.  
If it turns out that many people would like to see a solution for it, we might 
work out a way to model it.

Arpad
================================================================================
Arpad, Bob and Sung,

Best regards
peivand

Subject: Re[3]: Stored Charge by Peivand Tehrani
Cc: [email-masked]
To: Arpad Muranyi <[email-masked]>
From: "Peivand F. Tehrani" <[email-masked]>
Date: Wed, 24 Jul 1996 11:34:58 -0400 (EDT)
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