Subject: Egg : Absolute Maximum Ratings

From: FITZPATRICK John <[email-masked]>
Date: Thu, 23 May 1996 18:46:55 +0200

To IBIS mailing list:

Below is a proposal to include absolute maximum rating in an 
IBIS model. 

The key elements are:

   i) A new keyword [Maximum Voltage] is added

  ii) A table is given of the maximum voltage as a function of time

Two examples are given to explain why this information might be
useful to a board designer.

Unfortunately, I'm not an expert on what the physical reasons for
the maximum applied voltage are, so I would be very grateful for any 
comments from component designers on the following statements:

 a) Most often suppliers say the limit is latchup, requiring 
    current limitation.
    Does anyone have typical latch-up current vs. time curves?
 b) I was once told that the limit was the amount of reverse
    current in the power rings, and that the max current
    depended on the no. or power pins and no. of buffers in question!
 c) I also understand that the the finer the technology, the less
    its tolerance to higher voltages. So, for example, even without clamping
    diodes to Vcc, it may not be possible to make a 2.5V buffer which
    is 5V-TTL compatible.

I look forward to your comments,

Regards,
John

-- 
John Fitzpatrick   <[email-masked]>    
Alcatel CIT, 4 rue de Broglie, 22304 Lannion, France
Tel: (+33)96.04.79.33  Fax: (+33)96.04.85.09 To IBIS mailing list:

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BIRD ID#:      NA
ISSUE TITLE:   Absolute Maximum Voltage
REQUESTER:     John Fitzpatrick, Alcatel
DATE SUBMITTED:                       May 20, 1996
DATE ACCEPTED BY IBIS OPEN FORUM:     NA

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STATEMENT OF THE ISSUE:

IBIS can be extended to allow a component supplier specify the absolute
maximum voltages and currents that can be applied to an I/O buffer.
These limits should be expressible as a function of time to give
maximum flexibility to board designers.

Note: Because IBIS simulation data is provided from -Vcc to 2Vcc, a
non-specialist might wrongly believe that there are no absolute
maximum limits.

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STATEMENT OF THE RESOLVED SPECIFICATIONS:

Add the following keyword after the [Model] keyword:

|=====================================================================
|    Keywords: [Maximum Voltage]
|    Required: Yes, unless the component works for all simulation points
| Description: Defines the extreme positive and negative voltages
|              that can safely be applied to an I/O buffer.
|  Sub-params: POWER_Clamp_Reference, Pullup_Reference
| Usage Rules: This keyword defines a table of voltage versus time points.
|              There are four voltages: positive (above POWER) and negative
|              (below GND) voltages for 3-state and active(low impedance)
|              state.
|              Entries for active state are included only if the limits
|              are different than in 3-state.
|              Negative voltage are referenced to GND.
|              Positive voltages are given in the form:
|                   V = Vapplied - Vcc    if POWER_Clamp_Reference=yes
|                 or
|                   V = Vapplied          if POWER_Clamp_Reference=no
|              The last entries in the table are the static absolute maximum
|              voltages. When a waveform exceeds a static voltage, the
|              simulator will set time=0, then check that the rest of the
|              waveform is within the dynamic limits given in the table. 
|
| Other Notes: The I/V curves [Pullup], [POWER Clamp], [Pulldown] and
|              [GND Clamp] are used to calculate the input impedance,
|              and hence the absolute maximum currents.
|              If the component supplier wishes to specify the absolute maximum
|              current, he must calculate the corresponding maximum voltage.
|
|              When specifying limits, the component supplier might take
|              into account the following situations where the static
|              maximum ratings will be exceeded:
|
|              1) Reflections:
|                 - An over- or undershoot can last for up to 20ns (?)
|                 - If there are no clamping diodes, the buffer should
|                   tolerate applied voltages from -Vcc to 2Vcc (CMOS buffer)
|                 - If there are clamping diodes, the buffer should tolerate
|                   applied currents from -Vcc/Z to 2Vcc/Z (CMOS buffer),
|                   where Z is the track impedance. Usually Z > 40 ohms.
|
|              2) Power supply failure
|                 - In a multi-supply design (e.g. mixed 5V/3V bus), a
|                   buffer should tolerate excess applied voltages(dV)
|                   and currents(I) from the time its power supply fails until
|                   all connected outputs are disabled (time Tfail later).
|                       Tfail < 50us (Latchup is faster?)
|                           I < 250mA (?)
|                          dV < 3.3V (?) (e.g. 5V buffer on mixed 5V/3V bus)
|
|                 Note: The simulator will assume that the section of the
|                 [POWER clamp] table above Vcc can be used (shifted?) for all
|                 values of supply voltage from 0 to Vcc.
|
|              The example below could represent a CMOS output, with a
|              permanent clamping diode to GND, and a clamping diode to
|              Vcc in active state only:
|
[Maximum Voltage]
|
Pullup_reference=yes
POWER_clamp_reference=no
|
|   Time        Vpos(3-state)   Vneg(3-state)   Vpos(active)  Vneg(active)
     0              7              -2             2        -2
     20ns           7              -2             2        -2
     30ns           5.5            -1.5           1.5      -1.5
     50us           NA             -1             1        -1
    100us           5.5            -0.5           0.5      -0.5
 
|
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ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

The manner in which absolute maximum ratings are given in paper databooks
is extremely conservative. Typically, the board designer is expected to
guarantee that the voltage V applied to a buffer be in the range
      -0.5V < V < Vcc+0.5V. (*)

Most board designers know that these limits are often exceeded in their
designs due to reflections, without any harm being done to the component.
They would however like to have real risks flagged by a simulator.

In multiple power supply designs (e.g. mixed 3.3V/5V), it is possible
to have "5V tolerant" 3.3V buffers. But what happens if one of the
power supply fails? The designer would like to know if it is sufficient
to disable all output buffers, and if so, within what time-frame.

Some suppliers specify the absolute max voltage as a function of Vcc,
others tolerate any voltage up to a limit (usually 7V), even if Vcc
is set to 0V. The sub-parameter POWER_Clamp_Reference allows this
distinction to be taken into account.

Some 3.3V CMOS components (e.g. 74LVCxxx, 74LCXxxx) have output clamping
diodes in the active state only.  Optional columns are included to allow
this fact be taken into account.

This proposal is simply an extension of the existing absolute maximum
ratings, with the additional parameter: time. Any supplier who wishes
to be "customer-unfriendly" by continuing to specify (*) can write:

[Maximum Voltage]
|
POWER_clamp_reference=yes
|
|   Time        Vpos(3-state)   Vneg(3-state)
     0              0.5             -0.5

Remarks:

1) Should there be an optional keyword [Maximum Current] which could
   replace [Maximum Voltage] if the component supplier prefers to
   specify maximum current rather than maximum voltage.
   This would shift the burden of applying Ohms' Law to the simulator.

2) Many of the figures above are rough estimations or educated guesses.
   Feedback from component designers is needed.

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ANY OTHER BACKGROUND INFORMATION:

This BIRD has been inspired by the PCI bus specification.
The relevant references are (Rev 2.0):

   4.2.1.3 Maximum AC ratings and Device Protection (5V)
   4.2.2.3 Maximum AC ratings and Device Protection (3.3V)
   4.3.2   Reset

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