Subject: Bird 31.1 and 20/80 Spec.

From: [email-masked]
Date: Mon, 06 May 96 08:06:35

Gentlemen
     
     I have two questions:
     
     1.  20% - 80% Rise/Fall time..  I have to admit, my understanding of 
     ECL logic use in the semiconductor industry is somewhat low...  but... 
     The trend for our customers is a 10-90 Rise/Fall time specification...
     There is a different constant to calculate bandwidth using 20-80.  The 
     model could use the same structure but reference a different edge rate 
     sdue to the different Rise/Fall measurment.
     
     How is a 20-80 Rise/Fall specification more readily extracted in a 
     noisy simulation?  Does this allow for extra roll of in the "dog leg" 
     areas of a digital pulse?  Are there "convergance" issues when using IBIS  
      solvers?
     
     2. Someday femptoSeconds will be the industry norm.... Is a "all edge 
     rate model" pratical (using LCRZk matrices)?

     _gus Panella
     
     [email-masked]

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From: [email-masked] ( Bob Ross)
Date: Mon, 6 May 96 12:21 PDT

Gus, Stephen and IBIS Committee:

1. The 20% to 80% convention was chosen because it is consistent with the
existing dV/dt_r and dV/dt_r subparameters.  Also, since simulators 
might need to detect this during simulation, it gives less probability
of other noise or reflection artifacts entering into the determination
than, say, a 10% to 90% definition.  Finally, ECL is a high speed technology
often specified with a 50 ohm terminations and using the 20% to 80%
definition.  

The 20% to 80% definition can be transformed to the 10% to 90% definition
by the 4/3 factor or to the 0% to 100% definition by the 5/3 factor.  So
the bandwidth equivalent values could still be used from the 20% to 80%
information after it has been converted to 10% to 90% values.

This issue here is one of preference.  The 10% to 90% definition or any other
rise time definition could been used.  However, the convention used needs to
be stated.

2.  The Tedge_rate = 0 convention choices are (1) means no ("practical")
limit or (2) DC limit only.  The first choice means that the simulator
does not need to provide any checking.  The second choice means that 
the model provider must still "invent" a very small value and the simulator
may then need to provide some checking algorithm if the model structure
is not limited.  As Gus points out, the values could become very small
in practice when there is a limit.  

Regarding Stephens suggestion (2), usually DC connections are known and 
would not be checked anyway, so (2) does not convey useful information
to the simulator.  Also, if the connection is used at any frequency, then
you would generate a warning message automatically without testing.  The
same information is available by simply omitting the parameter.  Anyway,
these are some considerations on what Tedge_rate = 0 should be defined to
mean.

Bob Ross,
Interconnectix, Inc.
Secondly,