Subject: CMOS drain diodes

From: "D. C. Sessions" <[email-masked]>
Date: Wed, 20 Aug 1997 12:36:50 -0700

We use a pretty simple method to correct the parasitic
diode models for our HSPICE decks prior to doing the
IBIS extraction.

First, we replace each MOS transistor with a subcircuit
having similar characteristics and parameters; this is
handled by an AWK script:

#! /usr/local/bin/gawk -f 
BEGIN	{
	  IGNORECASE	= 1
	  }

/^M/	{
	  if( $6 ~ /^p$/ )
	    {
	      $6	= "pdt"
	      sub( /^M/, "Xmd_", $1 )
	      }
	    else if( $6 ~ /^n$/ ) {
	      $6	= "ndt"
	      sub( /^M/, "Xmd_", $1 )
	      }
	    else if( $6 ~ /^y$/ ) {
	      $6	= "ndt"
	      sub( /^M/, "Xmd_", $1 )
	      }
	    for( f = 6; f <= NF; f++ ) {
	      sub( /^L=/, "Ltc=", $f )
	      sub( /^W=/, "Wtc=", $f )
	      }
	    }
	  {
	    print
	    }

The library includes the subcircuit file for the
transistor models:

.SUBCKT	ndt	drain	gate	source	bulk
+	AS=0	AD=0	PS=0	PD=0

M1	drain	gate	source	bulk	N	L=Ltc	W=Wtc	GEO=3
*+	AS=0	AD=0	PS=0	PD=0
Dbs	bulk	drain	NDIO	AREA=AD	PJ=PD
Dbd	bulk	source	NDIO	AREA=AS	PJ=PS

.ENDS	ndt

.SUBCKT	pdt	drain	gate	source	bulk
+	AS=0	AD=0	PS=0	PD=0

M1	drain	gate	source	bulk	P	L=Ltc	W=Wtc  GEO=3
*+	AS=0	AD=0	PS=0	PD=0
Dbs	drain	bulk	PDIO	AREA=AD	PJ=PD
Dbd	source	bulk	PDIO	AREA=AS	PJ=PS

.ENDS	pdt

... which results in the area and sidewall parasitics
for the MOS devices being zeroed out (thus zeroing their
diode currents and parasitic capacitances) and in
their places are explicit diode models (NDIO and PDIO)
which have improved V/I matching and capacitances.

-- 
D. C. Sessions
[email-masked]