Subject: IBIS Face to Face Meeting Minutes

From: Stephen Peters <[email-masked]>
Date: Tue, 17 Jun 1997 08:25:31 -0700

VOTING MEMBERS AND 1997 PARTICIPANTS LIST:
 AMP                            Jeff Walden
 Applied Simulation Technology  Dileep Divekar*, Norio Matsui*, Raj Raghuram
 Cadence Design & UniCAD        C. Kumar*, Don Telian, Cameron Seitz*
 Cypress                        Bruce Wenniger
 Digital Equipment Corp.        Jeff Chu
 Hewlett Packard, EEsof         Karl Kachigan*, Henry Wu
 High Design Technology         (Razvan Ene)
 HyperLynx                      Kellee Crisafulli, Steve Kaufer*
 INCASES                        Olaf Rethmeier, Werner Rissiek*
 Intel Corporation              Stephen Peters*, Arpad Muranyi*, Henry Maramis*,
				Will Hobbs*
 Interconnectix                 Bob Ross*
 Mitsubushi                     Tam Cao, Hoang Nguyen*
 Motorola                       Ahmed Omer
 National Semiconductor         Syed Huq*, Cheng-Yang Kao, Mike Bristol,
				Peter Laflamme, Kevin Smith
 NCR                            Dave Moxley, Richard Mellitz
 NEC                            (Hiroshi Matsumoto)
 Quad Design/Viewlogic          Jon Powell, Chris Rokusek*, Peivand Tehrani*
 Quantic EMC                    (Mike Ventham)
 Texas Instruments              Thomas Fisher*
 Thomson-CSF/SCTF               (Jean LeBrun)
 VeriBest                       Ian Dodd, William Bell
 VLSI Technology                Harish Patel*, D.C. Sessions*
 Zuken-Redac                    (John Berrie)
 
 OTHER PARTICIPANTS IN 1997:
 3M                             Fran Hart
 Actel                          Scott Schlachter
 Acuson & Free Model Foundation Richard Munden*
 Alcatel                        John Fitzpatrick
 Ansoft                         Eric Bogatin
 Apteq Design Systems           Dan FitzPatrick 
 Compaq                         Weston Beal, Mark Leonard*
 EIA                            Patti Rusher*
 EMC                            Fabrizio Zanella
 Hitachi                        Saburo Hojo*, Yasushi Ogawa* 
 IBM                            Brad Herrman*
 Interface Technology           Dan Waterloo* 
 Micron Technology              Brian Johnson                      
 Molex                          Gus Panella
 North Carolina State U.        (Michael Steer)
 S3, Inc.                       Porsh Shih, Sarathy Sribhashyam
 Symmetry                       Andy Hughes*
 TRW                            Ray Steele*
 Ultratest International        Charles Im
 Zeelan Technology              George Opsahl 

 In the list above, attendees at the meeting are indicated by *.  Principal
 members or other active members who have not attended are in parentheses.
 Participants who no longer are in the organization are in square brackets.

 Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
 follows:
     
   Date               Bridge Number     Reservation #    Passcode
   Friday, July 11    (916) 356-9200     2-160894        4369865

 All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
 7 days before each open forum and meeting minutes out within 7 days after.  
 When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
 Hobbs and give the reservation number and passcode.
 
 NOTE: "AR" = Action Required.

 -------------------------------- MINUTES -------------------------------------

 INTRODUCTIONS AND MEETING QUORUM
 Twenty eight people attended the EIA/IBIS Open Forum Summit and introduced
 themselves.  Bob Ross thanked Patti Rusher of EIA for handling the meeting
 details including arranging for the fine meals and refreshments.

 PRESS AND WEB PAGE UPDATES
 Bob Ross reported two articles in the June 1997 issue of Computer Design by
 Charles Small which mention IBIS: "Demand for IBIS Models Begins to Take 
 Off", p. 34 and "Achieving Signal Integrity Demands Rethinking the Design
 Process", pp. 34-40.

 Bob Ross also submitted after the meeting these articles which refer to IBIS:
 "Signal Integrity: More than a Board Issue" in Electrical Engineering Times,
 by John Colfield and Greg Doyle on June 1997, p. 80; and "Analysis Tools 
 Target PC-Board Design-Cycle", by Cheryl Ajluni in a Supplement to Electronic 
 Design, May 27, 1997, pp. 57-63.

 NEW MODELS AVAILABLE, LIBRARY UPDATE
 Syed Hug has submitted prior to the meeting a new National URL for IBIS Models:

   http://www.national.com/models

 Bob Ross submitted prior to the meeting that Siemens has IBIS models at

   http://www.siemens.de/Semiconductor/products/ICs/31/3177.htm

 Also Bob submitted that the Micron link has changed to an FTP site

   ftp://www.micron.com/pub/ibis

 Cypress has more models in the Timing Technologies section.  Motorola also
 has added some models in the Power PC library.

 John Powell has updated the EIA/IBIS Web Site Models section with the new
 links.

 DESIGN AUTOMATION CONFERENCE (DAC) 1997 IBIS MEETING
 The morning session consisted of presentations and discussions by several
 individuals and the election of EIA/IBIS Open Forum Committee Officers
 for 1997-1998.  While this is not intended to be comprehensive, some notes
 about the presentations are given.  Among the casual conversation, Patti
 Rusher indicated good traffic at the EIA booth at DAC and continued interest
 in IBIS.  She also had reprints of Syed Huq's December 1996 Article in 
 Electronic Design: "Ease System Simulation With IBIS Device Models".  The
 IBIS poster at the Booth looked very nice and listed the participating
 companies.

 IBIS YEARLY REVIEW, Bob Ross, Interconnectix
 Bob summarized the technical features of IBIS from the "Core" Version 1.1
 in June, 1993, "Extensions" of Version 2.1 form June, 1994 through December,
 1995, and the proposed "Refinements" of June 1997.  International Progress
 includes IBIS as a work item proposal 93/46/NP in TC93 of IEC, a pending
 French proposal including EMC, Japanese activities at a more detailed level
 through EIAJ on the I/O Interface Model for Integrated Circuits and the fact
 that IBIS is referenced in EDIF 4 0 0.  

 IBIS models are now widely available from many companies (with demand for
 IBIS models greater than Spice models).  Eleven companies have model sites
 for downloading (up from four a year ago), and three commercial companies
 provide libraries and services - amounting to around 10,000 IBIS models.
 There have been s2ibis2 and ibischk2 improvements.  Four companies read
 IBIS models directly, and many others translate models from the IBIS format.
 IBIS is accepted and spreading!

 Two articles appeared on IBIS from Committee members, and Howard Johnson of
 "High Speed Digital Design, A Handbook of Black Magic" fame has written 
 favorably about IBIS.  The Committee continues to be active with over 20 
 official members and a 300+ mailing list.

 The major challenges include a clearer editorial release of IBIS Version 3.1,
 ibischk3 parser development, and improved information including the Cookbook,
 more articles and information.  Good modeling practices need to be conveyed,
 and Bob suggests that IBIS model developers attempt to work more closely 
 with CAE vendors who parse IBIS models.  s2ibis improvements are needed.
 There also continue to exist technical improvements consistent with evolving
 technology, and continued international involvement.  The major thrust is
 now for stabilization, cleanup, and information about IBIS.

 MITSUBISHI IBIS MODELING ACTIVITIES (4/96-5/97), Hoang Nguyen, Mitsubishi
 Semiconductor America, Inc.
 Hoang indicated that Mitsubishi provides IBIS, HSPICE, HDL models to support
 customers for DRAM and application-specific memory products.  A Web page is
 being created to access the models.  He showed the support system for models
 in North America and for Japan/Asian and European customers.  Mitsubishi
 IBIS models are Version 2.1 and are based on s2ibis2 processing of Spice 
 models validated by chip designers.  The response to IBIS models is positive.
 
 Hoang noted that some vendors have their own IBIS to Spice translators to
 process IBIS models in Spice simulation environments.  Hoang noted that some
 customers want test loads for waveforms and ramp different from the cookbook
 recommended test loads.  Hoang also noted that he hoped IBIS Version 3.0
 contained an index page for quick referencing of major keywords or
 definitions.

 CONSTRUCTION OF REAL EXAMPLE OF INPUT/OUTPUT INTERFACE MODEL FOR INTEGRATED
 CIRCUITS, Saburo Hojo, Hitachi.
 Saburo, (an original author of the Electronic Industries Association of
 Japan (EIAJ) I/O buffer modedling standard) gave an overview.  The proposal 
 originates from the Technical  Standardization Center, Committee on Semiconductor 
 Devices, I/O Interface Model Project Group.  The model is expressed as a network 
 and covers the IC Buffer and Package.  Its advantage are that the transistor 
 descriptions are in a table form to protect process information, and the 
 network descriptions can show details including power/ground circuitry
 for bounce analysis.  Saburo showed networks and examples of MOS one, two
 and three dimensional table formulations.  A real construction example was
 shown for a 16M DRAM in a TSOP 50 pin package.  Waveform tables to drive
 the gates were derived from simulation.  The power/ground connections were
 derived from an RC network from the physical layout.  The MOS transistor
 table and parameters were derived from simulation results.  The package
 was derived from the layout as an LMRC network (with coupling).  
 
 Saburo noted the size of the model as 460k bytes and broke down the lines 
 needed: I/O buffer Network (36), Waveforms to Output Buffer (283), Power/
 Ground Network (5428), Table Model (2080), Package Network (4639).  It
 currently takes one week to construct manually.  

 Stephen Peters asked how fast the EIAJ model simulates, and if any SPICE
 vendor support the table driven MOS transistor descriptions.  Saburo replied
 that the simulation speed depends on the size of the model (the 460K byte
 example simulated no faster than a full spice model) and that Metasoft is
 planning on supporting the table driven MOS descriptions.
 
 Concerning future work, Saburo noted some current limitations in the format.  
 Version 1.0 of the draft is expected September 1997 and final approval is
 planned December 1997 by EIAJ.
 
 (Saburo also has generated Hitachi IBIS models for customers.)

 SIMULATOR ALGORITHMS, Bob Ross, Interconnectix 
 Bob showed samples indicating that we need to know what is inside the model
 since simulator algorithms may be different concerning Ramp based models
 and Waveform table based models.  Bob showed by a simple example that there
 are a number of choices based on linear (ramp) transitions to simulate the
 data - all giving different results.  The implied IBIS model topology
 corresponds to a Current-based model, but its dual corresponds to a Voltage-
 based model.  Non-linear transitions can be derived from Waveform information 
 to give better fits corresponding to an IBIS reference topology.  Other 
 internal details such as C_comp handling, ramp rounding, and package details
 may be handled differently among simulators.  So, at the detailed level, IBIS
 models probably will be treated differently by simulators.  Even with these
 differences, the accuracy by all simulators has still proven to be sufficient
 for general board level analysis situations where IBIS models are very 
 suitable. 
 
 C. Kumar added some discussion about using power and ground current table
 information to improve accuracy.  More information can always be used.  He
 also noted that reactive elements in the *_fixture and *_dut should be 
 avoided because they lead to numerical difficulties.  C_comp handling, while
 needed, also leads to dV/dt numerical difficulties (spikes) since derivatives
 are handled using discrete time step algorithms.

 EIAJ IC PACKAGE MODEL STANDARDIZATION ACTIVITIES, Norio Matsui, Applied 
 Simulation Technology, Ltd.
 Norio stated that under the Technical Standardization Center exists the 
 Committee on Semiconductor Packages, Package Electrical Characterization
 Project Group.  This group consists of 18 members, headed by Hitachi, and
 has had six monthly one-half day face-to-face meetings.  Norio showed some
 preliminary research results of simulator and simulation investigations.
 Data book L and C parameters are undefined or too high.  Concerning radiation
 noise, 30% to 70% of PCB surfaces are covered with IC packages.  Radiation
 can be generated from horizontal lead frames, vertical lead frames and 
 power/ground planes. Both electrical and physical models are required.
 
 Model standardization for ceramic packages, plastic packages and MCMs for
 memory models is considered.  A BGA structure would include signal traces,
 ground and Vcc planes.  These would be described via nodal networks in
 the EIAJ table format.  Additional information includes frequency and 
 position of planes.  Among the rules, avoid using node 0 or GND/gnd - 
 ground should be floating.  Self R, L, C, (G) for lead frames and planes
 are provided, and mutual coupling for L and C for long distances is not
 necessary.  So the full LCR matrix is not needed.  Tools need to extract
 the user models from the total model.  Tools need to extract macro-models
 from segmented, detailed network models for simplified modeling for a large
 number of pins.  Under discussion is how to make models for huge pin counts
 for signal and power/grounds.  All pin model is still required.  Some
 techniques include using symmetry, limiting coupling range, connect all or
 grouped ground/power pins for BGA, and macromodels by one segment per pin
 at a frequency.
 
 Norio showed simulation results to complement Saburo Hojo's presentation 
 based on the EIAJ Table Spice and package model using an Applied Simulation
 Technology implementation.  The schedule tracks the I/O IMIC activity with
 June 1997 for Draft 1.0 with examples, September 1997 for Draft 2.0, and EIAJ
 approval of Level 2 (SI and PI) planned for December 1997.

 IBIS FORUM I/O BUFFER MODELING COOKBOOK, Stephen Peters, Intel Corp.
 Stephen passed out Revision 2.0, June 11, 1997 draft of the above document 
 and reviewed its contents.  It extends the cookbook to Version 2.1 levels
 and contains tables to clearly show the key components of IBIS models and
 the required/optional keywords and subparameters.  The sections are
 Introduction, Pre-Modeling Steps, Extracting the Data, Putting the Data Into
 and IBIS File, Validating the Model, Correlating the Data, and Resources.
 Five Examples are proposed and several individuals volunteered to provide
 them.  Stephen asked for feedback including comments from EDA vendors on
 the recommended test loads for waveforms.

 AR - The following people have volunteered to supply examples
  Steve Kaufer/Hyperlynx -- Example 1
  Arpad Muranyi - Example 2
  Stephen Peters - Example 3 

 AR - D.C Sessions.  Supply a paragraph or two explaining the best way to
 modify a SPICE transistor model to get realistic power and ground clamp 
 information

 AR - Bob Ross.  Supply the text for the section "Diode Transient Time Data"

 AR - Syed Huq.  Review and expand (if necessary) Section 3.3. on "Obtaining
 I/V and Switching Information via Lab Measurment".

 AR - Everyone who received a copy review the document and provide comments
 to Stephen Peters (address at the end).

 ELECTION OF EIA/IBIS OPEN FORUM OFFICERS FOR 1997-1998.
 The following Individuals were nominated and elected to serve as Committee
 officers:  Bob Ross, Chair, Syed Huq, Vice Chair, Stephen Peters, Secretary,
 and Jon Powell, Librarian.  They are listed at the end of these minutes.
 
 Patti Rusher presented EIA/IBIS Committee appreciation plaques to Jon Powell,
 Syed Huq, and Bob Ross for service for the 1996-1997 term.

 TECHNICAL SESSION
 After a break for lunch the technical session focused on final consideration
 of the Open BIRDs and the Ratification of IBIS Version 3.0 with modifications
 discussed at the meeting.

 BIRD41.7 - MODELING SERIES SWITCHABLE DEVICES
 Bob Ross proposed a syntax change for discrete elements changing [R L Series]
 to [Rl Series], [R C Series] to [Rc Series], and [L C Series] to [Lc Series].
 This was to make the syntax clearer and reduce underbar and space
 combinations.  This was approved.

 Also Bob Ross indicated that another reference in IBIS in the first paragraph
 under the [Model] keyword needs to be changed in two locations: [Pin] is
 changed to "[Pin] and [Series Pin Mapping]".  This was approved.

 Bob Ross also gave a presentation SERIES SWITCH MODELING TESTS showing the
 models and simulation results under Spice.  A crossbar switch model was shown.
 Drain Current as a function of Source Voltage for fixed Drain to Source
 voltages were shown.  This is another way of showing resistance as a function
 of voltage.  The tables show that this effective resistance changes as the
 drain to source voltage increases.  Because of the values of the models, using
 a 1/2 volt or 1 volt basis provides reasonable accuracy approximations.  All
 of the data assumed a linear relationship between voltage across the component
 and corresponding drain current.  While a two table implementation using a
 quadratic fit was tested, Bob reported did not have the predicted accuracy 
 improvement to justify recommending it.

 Under loaded conditions, the proposed [Series MOSFET] table model showed
 excellent correlation with the Spice Model for a single MOSFET transistor.
 A reflected wave circuit was used for the remaining tests to force the table
 model to operate in the forward and reverse directions over its entire range.
 Again good correlation was shown, with the major deviation being in the high
 impedance range.  The model supports moving the Vcc to 4.3 V for 5 V to 3.3 V
 interface applications.

 A full Spice model for the TI 74CBT3383 was tested against the proposed 
 IBIS simulation.  This switch has effective ground clamps and capacitances
 at both terminals.  The Spice simulation also showed agreement for 3.3 V
 inputs using the reflected wave test circuit.  The 5 V input showed more
 of a mismatch.  However, D.C. Sessions and others indicated that the 
 results were as good as could be expected since there were some very non-
 linear capacitances when the drain and source node voltage differences
 become equal.  The results also showed an effective power clamp, even though
 the DC extraction shows no such clamp.  However, this may also be second
 order effects associated with the non-linear behavior of the actual Spice
 Level 13 model.  In this region, the results were still deemed satisfactory
 considering the numerical uncertainties with high impedance regions.  Bob
 stated that the 4 pF capacitances were found by experimental matching, the
 data book indicates 6 pF.

 As part of the subsequent discussion, Stephen Peters requested a fully
 formatted IBIS example.  A vote on BIRD41.7 with changes was conducted.

 BIRD41.7 was unanimously approved with the above changes.

 AR - Bob Ross post BIRD41.8 documenting these changes and include the
 changes in the revised IBIS Version 3.0 [Done]

 AR - Bob Ross submit an example of a Series MOSFET component.

 BIRD43 - COMPONENT TEST POINT SUBPARAMETERS
 Bob Ross briefly introduced BIRD43 as an extension of the [Component] 
 keyword by adding two subparameters for timing and signal integrity 
 testing location (Die or Pin).  The primary motivation is that ASICs tend
 to provide specifications at the Die rather than the (default) Pin location.

 BIRD43 was approved by unanimous vote.

 BIRD44 - INTERPRETATION OF MIN/MAX/WEAK/STRONG DATA
 Bob Ross introduced BIRD44, recently submitted by Andy Ingraham.  With few 
 exceptions the Committee requires that BIRDs to be submitted at least two
 weeks prior to voting to give everyone an opportunity for review.  BIRD44
 does not change any technical content but is intended to provide clarity of
 the min and max tables usage for [Model]s.  Since the content is mostly
 editorial, BIRD44 can be considered for IBIS Version 3.1 where a number of 
 suggested editorial changes will be considered.

 Also, Bob indicated that maybe a note in the front may be an alternative way
 of dealing with the issue while retaining much of the established min/max
 notation that currently exists in models.

 BIRD42.2 - MODELING CURRENT WAVEFORMS
 Based on a suggestion by D.C. Sessions, Bob Ross deferred discussion of
 BIRD42.2 after considering the other BIRDs because of some controversial
 aspects.

 BIRD42.2 introduces keywords under the [Rising Waveform] and [Falling
 Waveform] tables for tables describing the ground and power currents of the
 buffer.  These tables give more detail regarding actual current flow for the
 buffer for bounce calculations and potentially provide more information for
 accurate modeling of buffer transitions.  C. Kumar drew some diagrams to
 support the position for more accurate modeling.  D.C. Sessions was concerned
 that this might not be the case and that the additional information might
 either be redundant or contradictory.  Much discussion and debate followed.
 One question was whether just a shunt current between rails was all that was
 needed.  Some other questions were raised regarding other paths - such as the
 input current glitch and possible capacitance and diode paths that may enter
 into the distribution.  It became clear that we could not reach a consensus.
 Werner Rissiek proposed that we not vote on BIRD42.2 and that it not be
 included in IBIS Version 3.0.

 The committee agreed to keep the editorial changes, example changes and
 recommendation text additions to [Rising Waveform] and [Falling Waveform]
 that are documented in BIRD42.2 as an editorial change to IBIS Version 3.0. 

 Regardless of the outcome, Bob proposed that BIRD42.2 keywords be changed to
 reflect the rail to which they are attached.  [GND Current] would be changed
 to [Pulldown Reference Current] and [POWER Current] would be changed to
 [Pullup Reference Current].  The Committee agreed with this change.  This
 would allow extensions to the other rails if needed and allow descriptions
 for ECL models to be consistent within the IBIS conventions.

 AR - Bob Ross post Bird42.3 documenting these changes.  Also delete the 
 keywords [GND Current] and [POWER Current] from IBIS Version 3.0.  [Done]

 AR - D.C. Sessions and Kumar get together and provide an example showing
 where the rising and falling waveform tables do not result in correct
 results.

 Bob mentioned that that while we have traditionally made the IBIS Version
 X.1 an editorial correction release, we were not bound by this convention.
 BIRD42.3 can be a candidate for inclusion in IBIS Version 3.1.  We also
 could issue an IBIS Version 3.2 as the final editorial correction since the
 parser development is expected to take a long time (one-half a year or more).

 DYNAMIC CLAMPS AND OTHER ITEMS
 Arpad Muranyi has not yet prepared a BIRD on this area.  However, since
 it relates to actual implementations, it could also be considered as a
 possible addition to IBIS Version 3.1 if the proposal is approved.

 Stephen Peters felt that the dynamic ranges within IBIS were unnecessarily
 large for some open configurations such as GTL devices with 3.3 V supplies,
 which are terminated 1.2 V or 1.5 V and have a reduced voltage swing.  Some
 notes could be made in the Cookbook or proposed as an editorial revision
 of IBIS Version 3.0 via the BIRD process.

 VERSION 3.0 RATIFICATION
 After the above consideration and resolutions of BIRD41.8 and BIRD43, Bob
 Ross asked for a ratification vote on IBIS Version 3.0 with the discussed
 modifications.

 IBIS Version 3.0 was unanimously ratified as modified.  Bob will make the 
 agreed upon changes and a few other minor corrections he discovered and will
 put the text on vhdl.org under /pub/ibis/ver3.0.  This will provide the
 baseline for IBIS Version 3.1 discussions.  Version 3.0 is not suitable for
 formal EIA and ANSI ratification.  However, it does formally endorse the
 newly approved functionality and syntax that has been under discussion
 for several years.

 D.C. Sessions asked for a grammar for IBIS.  Bob mentioned that he had 
 helped generate an unofficial BNF grammar for IBIS Version 2.1 and will 
 generate an update for Version 3.0.  He will put in the ver3.0 subdirectory.

 AR - Bob Ross generate the approved IBIS Version 3.0 document from the
 Pending document and the approved BIRDs and changes of this meeting and
 post the document on vhdl.org.

 AR - Bob Ross generate and post a BNF for IBIS Version 3.0

 Chris Rokusek asked what the parser status was.  With Version 3.0 ratified,
 Bob now has a document which parser development work can be contracted.

 AR - Bob Ross contact Paul Munsey concerning IBIS Version 3.0 parser
 development.

 FINAL ITEMS
 Steve Kaufer did not need to lead the scheduled discussion on examples for
 IBIS based on recent reflector e-mail.  Adequate discussion already occurred
 with the IBIS Cookbook presentation.

 Syed Huq raised the question concerning whether the IBIS Version 3.1 should
 have better graphics, and perhaps should be a formatted document rather than
 an ASCII document with character pictures.  Word or HTML formats could be
 considered.  This will be a subject for further discussion.

 Stephen Peters volunteered to be involved with the editorial cleanup activity.

 Because of holidays and people being on vacation, the next teleconferencing
 meeting was scheduled on Friday, July 11, 1997.

 NEXT MEETING:
 The next meeting is on Friday, July 11, 1997, 8:00 A.M. to 9:55 A.M.  
 ==============================================================================
				       NOTES
 
 IBIS CHAIR: Bob Ross (503) 603-2523, Fax (503) 639-3469
	     [email-masked]
	     Modeling Engineer, Interconnectix
	     10220 SW Nimbus Ave, K4, Portland, OR 97223

 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785
	     [email-masked]
	     Staff Applications Engineer, National Semiconductor, M/S A-2595
	     2900 Semiconductor Drive, Santa Clara, CA 95052
 
 SECRETARY:  Stephen Peters (503) 264-4108, Fax: (503) 264-4515
	     [email-masked]
	     Senior Hardware Engineer, Intel Corporation
             M/S JF1-56
	     2111 NE 25th Ave. 
             Hillsboro, Oregon 97124-5961

 LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
	     [email-masked]
	     Senior Scientist, Quad Design/Viewlogic
	     1385 Del Norte Rd., Camarillo, CA 93010
  
 This meeting was conducted in accordance with the EIA Legal Guides and EIA
 Manual of Organization and Procedure.
 
 The following e-mail addresses are used:

   [email-masked]
       To join, change, or drop from either the IBIS Open Forum Reflector
       ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
       or both.  State your request.

   [email-masked]
       To obtain general information about IBIS, to ask specific questions
       for individual response, and to inquire about joining the EIA-IBIS
       Open Forum as a full Member.

   [email-masked]
       To send a message to the general IBIS Open Forum Reflector.  This
       is used mostly for IBIS Standardization business and future IBIS
       technical enhancements.  Job posting information is not permitted.

   [email-masked]
       To send a message to the IBIS Users' Group Reflector.  This is 
       used mostly for IBIS clarification, current modeling issues, and
       general user concerns.  Job posting information is not permitted.

   [email-masked]
       To report ibischk2 parser bugs.  The Bug Report Form Resides on
       vhdl.org in /pub/ibis/bugs/bugform.txt along with reported bugs.

 Information on IBIS technical contents, IBIS participants, and actual
 IBIS models are available on the IBIS Home page found by selecting the
 Electronic Information Group under:

   http://www.eia.org

 Check the pub/ibis directory on vhdl.org for more information on previous 
 discussions and results.  You can get on via FTP anonymous.
 
 "IBIS Spoken Here" placards are available from Jon Powell ([email-masked]) for 
 use at trade shows.
 ==============================================================================