Subject: Re: Proposed Golden IBIS Parser checks

From: [email-masked] (Weston Beal)
Date: Wed, 4 Nov 98 12:22 CST

> All,
> 
> I'd like to raise for discussion some enhancements I would like to have made
> to the Golden IBIS Parser.
> 
> My goal is to elevate the quality of IBIS models being produced by having
> IBISCHK perform additional sanity checks.  Many of the enhancements proposed
> below would detect flaws in models which render the model unusable for some
> simulations.
> 
> I am proposing that we enhance the Golden IBIS Parser instead of creating a
> separate utility since the Golden IBIS Parser already performs some sanity
> checking and it is already accepted as an authoritative tool.  (I have
> actually had some model creators refuse to fix models because "IBISCHK
> doesn't complain".)
> 
> Proposed enhancements:
> 
...
CHOP
...

These are good points, and if this can be done, I would very much like
the golden parser to generate a warning when the timing reference load
is not specified.  I get too many model without the load information,
making them nearly useless for timing verification.  Most IBIS authors
leave them out, because they don't know what the parameters are, and
the specification makes them optional (interpreted as "not needed").

> 
> I realize that some of these enhancements might need a BIRD to be issued so
> that the IBIS specification specifically mentions values that are illegal.
> 
> Regards,
> Matthew Flora
> Senior Engineer
> HyperLynx
> (425) 869-2320 PH
> (425) 881-1008 FAX
> [email-masked]
>

---

From: tomda <[email-masked]>
Date: Wed, 4 Nov 1998 16:00:59 -0800

There are many CMOS inputs that have a resistor to a third logic voltage 
level (not high or low) that will never have the same intercept.  That 
third logic level will change with Vcc.

Tom Dagostino

-----Original Message-----
From:	Kellee Crisafulli [SMTP:[email-masked]]
Sent:	Wednesday, November 04, 1998 2:03 PM
To:	[email-masked]
Subject:	Re: Proposed Golden IBIS Parser checks

Hi IBIS,

At 01:00 PM 11/4/98 -0700, you wrote:
>> >> 3) For non-ECL models, shouldn't the zero current voltage for the
Typ, Min,
>> >>    and Max columns in the Pullup or Pulldown V/I tables be the same 
(say
>> >>    within a microvolt)?  I suggest that a warning be generated if
they are
>> >>    not.
>> >Lots of technologies have zero-current intercepts inside of their
>> >rails.  ECL is only one of them; perhaps you've heard of TTL?
>
>> I think Matt is asking that the zero current intercept be the same for
>> typ,min,max  not that it be 0.
>
>Still wouldn't work.  TTL (to pick one) intercepts when the
>forward current through the base-collector junction equals
>the pulldown current through the collector-emitter path.
>This depends on the forward voltage of the base-emitter
>junction, the beta of the transistor, and the forward
>voltage of the collector-base junction as well as the
>predriver current to the transistor base node (also variable).
>The first three are dependent on process and temperature, and
>the last is also dependent on supply voltage.  IOW, the
>open-circuit Vol is going to be all over the place.

Excellent point DC!

Any ideas on how to do this that would work better are appreciated.
Did I mention it needs to be reasonably simply so it's not too hard
to write the test.  This is another common problem we see it would be nice
to smash with the golden parser.

---------------------------------------------------------
Have a great day....
Kellee Crisafulli at HyperLynx
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:[email-masked]>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------