Subject: Re: standard loads on 66 MHz PCI

From: "D. C. Sessions" <[email-masked]>
Date: Mon, 09 Nov 1998 13:01:02 -0700

Muranyi, Arpad wrote:
> 
> All,
> 
> I guess it is not impossible to come up with a fix to the IBIS spec to
> accommodate the various reference loads the PCI spec uses.  But, to answer
> someone's question, I have only seen this kind of multiple reference loads in
> the PCI spec. so far.  And, sorry, but I have no idea why it was done that
> way.

It actually maps into the requirements.  Min has to be guaranteed at light
load to avoid violating the zero hold time spec in the face of clock skew;
the light load is possible in onboard point-to-point connections.

The max is necessary to guarantee avoiding setup violation on a loaded bus.

> To further complicate things, think about this.  There is a separate min and max
> reference (test) load.  But what are you supposed to use if you want to run a
> typical simulation?  This makes me suggest that we should look into how to fix
> the PCI spec...

Fixing the PCI spec would be nice, (the 5v tolerant section has always
been ugly) and the timing is right since Intel has announced its end-of-life.
Less flippantly, it's probably too late.  The fool thing has a life of
its own now.  To get an idea, see how many 3.3v PCI systems you can find,
and then read the intro to the electricals where Intel announced that PCI
is intended to be a 3.3v bus but 5v is supported only as a transisition
path...

-- 
D. C. Sessions
[email-masked]

---

From: [email-masked] (Bob Ross)
Date: Mon, 9 Nov 98 14:57:30 PST

To All:

The IBIS Version 3.1 format could theoretically handle this
multiple test load situation by using the [Model Selector]
keyword to reference individual [Model] keywords containing
the same information except for the individually specified
test loads.  However, it is likely that the user would to
manually manage the analysis for testing the design corners.

Bob Ross
Interconnectix/Mentor Graphics

> Date: Mon, 09 Nov 1998 13:01:02 -0700
> From: "D. C. Sessions" <[email-masked]>
> Reply-To: IBIS Mailing list <[email-masked]>
> To: IBIS Mailing list <[email-masked]>
> Subject: Re: standard loads on 66 MHz PCI

---

From: "Muranyi, Arpad" <[email-masked]>
Date: Mon, 9 Nov 1998 15:05:00 -0800

That is ture, but the simulations would still have to be run twice...
Arpad
============================================================================
==

To All:

Bob Ross

> > someone's question, I have only seen this kind of multiple reference
loads 
in

> > To further complicate things, think about this.  There is a separate min
and
max
> > reference (test) load.  But what are you supposed to use if you want to
run 
a
> > typical simulation?  This makes me suggest that we should look into how
to 
fix

---

From: Andrew Ingraham <[email-masked]>
Date: Tue, 10 Nov 1998 07:59:49 -0500

Greg Edlund asked:

> How new are these Tval loads?  Version 2.2 (currently in draft, dated
> June 
> 1998)?

Much older than that.  They became official at least as early as June
11, 1995, and were available in preliminary form a year before that.
See Version 2.1, note 2 under Table 4-6, on page 134; and Figures 7-6,
7-7, and 7-8 on pages 227-228.  Parts for the 5V PCI signaling
environment use the two simple "lumped" test loads (0pF and 50pF), as
these were already in place and in use for Version 2.0 (1993).

Arpad Myranyi said:

> The test load (and waveform) doesn't match the driver's real load
> (and waveform) ...

But I think they do!  They are more realistic than the conventional 50pF
lumped test load.

The minimum load represents the limiting case of two PCI devices on a
motherboard with no expansion slots and short etch; a strictly local
bus.

The maximum load represents that first nanosecond or so on a long bus,
before the incident edge bounces off the open ends and returns to the
driver.  The waveform you get is ... well ... it's what you really get!

Regards,
Andy Ingraham