Subject: IBIS Open Forum Minutes 15 Oct 1998

From: Matthew Flora <[email-masked]>
Date: Wed, 21 Oct 1998 09:27:46 +0000

DATE: 10/21/98

SUBJECT: 10/15/98 EIA IBIS Summit Meeting Minutes
   
VOTING MEMBERS AND 1998 PARTICIPANTS LIST:
AMP                            (Martin Freedman) 
Applied Simulation Technology  Norio Matsui, Raj Raghuram*
Cadence Design (& UniCAD)      C. Kumar*, Don Telian, Patrick Riffault, 
                               Craig Lewis, Greg Fitzgerald, Paul Galloway,
                               Patrick Dos Santos, Catherine Weiss, 
                               Alain Tribaudot, Geoffrey Ellis,
                               Todd Westerhoff*, Ken Willis*
Compaq                         Shariq Rahma, Jeff Chu, Bob Haller*, 
  (Digital Equipment Corp.)    Doug Burns*, Steve Coe*
Cypress                        Bruce Wenniger
H.A.S. Electronics             Haruny Said
Hewlett Packard (EEsof, etc.)  Karl Kachigan, Henry Wu, Paul Gregory,
                               Brenda Arena*
High Design Technology         Razvan Ene
HyperLynx                      Kellee Crisafulli, Matthew Flora, Gene Garat*,
                               Dave Kohlmeier*
Incases                        Olaf Rethmeier, Scott Jacobson,
                               Werner Rissiek
Intel Corporation              Stephen Peters*, Arpad Muranyi, Frank Kern*,
  (& formerly NCR)             Will Hobbs*, Prakash Radhakrishnan,
                               Mohammed Hawana, Martin Chang, Dave Moxley,
                               Tim Schreyer*
LSI Logic (Symbios Logic)      Larry Barnes
Mentor Graphics (Zeelan,       Bob Ross*, George Opsahl, Mark Noneman,
  Interconnectix, etc.)        Tom Dagostino, Karine Loudet, Jean Oudinot,
                               Manuel De Almeida, Stephane Rousseau, 
                               Neven Orhanovic, Mohamed Mahmoud, Kevin Cohan*
Mitsubishi                     Tam Cao
Motorola                       (Ron Werner)
National Semiconductor         Cheng-Yang Kao, John Goldie, Ikchang Song,
                               Milt Schwartz
North East Systems Associates  Edward Sayre*, Kathy Breda*, Michael Baxter*
  (NESA)                       Jon Green*, Jinhua Chen*
NEC                            (Hiroshi Matsumoto)
Quantic EMC                    (Mike Ventham)
Texas Instruments              Thomas Fisher, Harvey Stiegler,
                               Vincent Chang, Jean-Claude Perrin,
                               Peter Forstner
Thomson-CSF                    Jean-Marc Claveau, Laurent Duzaic,
                               Saverio Lerose, Benoit Meyniel,
                               Jean Lefebvre  
Viewlogic                      Jon Powell*, Chris Rokusek, Guy de Burgh, 
                               Gary Mandel
VeriBest                       Ian Dodd, David Weins, Ian Gabbitas
VLSI Technology                D.C. Sessions
Zuken-Redac                    (John Berrie) 

OTHER PARTICIPANTS IN 1998:
3Com                           Steve Miller*
3Dfx Interactive               Ken Wu*
A.T.Sinker                     Tony Sinker*
Actel                          Eric Tardif, Emmonvelle Gaudin 
Aerospatiale                   Lionel Dreux, Claude Huet
Alcatel (Bell, Espace, etc.)   John Fitzpatrick, W. Temmerman, 
                               Laure Bessettes, Jean-Claude Pourtau,
                               Daniel Peron
ALS Design                     Yves Mouquet
Ansoft                         Eric Bogatin
Apple                          Fred Floresca, Danny Itani
Apteq Design Systems           Dan FitzPatrick 
Atmel                          Ali Baktashian
Avanti                         Nik Bannov
CERN                           Olivier Clere, Jean-Michel Sainson, 
                               Rudi Zurbroken
Cisco Systems                  Syed Huq, Sergio Camerlo, Irfan Elahi
Corning                        John Nieznanski*
Crucial Technology             Rathna Reddy
DIVA Corp                      Tieng Nguyen*
Dynamic Research Corporation   Mike Walsh*
EIA                            Patti Rusher*
EMC                            Fawn Engelmann, Fabrizio Zanella*
ENST, Paris                    Jean-Jacques Charlot
European CAD Standardization   Adam Morawiec
  Intitiative (ECSI)
Fairchild Semiconductor        Peter LaFlamme*
Focus Technology               John Salzillo*, Gary Brophy*,  Mike Arieta*,
                               Jim Skane*
IBM                            Richard Steinle, Kevin Jackson, Greg Edlund*
InRange                        Elliot Lipin*
Intracon Design Ltd.           Derek Laidlaw
Philips Semiconductor          Todd Andersen
Rockwell Semiconductor         Tim Gilbert*
Scottish Electronics           Robert Easson
  Manufacturing Center (SEMC)
Seagate                        Vanessa Howard
Signal Integrity Software      Barry Katz*
SGS-Thomson                    Philippe Lefevre
Siemens                        Gerald Bannert, Bernhard Unger, 
                               Christian Marot, Miguel Hernandez,
                               Gil Russell
SSEI                           Tom Hawkins
Stratus                        Bruce Heilbrunn*, Steve Mango*, Lewis Steiner*, 
                               Karla Eignor*, Rich Newell*
Summit Computer Systems        Bob Davis
Sun Microsystems               Lam Dong, Kevin Ko, Tay Ansari*, Ken Weiss*
Symmetry                       Andy Hughes
Tektronix                      Nassrin Ghahyasi
Teradyne                       Michael Khusid*
TranSwitch                     Bill Todd*
TRILOGIC                       Joe Socha*
Ultratest International        Chris O'Connor
Xilinx                         Susan Wu

In the list above, attendees at the meeting are indicated by *.  Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are
as follows:
  
  Date               Bridge Number     Reservation #    Passcode
  November 6, 1998   (916) 356-9200    2-275145         3938931
  Wednesday, December 7, 1998 IBIS Summit Meeting - No Teleconference

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas 
out 7 days before each Open Forum and meeting minutes out within 7 days 
after.  When you call into the meeting, ask for the IBIS Open Forum hosted 
by Will Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -----------------------------------

IBIS SUMMIT MEETING SUPPORT
The IBIS Summit Meeting was held at the Boxboro Woods Holiday Inn in 
Boxboro, Massachusetts.  Thanks to Kathy Breda and the staff of North East 
Systems Associates (NESA) for taking care of the arrangements and to the 
IBIS Users group and the sponsors of the meeting for providing additional 
support and funding.  The sponsors are listed:

  Applied Simulation Technology
  Cadence Design Systems
  Compaq Computer Systems
  EMC Corporation 
  Focus Technology 
  HyperLynx
  North East Systems Associates

Thanks to the following groups for showing equipment and demonstrations 
supporting IBIS model processing:

  Applied Simulation Technology - Raj Raghuram
  Cadence Design Systems - Todd Westerhoff
  HyperLynx - Dave Kohlmeier and Gene Garat
  Interconnectix/Mentor Graphics - Kevin Cohan
  Viewlogic - Jon Powell
  IBIS Users Group (with equipment from Hewlett Packard)

About 50 people representing 29 organizations participated in a meeting 
packed with content.  The food, refreshments, and the facilities were 
excellent.  The Minutes here just briefly note some of the content of the 
meeting and some discussion.  Most of the presentations and related 
documents will be uploaded at:

  http://www.eda.org/pub/ibis/summits/oct98.

INTRODUCTIONS AND BUSINESS 
- Bob Ross (Mentor Graphics) and Ed Sayre (NESA)
Bob Ross opened the meeting and introduced the officers, sponsors, and 
people doing demonstrations.  The participants introduced themselves.  Bob
noted that there was good representation from the semiconductor, EDA vendor
and user sectors.

Ed Sayre noted that a strong IBIS Users Group has put in a lot of effort to
propose a method of quantifying the quality of IBIS models.  Ed showed a 
three-way linkage between

  IBIS models of chips, transmission lines, connectors, etc;
  IBIS software, syntax checker, IBIS to SPICE, SPICE to IBIS, training; and
  simulators and circuit prediction software.

He stated that IBIS Users and their missions are central to IBIS.

Bob Ross reviewed some ongoing IBIS Open Forum activities.  The first IBIS
Version 3.2 parser was distributed to the 12 funding companies.  Several
BIRDs exist for ratifying IBIS Version 3.2.  Bob noted that the ratification
of IEC 62014-1 has been delayed since the IBIS Version 2.1 document had not 
been forwarded to the IEC Central Office for distribution.  Patti Rusher 
properly forwarded the document, and it will be sent out for Committee Draft 
for Vote (CDV) on a fast track basis which should take about a year.

Bob along with Will Hobbs (past Chair of the EIA IBIS Open Forum) and
Stephen Peters (Vice-Chair.), both from Intel, and some model and simulator 
development people from Mentor Graphics had recently met with Dr. 
Hideki Fukuda, Chair of the EIAJ committee on I/O Model for Integrated 
Circuits (IMIC).  Ed Sayre and the staff at NESA had also met with Dr. 
Fukuda.  The agenda was to get more information and to investigate whether 
IBIS and IMIC can and should be merged or linked in some manner.

Bob noted that the next IBIS Summit meeting is being held in San Diego, CA,
and is co-located with the JEDEC JC-16.2 (Modeling and Test) committee
meeting.  The meeting, originally proposed by D.C. Sessions is scheduled for 
December 9, 1998.  This should provide more communication and interaction 
between IBIS members and people involved with semiconductor development. 
Information will be sent out shortly.

[Added note - this meeting is now being changed to December 7, 1998.]

A formal business item was to consider a proposal for IBIS Open Forum 
Associate Sponsorship of DesignCon99.  The benefits include a meeting room
and refreshments for the IBIS Summit Meeting on February 1, 1999, a 10x10
booth at DesignCon99, a suite, publicity, VIP registration with 10%
discount, and other perks.  DesignCon99 would be able to use the IBIS 
reflector lists for advertising DesignCon99.  Patti checked that this was
acceptable with EIA.  The group approved accepting the Associate
Sponsorship proposal.

[Administrative note - H.A.S. Electronics is now an official EIA IBIS Open 
Forum Member.]

IBIS TRAINING 
- Joseph Socha (TRILOGIC)
Joe Socha gave a quick run through of an IBIS training tutorial he is 
developing.  Joe took some material from a number of publicly available
documents and integrated them into a training program which could be
merged with vendor-specific programs.  The content included reviewing the
keywords for I/V data and ramp information within Version 1.1.  He would 
like feedback on the content and material.  Joe's plan is to enlarge the 
presentation into a 4 hour class and is considering offering it at
DesignCon99.

IBIS CONNECTOR MODELS: WORKING GROUP STATUS 
- Fabrizio Zanella (EMC Corporation)
Fabrizio Zanella gave an interim status.  The Connector Working Group has
had participation from 9 individuals from 7 companies and meets several times
a month.  The goal is to draft an IBIS Connector BIRD to define single line
and multiline connector models.  About 25 new keywords are defined that
support connectors derived from 2D and 3D field solver extractions.  Both
mated and unmated configurations will be supported.  Connectors can support
several cascaded L,C matrix sections.  A smaller section (designated a 
swath) can be used which is repeated for the entire connector.  One option
includes providing a JPEG file to show the connector.  The Group plans to 
investigate T stubs and loops and issue the BIRD by January 1999.  The Group 
also is seeking funding for parser development.

BEHAVIORAL/IBIS MODELING OF A FET BUS SWITCH USING CADENCE TOOLS
- Tay Ansari (Sun Microsystems)
Tay Ansari discussed a series of experiments to model FET bus switches.
After discussing some FET theory, Tay presented several modeling approaches
for FET switches:  Series (5 ohm) resistor, Voltage Controlled Resistor,
I-V Tables/Conditional Statements, and IBIS 3.0 format.  He also showed
the model for parasitic elements.

Using a criteria that he expects behavioral simulations to overlay with
SPICE simulation results, Tay then inserted the FET switch models in a 
multiboard test circuit and showed the results.  All cases showed general
agreement, but the table/conditional approach seemed to give the closest
correlation.  He did not test the IBIS Version 3.0 approach directly, but 
considered it a format variation of the table approach.  He recommends using
two-dimension tables for best accuracy relative to SPICE simulation.

IBIS ACCURACY SPECIFICATION 
- Robert Haller (Compaq Computer Corporation)
In the presentation, Bob Haller reviewed the contents of the draft document 
and its rationale.  The draft IBIS Accuracy Specification document was also 
provided.  To limit the scope of the project, the document focused on IBIS 
Version 1.1 keywords and subparameters and corresponding test setups for 
extractions.  The goal is to provide quantitative metrics which correlate 
hardware measurements to IBIS simulations.  This can be used as a quality 
standard for IBIS datasheets.

A Subcommittee of six people worked on the proposal since December, 1997
and also worked on the test configurations for checking IV data, test load
waveforms and capacitance.  The correlation metrics include timing and 
voltage deltas, documentation of monotonic behavior, curve overlay and
curve envelope correlations, and capacitance differences.  Four correlation
levels take into account these cases:  Random Sample with no SPICE model
available, Random Sample with SPICE model available, Known typical sample
with SPICE model available, and Known corner samples with no SPICE model
required.  The goal is to produce a finished Specification by DesignCon99.

IBIS TEST BOARD 
- Peter LaFlamme (Fairchild Semiconductor)
Peter LaFlamme followed the presentation by discussing the test board itself.
It was designed for measuring DC IV tables, extracting AC waveforms for
various test loads and measuring capacitance.  It could be used for creating 
IBIS models from sample silicon.  The schematics and layout are now available,
and the plan is to demonstrate to board at DesignCon99.

The test board accommodates a 16244 function in a 48 lead TSSOP package.
It houses two devices, one to set up I/V data collection and input/output
capacitance, and the other to do AC measurements.  Also, there are test
strips for transmission line characteristics and board traces and load
characteristics of board vias.  Examples of DC and AC tests were illustrated.
The AC waveforms include the transmission line terminated to Z0, standard
lumped timing test load, a lightly loaded transmission line, and a driver
driving a receiver of the same family.  Several methods to measure capacitance
are supported including frequency domain (LRC meter and capacitance bridge)
and time domain (TDR and pulse technique) methods.  Not measured are package
resistance (usually negligible, and package inductance).  More work is needed
to characterize the board.  However, the complete package includes schematics,
Gerber files, and a parts list.

IBIS CASE STUDIES: COMPARISONS OF SIMULATIONS 
- Fabrizio Zanella (EMC Corporation)
Fabrizio Zanella presented the results of case studies comparing IBIS 
model simulation, SPICE simulation and measurements.  Three cases were
presented:  Case 1: TTL signal, empirical, SPICE, IBIS simulation; Case 2:
SRAM signals: empirical, SPICE, IBIS; and Case 3: IBIS model comparison.

While there were differences due to a number of factors, Case 1 showed
excellent agreement on the 1.5 V ringback signal.  Case 2 showed similar
undershoot between IBIS simulations and measurements.  However, there were
some unaccounted differences in waveforms.  Case 3 showed differences in
simulation waveforms between data sheet and SPICE 2 IBIS extracted models.
In general, Fabrizio concludes the SI simulators using IBIS models are
reasonably accurate, but beware of data sheet models.

COMPARISONS BETWEEN SPICE AND IBIS I/O DEVICE SIMULATIONS
- Jinhua Chen (North East Systems Associates)
Jinhua Chen compared results of SPICE and IBIS model simulations using the
Fairchild 74LCX16245 SPICE and extracted IBIS models.  Three Cases were
studied: Case 1: 50 ohm net with no termination, Case 2: Same net with a
25 ohm series resistance to dampen the overshoot, and Case 3: A 15 pF
capacitive load only.  In Case 1 at two clock frequencies, there was
good correlation between waveforms, but the IBIS simulation ringing was
about 20 percent larger.  Excellent correlation was obtained in Case 2.
Case 3 showed larger overshoot and undershoot using the IBIS models.
However, overall correlation was good with SPICE models.

TIPS AND TRICKS FOR CREATING IBIS MODELS 
- Jon Powell (Viewlogic Consulting Services)
Jon Powell provided many tips based on much experience developing IBIS models.
An important setup is to extract VT tables using 50 ohms to ground and 50 ohms
to Vcc.  Parasitics need to be eliminated.  The time domain extractions need
to be set up for maximum accuracy by controlling the Options settings in SPICE
and by doing the simulations for a long enough duration to capture the whole 
waveform.  Jon showed excellent, overlaying correlation between Spice
extractions and model simulations.  He pointed out a number of extraction
problems related to simulation time, Cdie, control options to converge,
unrealistic SPICE diode models, and the fact that some SPICE features are
not modeled.  Some difficulties with IBIS include: 100 point limitation,
the typ-min-max corners may not give the full range of corners, the LC
package model may be too simplistic, and rise time and high speed buffers
need more than just the transition time specification.  However, using
QA simulations with the complete model, Jon again showed overlaying
correlation.  He also showed a significant difference in results when he just
used the [Ramp] specification.

MODEL PROCESSING ALGORITHMS
- Bob Ross (Interconnectix/Mentor Graphics Corporation)
Bob Ross discussed some details in a prototype SPICE implementation of IBIS
done several years ago and sent on the IBIS reflector in October, 1997.  The
algorithm involved the transition between the high and low state tables by 
using multiplying Ku(t) and Kd(t) tables.  Some code details were shown for
one and two waveform based methodologies.  The K table extractions were based
on a feedback method which forced convergence to the correct solution using
the SPICE convergence algorithms.  Bob presented results which showed
excellent overlaying correlation between the original Spice waveforms and IBIS
model simulations and superimposed with the corresponding Ku(t) and Kd(t)
tables.  However, a one waveform based model for K(t) extraction showed some
simulation difference between the second waveform and the corresponding
simulation.

Bob also presented some aspects of the EIAJ IMIC 1, 2, and 3 dimensional 
table model.  The model does allow two independent waveforms that can be
extracted from within the Spice model for controlling the PMOS and NMOS
devices of an output stage.  However, the accuracy of this approach needs
to be validated since the table transistor models themselves are given
in terms of derived tables.

IBIS EVOLUTION AND ADOPTION
- Will Hobbs (Intel Corporation)
Will Hobbs gave a brief IBIS history and then issued the challenge for models 
and simulators to keep up with technology.  New challenges cause the subtler
effects (and their combinations) to become significant.  Accuracy work is
needed, and IBIS Version 3.X functionality needs to be adopted.  Future
developments need to be deployed more quickly.

Will shared a real case study experience where the combined effects of SSO,
coincident reflections with SSO, and noise margin erosion caused by
termination plane noise, routing topology, package routing, Vcc bypassing,
connector inductance, and sub-optimal ground return path all contributed
to a deep glitch.  Normally these are considered second order effects.  Will
described a recent modeling approach where the timing is taken from the
input of the driver to the output of the receiver for cleaner test points.
Such advances raise the question about how far the IBIS methodology can go
and what to do about addressing the emerging needs.  He speculated on some
alternatives including a more sophisticated input model, improved package
models, equation based models, and feedback.  He also speculated on a 
coexistence between structural and behavioral modeling (through an interface
which protects intellectual property).

TOOL CAPABILITIES NEEDED FOR DESIGNING 100 MHZ INTERCONNECTS
- Tim Schreyer (Intel Corporation)
Tim Schreyer summarized a presentation he gave at ASP DAC 98 in February 1998
in Tokyo, Japan.  He described the interconnect design challenges for the
Pentium(R) II processor based PCs.  The trends are moving to higher speeds
away from the CPU (e.g., AGP bus), and changing buses from "common clock" to
"source-synchronous" configurations.  The common clock goal is to minimize
interconnect delay, whereas the source synchronous goal is to match
interconnect delays and minimize uncertainty.  This requires more attention to 
second order effects.  Worse case design is harder to achieve.  Conventional
iterative or single pass approaches may not converge or take into account the 
resulting second order effects.  Tim proposes doing extensive Monte Carlo
simulations to understand the real effects and their interactions so that
realistic design rules can be developed.  One example considering variations
in length, capacitance, pulsewidth, rise and fall times, and odd/even mode
interactions showed a worse case design variation of 1.55ns when the effects
were added independently versus a computed worse case variation of 0.647ns
when the effects were treated together.

Such simulations create a lot of data.  Tim showed some graphical displays
using Microsoft Excel graphics and drop down macros to process the data.  
Various two and three dimensional plots and distributions quickly allow the 
user to see the worse case conditions among the interacting parameters.

Tim concluded by noting that thousands of simulations are needed for speeds
above 100 MHz.  Tools must be designed for batch mode processing and post
processing visualization.  Tim emphasized that the primary role is to
achieve understanding rather than automation.

ADJOURNMENT                
Bob Ross thanked the organizers for their efforts, and the meeting was 
adjourned for social interaction.

NEXT MEETING:
The next teleconference meeting will be on Friday, November 6, 1998 from 
8:00 AM to 10:00 AM.
==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            [email-masked]
            Modeling Engineer, Interconnectix BU of Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            [email-masked]
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-56
            2111 NE 25th Ave. 
            Hillsboro, Oregon 97124-5961

SECRETARY:  Matthew Flora (425) 869-2320, Fax: (425) 881-1008
            [email-masked]
            Senior Engineer, HyperLynx, Inc.
            17641 NE 67th Court
            Redmond, WA 98052

LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Scientist, Viewlogic (formerly Quad Design)
            1385 Del Norte Rd., Camarillo, CA 93010
 
This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  [email-masked]
      To join, change, or drop from either the IBIS Open Forum Reflector
      ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
      or both.  State your request.

  [email-masked]
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  [email-masked]
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  [email-masked]
      To send a message to the IBIS Users' Group Reflector.  This is 
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  [email-masked]
      To report ibischk2 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, 
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eia.org

Check the pub/ibis directory on eda.org for more information on previous 
discussions and results.  You can get on via FTP anonymous.
==============================================================================