Subject: RE: True or False?

From: "Muranyi, Arpad" <[email-masked]>
Date: Thu, 8 Oct 1998 11:54:00 -0700

Chris,

1)  Could you please point it out to me where the spec says that it is NOT 
allowed to have anything, except terminators on either side of the series 
device?  I don't recall reading that, but might have missed it.

2)  Our device which has this situation actually does sense the signal 
differentially, but since it never drives and the clamps are so far out from
the
signal swing, we didn't include a receiver model (even though I was
considering 
to do it).

3)  It may be sufficient to define [Series mapping] only if we didn't have a

receiver in the device.

Since we just made an IBIS model like that, you got my curiosity up, is it 
really illegal to do this?  By the way, it passed the parser, so if it is 
illegal, should the parser check for that?

Arpad
============================================================================
===

Arpad,

The Spec explicitly does NOT allow either side of the series device to 
be anything except terminator.  So how can you have a differential 
relationship (such as vdiff, or tdelay) between terminators (there's 
no sensing nor driving)?  I argue that if that component is not 
sensing the voltage difference on those pins then from the point of 
view of that component, the pins are not differential.

Note that if you want the nets to be connected differentionally, this 
would occur at a another component(s) on the board which would have an 
actual differential driver or receiver pair triggering an electrical 
association between the nets.

   I+ ---series--- O+

   I- ---series--- O-

Would it be sufficient to define the [Series mapping] only and not the 
[Diff Pin] relationship for the above case?

Chris

>
>
> I would vote for FALSE, because I could see them being used together in a 
> situation where you have a differential pair going into the chip and come 
> out on
> two other pins though a series model.  For example, let's make 
>
>     pin2 = diff_in+
>     pin3 = diff_in-
>     pin4 = diff_out+
>     pin5 = diff_out-
>
> where the ins and outs are "shorted" with metal. 
>
> In this case the [Diff Pin] keyword would associate pins 2-3 and pins 4-5
as 
>
> differencial, but the [Series Pin Mapping] keyword would connect pins 2-4 
> and
> pins 3-5.  Since the series models ignore the C_comp, the only way I can 
> enter
> the die capacitance into this picture is if I use the Terminator model on 
> each
> pin with nothing but C_comp in it. 
>
> This is how I can see the series and terminator models used together with 
> differencial pins.
>
> Arpad
> ==========================================================================

---

From: Chris Rokusek <[email-masked]>
Date: Thu, 08 Oct 1998 14:40:40 -0700

Arpad,

> device?  I don't recall reading that, but might have missed it.

Yes, from ver3_2.a.ibs, see 2nd paragraph under Other Notes, sentence #2
below.

<snip>
|     Keyword:  [Series Pin Mapping]
<snip>
| Other Notes:  If the model_name is for a non-symmetrical series model, 
|               then the order of the pins is important.  The [Series
Pin
|               Mapping] and pin_2 entries must be in the columns that
|               correspond with Pin 1 and Pin 2 of the referenced model.
|
|               This mapping covers only the series paths between pins. 
The
|               package parasitics and any other elements such as
additional
|               capacitance or clamping circuitry are defined by the
|               model_name that is referenced in the [Pin] keyword.  The
|               model_names under the [Pin] keyword that are also
referenced
|               by the [Series Pin Mapping] keyword must be either 'NC'
or
|               reference a [Model] whose Model_type is 'Terminator'. 
Thus.
|               for example, a Series_switch model may contain
Terminator
|               models on EACH of the pins to describe both the
capacitance
|               on each pin and some clamping circuitry that may exist
on
|               each pin.
<snip>

> signal swing, we didn't include a receiver model (even though I was

We've never had to model "paths through active devices" so that is where
the problem comes in where a single pin is defined as both a recevier
(customarily terminating the signal) and defined as a passive series
device to another pin.

However using only the [Series mapping] only will work A.O.K for us as
you state in #3 below assuming another component on the board joins
these two nets differentially.

> illegal, should the parser check for that?

The part I thought was illegal was the tying of a single pin together
with other pins using BOTH [Series Mapping] and [Diff Pin] since the
Series pins could only be terminators but the Diff Pins had to be
NON-terminators.

The parser should check.

It sounds like you may wish to propose a BIRD to allow this type of
thing in the future in which case we will enhance the capabilities of
our software to handle.  Its just never come up before.  There's always
been a buffer between Input and Output allowing us to decoupling the two
sides of the analysis.

Chris