Subject: JC-16 News

From: "D. C. Sessions" <[email-masked]>
Date: Thu, 17 Sep 1998 17:01:16 -0700

At this week's meeting of JC-16 and JC-42 (memory standards)
IBM presented the results of a survey of V/I curves (from IBIS!)
from several DDR SDRAM vendors.  Not a lot of agreement.
After some discussion there was a vote and it was decided to
go to ballot with an amendment to the SSTL specification to
include envelope specs -- in IBIS format.  Milestone.

The next day, the JC-42 committee agreed to go forward with
a detailed data-sheet format composition of the DDR SDRAM
standard, to incorporate several detailed electrical specs
including maximum and minimum pin capacitance.  The working
group has provisionally decided to publish the electrical
specs as a full IBIS model of a compliant memory part.

There was a GREAT deal of ignorance as to what IBIS is, what
it can and can't do, etc.  Many of the vendors doubted that
their engineering groups could produce a robust IBIS model
or verify a sample part against a specification model (sounds
like a business opportunity.)  I mentioned to several of the
vendors the posibility of acquiring the model generation tools
that Hyperlynx has so graciously made available.

One of the key functions of the DDR SDRAM spec depends on FET
switches for load isolation in large systems.  I pointed out
that IBIS can now model these devices, which was news to the
TI member there, one Mr. Stephen M. Nolan mailto:[email-masked]
who would like to hear from EDA vendors about support for
FET switch models; he'll pass on the contact to the interested
parties within TI.

Several of these issues will be coming up for vote at the joint
December meeting; I want to *strongly* encourage our members to
appear in force as it looks like a priceless opportunity to
educate some very influential people about IBIS at a time when
they are setting standards.  Not a bad marketing opportunity,
either, if it comes to that.

-- 
D. C. Sessions
[email-masked]