Subject: non-monotonicity

From: "fabrizio zanella" <fabrizio=[email-masked]>
Date: Thu, 6 Aug 98 16:59:42 -0400

IBIS experts/users:
I have a question regarding monotonicity of IBIS model curves.  I have 
encountered some logic IBIS models (clock drivers) which pass the golden 
parser (with some warnings), but do not pass the IBIS parser within my 
simulator.  The error I get is 
'the sum of the maximum clamp curves and the pullup curve is non-monotonic 
at -0.5 volts'.
I know for a fact that another  simulator we have in house parsed these 
models.  My question is, do some devices naturally have non-monotonic 
curves, and should an IBIS simulator accept this as a standard condition?  
Does anyone have experience modifying IBIS models to remove the 
non-monotonicity?

Thank you very much,
   Fabrizio Zanella
   Hardware Engineering
   email: [email-masked]
  (508) 435-1000 Ext. 4645
   Fax: (508) 435-8949
   EMC Corporation     
   171 South Street
  Hopkinton, MA 01748-9103

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From: "D. C. Sessions" <[email-masked]>
Date: Thu, 06 Aug 1998 14:52:43 -0700

> Does anyone have experience modifying IBIS models to remove the

Some drivers really do have non-monotonic curves.  We have some which
are protected against certain power states by having a line-operated
turnoff device on the driver gates, for instance; these have slope
reversals in their V/I curves.

-- 
D. C. Sessions
[email-masked]

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From: Jon Powell <[email-masked]>
Date: Fri, 07 Aug 1998 08:24:06 -0700

There are 3 issues (I am aware of) on monotonicity:

1) The measuring technique used in making models can sometime lead to
non-monotonicity through round off error (though this is usually so far
from the operating region that you don't care much).

2) The non-monotonicity could be extremely small and caused by small
noise oscillations in a spice simulation in an area that was supposed to
be flat.

3) The device is really non-monotonic in the operating range. If this is
true, this implies the device is using some active feedback technique.
If THIS is true then there is some implied delay in the feedback loop.
This feedback delay is not modeled by IBIS. The IBIS committee has
requested IC vendors to come forward with SPICE circuit examples of
devices that exhibit this effect so that we can figure out a behavioral
mechanism to describe it but (at least to my current knowledge) no such
circuit has been delivered. So your choices are: Ignore the
non-monotonicity (that is, remove it from the IV curve) or simulate with
the  non-montonicity but with no info about the delay. Depending on how
the circuit works, either of these could the best approach and I believe
different EDA vendors have made different decisions on what is most
appropriate in their simulators.

I think people who have problems with IBIS models showing this effect
should go ask their EDA vendors what is the appropriate solution for a
given model.

regards
jon

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From: "D. C. Sessions" <[email-masked]>
Date: Fri, 07 Aug 1998 09:27:00 -0700

> appropriate in their simulators.

Missed the request, Jon.  Here's one:

.SUBCKT	od_drvr	i	pad	vdd	vss
R1	pad	rpad	200
MN1	pad	ngate	vss	vss	NCH	L=0.5u	W=200u
MN2	ngate	rpad	vss	vss	NCH	L=1.0u	W=6u
MN3	rpad	vss	vss	vss	NCH	L=0.5u	W=40u
MN4	ngate	i	vss	vss	NCH	L=0.4u	W=50u
MP4	ngate	i	vdd	vdd	PCH	L=0.4u	W=120u
.ENDS	od_drvr

Use just about any 0.35u process models.  You'll find that the
V/I curve becomes nonmonotonic at higher voltages.

-- 
D. C. Sessions
[email-masked]