Subject: Characterization Conditions

From: Rob Eccles <[email-masked]>
Date: Thu, 17 Dec 1998 09:54:34 -0800

I have read with interest the latest version of the
IBIS cookbook.  It details recommended characterization
conditions for simulating TTL, ECL, LVCMOS, etc.  It 
does not contain recommended conditions for measuring
newer I/Os, i.e. SSTL, HSTL, GTL, LVDS.

What are the recommended simulation conditions for these
I/Os?

Rob Eccles
Xilinx
[email-masked]

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From: Stephen Peters <[email-masked]>
Date: Thu, 17 Dec 1998 12:24:51 -0800

Hello Rob:

   By "recommended characterization conditions" I assume you mean
the output loads/voltages use to extract V/T waveforms.  Because the
GTL/GTL+ outputs are open-drain, I would extract the V/T waveforms
using the rules for open drain buffers -- a load resistor to 
Vterm, with the value of Rterm and Vterm determined by the 
specification or part manufacturer.  As for the other standards,
if the driver uses a standard push/pull structure use the rules for 
standard CMOS or TTL (depending on the technology of the buffer).  
Remember: by taking the V/T waveforms with a load tied
to Vcc then to ground, one can isolate the turn-on, turn-off and 
overlap times of the pullup and pulldown structures, thereby allowing
the simulator to construct an accurate model of the driver.  This
model should be accurate, even if the driver application calls for
the output to be terminated to Vcc/2, or series terminated, or whatever.

          Regards,
          Stephen Peters
          Intel Corp.

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From: Rob Eccles <[email-masked]>
Date: Thu, 17 Dec 1998 17:57:28 -0800

Hi Steve,

Thanks for your prompt reply!  

After reading your response, and giving it some more thought,
it looks like SSTL and HSTL should use the same methodology
given in Table 1 for CMOS (from the 2.0X version of the Cookbook).

In practise, not all boards will use 50 Ohm loads.  How sensitive
are the IBIS models to termination resistance?  I would expect
this to be significant.

Regards,
Rob Eccles
Xilinx