Subject: .EBD question

From: Kellee Crisafulli <[email-masked]>
Date: Thu, 17 Dec 1998 19:34:01 -0800

Hello Ibisians,

  This came up in a conversation recently and I did not
know the answer.  
How do you describe a loop in a trace layout with the
[Path Description] in a .EBD file?

For example:
Pin 1
*
*
****
*  *
****
*
*
Pin 2

[Path Description] LOOP
Pin 1
Len = 1.0 L = 1.0n C= 2.0p / 
 Fork
 Len = 1.0 L = 1.0n C= 2.0p /
 Len = 1.0 L = 1.0n C= 2.0p /
 Len = 1.0 L = 1.0n C= 2.0p 
 Endfork
|
|now what do I do to close the loop?
|
Len = 1.0 L = 1.0n C= 2.0p /
Pin 2

---------------------------------------------------------
Have a great day....
Kellee Crisafulli at HyperLynx
SI,EMC,X-talk and IBIS tools for the Windows platform
E-mail: <mailto:[email-masked]>
web:    <http://www.hyperlynx.com>
---------------------------------------------------------

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From: Mike LaBonte <[email-masked]>
Date: Fri, 18 Dec 1998 13:16:24 -0500

Kellee,

The Fork/Endfork notation implements what is commonly called a
Directed Acyclic Graph. The key term here is "acyclic", meaning
you can not have loops. Notations that allow loops, like SPICE,
almost always do so by naming the nodes so that multiple references
into a node are accepted.

Mike LaBonte
Cadence Design Systems

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From: Kellee Crisafulli <[email-masked]>
Date: Fri, 18 Dec 1998 11:00:28 -0800

Hi Mike, all,

Thanks for the reply.

  Unless some disagrees I would like to consider a Bird to
correct this problem.
The problem I see is that the node property can not be
anything other than a component.  We could add another
property that is a non-component interconnect and fix this.

best wishes...
Kellee

---

From: Kellee Crisafulli <[email-masked]>
Date: Fri, 18 Dec 1998 13:34:21 -0800

Hi Scott, Will,

I think you and Will both suggested the 0 ohm resistor
approach.  Sounds like it will work to me and I hate
changing the spec.

At 01:16 PM 12/18/98 -0800, you wrote:
>Yep, it will be easier than changing the spec.  Loops become
>problematic for simulations.  How may loops will you allow?
Our simulator has no problem with loops.  They are stable and
you can have an infinite number of them.

>Loops are ugly, anyway.  My manufacturing engineers
>always veto the use of loops, if they notice them.
I agree, but many boards do have them.

Thanks for the feedback.
Have a happy holiday!

Kellee