Subject: IBIS Accuracy Subcommittee Minutes 6/18/98

From: Greg Edlund <[email-masked]>
Date: Mon, 22 Jun 1998 13:11:45 -0400

IBIS Accuracy Subcommittee Minutes

Thursday, June 18, 1998
Held at Stratus Computer, Marlborough, MA 

Thanks to Bruce Heilbrunn and Stratus for providing a place to meet.

Attendees

Greg Edlund, Digital Equipment (chair)
Fawn Engelmann, EMC
Bob Haller, Digital Equipment
Bruce Heilbrunn, Stratus Computer
Peter LaFlamme, Fairchild Semiconductor
Harvey Stiegler, Texas Instruments (by phone)

Next meeting is Friday, August 28, 1998 from 3:00 to 5:00 pm, location
to be determined.

MILESTONES

The test board is awaiting clean-up routing and final review.  Work
priorities have halted work on the test board for the past six weeks.
When the board has been debugged, we will post the Gerber files to the
web.

?? 1998:  Post the IBIS Accuracy Test Board to the web
September 18, 1998: Distribute the first draft of the IBIS Accuracy
Specification
October 1998:  PCB West Conference, IBIS Summit, and first IBIS Class
February 1999:  Present the IBIS Accuracy Specification at DesignCon99

EDITING

1. Scope - no activity this meeting.

2. Required Measurements

The subcommittee decided that it does not make sense to specify which
unique I/O buffer designs must be measured and compared to simulations.
In cases where there is a large number of I/O buffer designs on a chip,
the task of deciding which to measure involves engineering judgment,
which is not something that we can specify.  A perfect example of this
is a gate array which has over 100 cells in its I/O buffer library.
However, the modeling engineer must document which I/O buffer designs he
measured and which he did not.

3. 	Measurement Techniques

There are three types of measurements involved in the IBIS Accuracy
Specification:  IV curves, transient waveforms, and capacitance.  We
covered IV curves in this meeting.  The two main topics of discussion
were 1) specifying voltage and current ranges and 2) when to worry about
line drop.

For parts with clamp diodes, the modeling engineer should sweep voltage
from -1 V to Vdd + 1 V to make sure the clamps turn on fully.  The
overcurrent protection limit should be set at the absolute maximum I/O
current specification from the component datasheet.

We did not discuss whether parts without clamp diodes should have
different requirements.  One could make a strong argument that they
should.  Perhaps a good place to start would be to sweep the voltage
from -5 V to Vdd + 5 V, as specified by IBIS, with overcurrent
protection set to the absolute maximum I/O current specification.  In
many cases, parts without clamps would certainly go into overcurrent
protection somewhere over this range.

We discussed the need for four-point probing.  When line resistance from
the DUT to the instrument is high and current is high, the IR drop in
the line can introduce a significant error to the measurement.  The
modeling engineer must compute this IR drop and use a four-point probe
when IR drop reaches a certain threshold whose value has not yet been
determined.

4. Metrics - no activity this meeting.

----------
Greg Edlund, Principal Engineer
Server Product Development
Compaq Computer Corp.
129 Parker St. PKO3-1/20C
Maynard, MA 01754
(978) 493-4157 voice
(978) 493-0941 FAX
[email-masked]

---

From: tomda <[email-masked]>
Date: Tue, 23 Jun 1998 15:08:52 -0700

We at Zeelan have measured many thousand IC's and have some insight into 
the measurement problems on VI curves.  Going to -1 V below Vss and to Vdd 
+ 1 may or may not be sufficient to characterize the device.  Many times 
you will not get far enough to see the "linear" part of the "diode's" VI 
characteristics.  Just as many times the part will not allow you to get to 
-1 V below Vss.  There are all kinds of behaviors that can and do occur in 
real parts below Vss.  Limiting the current to the absolute max rating in 
the datasheet will also not allow a full characterization of the "diode". 
 But on the other hand, there are parts that will latch up very easily.

A few unfortunate times that I accidentally pushed a part to more than -2 V 
below Vss with current limits on they were sand again with epoxy impurities 
in microseconds.

Sweeping parts from -5 to Vdd +5 will only show you the current limit 
characteristics of your system for over half of the sweep.  And if the 
current times voltage (power) gets too high or the breakdown 
characteristics are exceeded, etc. you too will have made dirty sand.  I 
don't recommend doing this at all.

I question the need for 4 point current measurements.  I've never had to 
design a fixture where the IR drops in the test system were anywhere near 
significant.  The most current I've had to sink or source out of a driver 
is on the order of an amp.  With even 50mOhms of trace resistance the IR 
drop will not affect the model in any meaningful way.

Tom Dagostino
Zeelan Model Libraries
Mentor Graphics
503-685-1613 [email-masked]

-----Original Message-----
From:	Greg Edlund [SMTP:[email-masked]]
Sent:	Monday, June 22, 1998 10:12 AM
To:	[email-masked]'
Subject:	IBIS Accuracy Subcommittee Minutes 6/18/98

Thursday, June 18, 1998

Attendees

MILESTONES

EDITING

2. Required Measurements

----------