Subject: IBIS/JEDEC-16

From: "Dr. Edward P. Sayre" <[email-masked]>
Date: Fri, 06 Mar 1998 11:03:27 -0500

D. C.:

I concur that IBIS and JEDEC-16 should meet periodically.  You chip guys
have a definite interest in device qualitative descriptions, threshold
definitions and some application information is assembled and published,
but interoperability, modeling (SPICE and IBIS) and other user oriented
stuff is often left to the lab motorheads to complete.  The result is that
it often doesn't get done soon enough for our purposes.

By the way does JEDEC-16 have a web site with current drafts and standards?

ed sayre

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From: "D. C. Sessions" <[email-masked]>
Date: Fri, 06 Mar 1998 15:51:08 -0700

> it often doesn't get done soon enough for our purposes.

The result is that is often doesn't get done soon enough for ANY
purposes.  Keep in mind that the ICs that I design have to talk
over transmission media to chips that others design, and it's
not much help if their models aren't ready when I'm designing.

Worse yet (and part of the reason for JC-16B) is that some of
the *standards* were introduced without any upfront analysis
(read modelling) and are crippled thereby.  If I were feeling
nasty I'd mention GTL at this point.

> By the way does JEDEC-16 have a web site with current drafts and standards?

Would you believe http://www.eia.org/jedec/download/freestd/jesd8-xx/
The domain should be familiar.

-- 
D. C. Sessions
[email-masked]