Subject: IBIS BIRD65 - C_comp Refinements

From: Bob Ross <[email-masked]>
Date: Tue, 26 Oct 1999 14:54:15 -0700

To IBIS Committee:

Arpad Muranyi has issued BIRD65 below.  Both BIRD64 and BIRD65 will be
introduced at the IBIS Meeting on Friday, October 29, 1999.

Bob Ross
Mentor Graphics

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BIRD ID#:      65
ISSUE TITLE:   C_comp Refinements
REQUESTER:     Arpad Muranyi, Intel
DATE SUBMITTED:                       10-25-99 
DATE ACCEPTED BY IBIS OPEN FORUM:     Pending

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STATEMENT OF THE ISSUE:

Currently, the IBIS specification (v3.2) uses a single constant value for
describing the total die capacitance as seen at the pad.  This value is given
by the subparameter C_comp under the [Model] keyword.  The specification does
not mention how this capacitance is distributed between the power and ground
references, or how it should be connected to the circuit.

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STATEMENT OF THE RESOLVED SPECIFICATIONS:

Four new subparameters shall be introduced in the IBIS specification under the
[Model] keyword to provide means for a more detailed description for the die
capacitance.  These new subparameters, C_comp_pu, C_comp_pd, C_comp_pcl, and
C_comp_gcl are associated to the corresponding voltage reference keywords,
[Pullup Reference], [Pulldown Reference], [Power Clamp Reference], and [GND
Clamp Reference], respectively.  This mechanism allows the association of a
specific capacitance between the I/O node and the four possible supply nodes
without disturbing the submodel syntax.

The syntax of these four new subparameters are identical to the existing
C_comp subparameter.

Should we add voltage dependencies here with tables?

|=============================================================================
|     Keyword:  [Model] 
|    Required:  Yes.
| Description:  Used to define a model, and its attributes.
|* Sub-Params:  Model_type, Polarity, Enable, Vinl, Vinh, C_comp, C_comp_pu,
|*              C_comp_pd, C_comp_pcl, and C_comp_gcl Vmeas, Cref, Rref, Vref
| Usage Rules:  Each model type must begin with the keyword [Model].  The
|               model name must match the one that is listed under a [Pin],
|               [Model Selector] or [Series Pin Mapping] keyword and must not
|               contain more than 20 characters.  A .ibs file must contain
|               enough [Model] keywords to cover all of the model names
|               specified under the [Pin], [Model Selector] and [Series Pin
|               Mapping] keywords, except for those model names that use
|               reserved words (POWER, GND and NC).
|
|               Model_type must be one of the following:
|
|               Input, Output, I/O, 3-state, Open_drain, I/O_open_drain,
|               Open_sink, I/O_open_sink, Open_source, I/O_open_source,
|               Input_ECL, Output_ECL, I/O_ECL, 3-state_ECL, Terminator,
|               Series, and Series_switch.
|
|               Special usage rules apply to the following.  Some definitions
|               are included for clarification:
|
|               Input              These model types must have Vinl and Vinh
|               I/O                defined.  If they are not defined, the
|               I/O_open_drain     parser issues a warning and the default
|               I/O_open_sink      values of Vinl = 0.8 V and Vinh = 2.0 V are
|               I/O_open_source    assumed.
|
|               Input_ECL          These model types must have Vinl and Vinh
|               I/O_ECL            defined.  If they are not defined, the
|                                  parser issues a warning and the default
|                                  values of Vinl = -1.475 V and Vinh =
|                                  -1.165 V are assumed.
|
|               Terminator         This model type is an input-only model
|                                  that can have analog loading effects on the
|                                  circuit being simulated but has no digital
|                                  logic thresholds.  Examples of Terminators
|                                  are: capacitors, termination diodes, and
|                                  pullup resistors.
|
|               Output             This model type indicates that an output
|                                  always sources and/or sinks current and
|                                  cannot be disabled.
|
|               3-state            This model type indicates that an output
|                                  can be disabled, i.e. put into a high
|                                  impedance state.
|
|               Open_sink          These model types indicate that the output
|               Open_drain         has an OPEN side (do not use the [Pullup]
|                                  keyword, or if it must be used, set I =
|                                  0 mA for all voltages specified) and the
|                                  output SINKS current.  Open_drain model
|                                  type is retained for backward
|                                  compatibility.
|
|               Open_source        This model type indicates that the output
|                                  has an OPEN side (do not use the [Pulldown]
|                                  keyword, or if it must be used, set I =
|                                  0 mA for all voltages specified) and the
|                                  output SOURCES current.
|
|               Input_ECL          These model types specify that the model
|               Output_ECL         represents an ECL type logic that follows
|               I/O_ECL            different conventions for the [Pulldown]
|               3-state_ECL        keyword.
|
|               Series             This model type is for series models that
|                                  can be described by [R Series], [L Series],
|                                  [Rl Series], [C Series], [Lc Series],
|                                  [Rc Series], [Series Current] and [Series
|                                  MOSFET] keywords
|                                 
|               Series_switch      This model type is for series switch
|                                  models that can be described by [On],
|                                  [Off], [R Series], [L Series], [Rl Series],  
|                                  [C Series], [Lc Series], [Rc Series],
|                                  [Series Current] and [Series MOSFET]
|                                  keywords
|
|*              The Model_type subparameter is required.  The C_comp
|*              subparameter is only required if C_comp_pu, C_comp_pd,
|*              C_comp_pcl, and C_comp_gcl are not present, or the C_comp_pu,
|*              C_comp_pd, C_comp_pcl, and C_comp_gcl subparameters are
|*              required if the C_comp subparameter is not present.
|
|               The Polarity, Enable, Vinl, Vinh, Vmeas, Cref, Rref, and Vref
|*              subparameters are optional.  C_comp* define the silicon die
|*              capacitance.  Thse values should not include the capacitance
|*              of the package.  C_comp* are allowed to use "NA" for the min
|               and max values only.  The Polarity subparameter can be
|               defined as either Non-Inverting or Inverting, and the Enable
|               subparameter can be defined as either Active-High or
|               Active-Low.
|
|               The Cref and Rref subparameters correspond to the test load
|               that the semiconductor vendor uses when specifying the
|               propagation delay and/or output switching time of the model.
|               The Vmeas subparameter is the reference voltage level that the
|               semiconductor vendor uses for the model.  Include Cref, Rref,
|               Vref, and Vmeas information to facilitate board-level timing
|               simulation.  The assumed connections for Cref, Rref, and Vref
|               are shown in the following diagram:
|
|                            _________
|                           |         |
|                           |      |\ |            Rref
|                           |Driver| \|------o----/\/\/\----o Vref
|                           |      | /|      |
|                           |      |/ |     === Cref
|                           |_________|      |
|                                            |
|                                           GND
|
| Other Notes:  A complete [Model] description normally contains the following
|               keywords:  [Voltage Range], [Pullup], [Pulldown], [GND Clamp],
|               [POWER Clamp], and [Ramp].  A Terminator model uses one or
|               more of the [Rgnd], [Rpower], [Rac], and [Cac].  However, some
|               models may have only a subset of these keywords.  For example,
|               an input structure normally only needs the [Voltage Range],
|               [GND Clamp], and possibly the [POWER Clamp] keywords.  If one
|               or more of [Rgnd], [Rpower], [Rac], and [Cac] keywords are
|               used, then the Model_type must be Terminator.
|-----------------------------------------------------------------------------
| Signals       CLK1, CLK2,...         | Optional signal list, if desired
[Model]         Clockbuffer
Model_type      I/O
Polarity        Non-Inverting
Enable          Active-High
Vinl = 0.8V                            | input logic "low" DC voltage, if any
Vinh = 2.0V                            | input logic "high" DC voltage, if any
Vmeas = 1.5V              | Reference voltage for timing measurements
Cref = 50pF               | Timing specification test load capacitance value
Rref = 500                | Timing specification test load resistance value
Vref = 0                  | Timing specification test load voltage
| variable      typ             min             max
C_comp          12.0pF          10.0pF          15.0pF
|
|=============================================================================
|
[Model]         Clockbuffer
Model_type      I/O
Vinl = 0.8V                            | input logic "low" DC voltage, if any
Vinh = 2.0V                            | input logic "high" DC voltage, if any
|
| variable      typ             min             max
C_comp_pu       3.0pF           2.5pF           3.5pF
C_comp_pd       2.0pF           1.5pF           2.5pF
C_comp_pcl      1.0pF           0.5pF           1.5pF
C_comp_gcl      1.0pF           0.5pF           1.5pF
|
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ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

Problem statement

The single (constant) C_comp value of the current IBIS specification (v3.2)
does not provide enough information for the simulator to accurately simulate
high speed signals and/or ground and supply noise.

In order to simulate the signal current return path and/or supply rail noise
(GND bounce and/or Vcc droop) accurately, a model needs to provide more
detail on the distribution of the total die capacitance between the I/O pad,
power and ground references.  This BIRD attempts to provide the means for
incorporating such information in a model.

The existing C_comp subparameter does not specify how it should be connected
between the I/O pad and the supply rails.  Most naturally it will end up
getting connected to the I/O node and ground.  However, since it not only
represents the capacitance of the pulldown device, but also the capacitance of
the pullup device, one should split it between the I/O pin and ground, and the
I/O pin and power rails.  One can easily see that this configuration forms a
series combination of two capacitances between power and ground.  Simulations
show a significant difference in the waveforms for the distributed or lumped
capacitance when power and ground nodes of the die are connected through the
package parasitics to the ideal power source(s).

Possible solutions

1)  Specify splitting factor coefficients
2)  Use a new subparameter under each voltage reference keyword
3)  Use a new subparameter under each I-V curve
4)  Use four new subparameters under the [Model] keyword (as presented in
    this BIRD).

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ANY OTHER BACKGROUND INFORMATION:

The voltage dependency of the die capacitance should also be addressed at some
point. (Use typ., min., max, capacitance vs. voltage tables instead of single
values)?

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