Subject: RE: BIRD #61

From: "Muranyi, Arpad" <[email-masked]>
Date: Tue, 24 Aug 1999 17:56:19 -0700

Part of the issue here is a fundamental question, not so much whether
we had the smarts to come up with a function or not.

If we go with functions to characterize input behavior, the model maker
will have to generate the coefficients, or even the function itself.  In
this case the simulator may turn into a dumb number cruncher.  On the
other hand, if we go with tables (as currently proposed) the tool vendor
will have the burden of coming up with the smarts to find the proper
algorithm for the behavior of the input.  This allows room for product
differentiation, but may result in a situation where the data provided
in the tables does not define all possible solutions (as someone commented
on this before).

This is the reason we decided to put the proposal (BIRDs) out and solicit
feedback ESPECIALLY from the tool vendors.  We want to find out from them
whether they can work with something like this, or not.  If the answer is
NO, we will have to revisit the problem and try coming up with a proposal
using functions.  If the answer is something like:  This will work but,
this and that should be changed (data format, amount of data, etc..) then
we will tweak this proposal until (most of) the tool gurus like it.

So keep on commenting...

And thanks for the comments so far.

Arpad Muranyi
Intel Corporation
========================================================================

I think that this actually addresses the subject of BIRD #61 instead,
so I've changed the 'Subject:' to match.  #62 just attempts to capture
in IBIS the same specification semantics that already exist in standards
such as SSTL and HSTL so that there is common ground between the SI tools
and device timing specs.

WRT using vout <= f( vin ) semantic, the problem is that this is not
a static function.  The whole point is that it's time-sensitive in
some pretty nonlinear ways.  We had a go at characterizing input
delays using algebraicly and weren't happy with the results, so we
fell back on the IBIS tabular strategy.

That doesn't mean that there isn't some clever way to do it more
concisely; it just means that the BIRD's authors weren't smart
enough to find it.  Maybe one of the other listmembers will fare
better.

-- 
D. C. Sessions
[email-masked]

---

From: "D. C. Sessions" <[email-masked]>
Date: Wed, 25 Aug 1999 11:49:12 -0700

Fred Balistreri wrote:

> Hello Arpad, I'm curious about how the delay numbers wrt slope are
> measured or derived from. I realize you may not be the right person to
> ask. My question is very fundamental. Are we measuring these parameters
> and if so how. Or are we relying on SPICE simulations? In other words
> we are trying to determine the conditions upon which an input stage
> accepts a "high" or "low" state. On a VVLSI device how does one measure
> this? Do semiconductor vendors really put test points inside the
> input stage to probe? If not what techniques are going to be used to
> assure of the numbers? I'm having a hard time understanding how the
> numbers are derived and if they can be trusted.

I'll answer this.  Basically, we SPICE the input variation with
stimulus waveforms.  The actual setup and hold times are also
derived from simulation but are regressed by our test group
during characterization.  One of the reasons we chose to propose
the table-based method is that it's possible for physical model
services to measure delay variation by testing setup and hold
variations against the input waveform sets.

-- 
D. C. Sessions
[email-masked]

---

From: Fred Balistreri <[email-masked]>
Date: Wed, 25 Aug 1999 14:56:38 -0700

> variations against the input waveform sets.
Have you found a direct equation or coorelation between setup and
hold time variation vs delay variation due to slope change? Is it
exactly one to one? And sort of consistant for all parts?, technologies?
If so would you be willing to share the information with service
model providers? 

On a VVLSI device where the signal propagates through perhaps several
stages is not the variation of setup and hold also do to those stages
as well as the input buffer? In IBIS are we trying to do through gate
delay or define acceptable input voltage thresholds?   

Best Regards, 
-- 
Fred Balistreri
[email-masked]

http://www.apsimtech.com