Subject: IBIS Summit Meeting Minutes 9 Mar 1999

From: Matthew Flora <[email-masked]>
Date: Wed, 17 Mar 1999 15:30:45 -0100

DATE: 3/17/99

SUBJECT: 3/9/99 EIA IBIS Summit Meeting Minutes

VOTING MEMBERS AND 1999 PARTICIPANTS LIST:
AMP                            (Martin Freedman) 
Applied Simulation Technology  Raj Raghuram, Norio Matsui
Avanti                         Nik Bannov
Cadence Design                 Mike LaBonte
Cisco Systems                  Syed Huq
Compaq                         Bob Haller, Steve Coe, Shafir Rahman,
                               Maher Elasad
Cypress                        (Rajesh Manapat)
Fairchild Semiconductor        Peter LaFlamme, Craig Klem
H.A.S. Electronics             (Haruny Said)
Hewlett Packard (EEsof, etc.)  Paul Gregory, Henry Wu
High Design Technology         Razvan Ene*
HyperLynx                      Matthew Flora, Kellee Crisafulli
IBM                            Greg Edlund, Michael Cohen, Praven Patel
Incases                        Olaf Rethmeier, Werner Rissiek*, David Eagles*,
                               Wilhelm Arnoldi*, Ulrich Losch*
Intel Corporation              Stephen Peters*, Arpad Muranyi, Frank Kern,
                               Martin Chang, Dave Moxley, Kerry Nelson, 
                               Jeff Day, Richard Mellitz, Peter Liou
LSI Logic (Symbios Logic)      Scott King
Mentor Graphics                Bob Ross*, Mohamed Mahmoud, Sherif Hammad*,
                               Jean Oudinot*, Markku Kukkanen*,
                               Martin Grober*, Karine Loudet*
Mitsubishi                     (Tam Cao)
Motorola                       (Ron Werner)
National Semiconductor         Milt Schwartz
North East Systems Associates  Edward Sayre, Michael Baxter, Kathy Breda
NEC                            (Hiroshi Matsumoto)
Philips Semiconductor          Todd Andersen*, Peter Christiaans*
Quantic EMC                    (Mike Ventham)
Texas Instruments              Jean-Claude Perrin*, Shankar Balasubramaniah,
                               Ramzi Ammar
Thomson-CSF                    (Jean Lebrun)
Time Domain Analysis Systems   Dima Smolyansky
Viewlogic                      Chris Rokusek, Guy de Burgh*, Cary Mandel*,
                               (Jon Powell),
VeriBest                       Ian Dodd
VLSI Technology                D.C. Sessions
Zuken-Redac                    (John Berrie) 

OTHER PARTICIPANTS IN 1999:
3Dfx Interactive               Ken Wu
Actel Corporation              Silvia Montoya
Alcatel                        Steven Criel*
Analytical Edge                Robert Easson*
Applied Microelectronics       Brian Sanderson
BMW                            Friedrich Haslinger*
Bogatin Enterprise             Eric Bogatin
Bosch Telecom                  Detlef Wolf*
ECI Telecom                    Daniel Adar*
EIA                            Patti Rusher
Electronique                   Catherine Gross*
EFM Consulting                 Ekkehard Miersch*
EMC Corporation                Fabrizio Zanella
Intracon Design                Mike Osmond*
FCI                            John Ellis
Litton Systems                 Robert Bremer
Molex Incorporated             Gus Panella
Nortel Networks (& Viewlogic)  Martin Hall*
Oce Printing Systems           Ernst Deiringer*
Rockwell Collins               Susan Tweeton, Ron Hau
Samsung                        Jung-Gun Byun, Cheol-Seung Choi
Siemens                        Bernhard Unger*, Christian Mitschke*, 
                               Manfred Maurer*, Peter Kaiser*, Wolfram Meyer*,
                               Gerald Bannert*, Harmut Ibowski*,
                               Hans Pichlmaier*, Eckhard Lenski*,
                               Kortheuer Udo*, Katja Zuleeg*,
                               Christian Sporrer*
Signals & Systems Engineering  Tom Hawkins
SiQual                         Scott McMorrow
STMicroelectronics             Fabrice Boissieres*, Philippe LeFevre*
StorageTek                     Nick Krull
Sun Microsystems               Victor Chang
Tektronix                      Tom Brinkoetter
Teradyne                       Mikhail Khusid
VDOL                           Robert Novosel*
Xilinx                         Susan Wu
(Unaffiliatied, Retired)       Bruce Wenniger

In the list above, attendees at the meeting are indicated by *.  Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are
as follows:
  
  Date               Bridge Number     Reservation #    Passcode
  March 26, 1999     (916) 356-9200    2-306362         7132187

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas 
out 7 days before each Open Forum and meeting minutes out within 7 days 
after.  When you call into the meeting, ask for the IBIS Open Forum hosted 
by Will Hobbs and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES -----------------------------------

IBIS SUMMIT MEETING
The IBIS Summit Meeting was held at the Astron Hotel in Munich, Germany, near
the site of the DATE99 (Design Automation and Test in Europe) conference.

About 42 people representing 19 organizations participated in the meeting.

These minutes just briefly note some of the meeting content and some of its
discussions.  Most of the presentations and related documents are available
on the World Wide Web at:

  http://www.eda.org/pub/ibis/summits/mar99/

INTRODUCTIONS
- Bob Ross (Mentor Graphics)
After a delicious buffet lunch provided at the Astron Hotel for all
participants, Bob Ross opened the IBIS meeting by introducing himself and Vice
Chairman Stephen Peters.  Bob also introduced the sponsors of the lunch and 
meeting:  Mentor Graphics, INCASES and High Design Technology (HDT).  Bob
asked the participants to introduce themselves and noted that there were a
large number of users of EDA tools and IBIS models present.  Bob thanked
Karine Loudet of Mentor Graphics for her excellent work in handling the local
arrangements and producing the poster (which arrived late).

Bob Ross called for Ad Hoc presentations and discussion topics.  No Ad Hoc
presentations were offered, but a last minute presentation was inserted:

  Fabrice Boissiere - Generation of IBIS Models at STMicroelectronics

Later, after the break, Bob introduced Catherine Gross, a technical editor of
the  French magazine Electronique.  The article "Modeles Ibis, Mode d'emploi",
co-authored by Jean Oudinot and Kelly Freuler appears in the March, 1999
issue on pages 69-76 and gives a general overview of IBIS.   Also, Catherine
Gross authored "Les Criteres De Choix" on pages 115 and 116 and discusses
simulators and modeling topics including IBIS.

PROGRAM NOTES FOLLOW:

CURRENT IBIS ACTIVITIES AND ISSUES
- Bob Ross, Mentor Graphics
Bob Ross started the main meeting by giving a brief overview of what has 
occurred during the last year.  IBIS Version 3.2 was ratified and will be
forwarded for ANSI/EIA-656A ratification.  The ibischk3.2 parser is nearly
completed, but still needs some refinements.  IBIS Version 2.1 is moving
forward, but is still pending ratification as IEC 62014-1.  Bob noted that
over 350 people are on the IBIS reflectors.  There are 27 member companies 
(including Philips Semiconductor which was not listed last year), and
over 70 organizations and over 170 people participated in IBIS meetings in
1998.  Five face-to-face Summits were held.  Bob also noted that he knew of
over 30 different companies which provide web sites where IBIS models can be
requested or downloaded.  Other companies provide IBIS models directly.

Bob added that there are some major upcoming activities.  These include
IBIS Version 4.0 considerations, Connector Specification activity and the
IBIS User's group activity.  The User's group is dealing with the Accuracy
Specification and initial educational activity, and is holding regular
teleconference meetings.  Other activities include defining the relationship
with the EIAJ IMIC activity and tracking the EMC/EMI activity in Europe.

DETECTION OF TYPICAL BUGS IN IBIS MODELS
- Werner Rissiek, INCASES Engineering
Werner Rissiek provided an overview concerning the types of problems he has
encountered with IBIS models.  Some simple checks are recommended.  He finds
it useful to do a parser check of the model (for minor problems such as file 
length and name violations) and also to examine the model for "human" 
plausibility.

Werner gave an HSTL example where the where the best termination voltage for
waveform extraction (1.5 V) was not used.  Rather, the supply voltage of 3.3 V
was used.  Werner also has seen incorrect polarity conventions for the
[Pullup] table.  Another plausibility check involves observing where the
current passes through 0 A on the table.  The cross-over point should be near
a rail voltage for CMOS devices.  Clamps should not be double counted in the
[Pullup] and [Pulldown] tables.  The dV value under [Ramp] may conflict with
the I/V table data.  Bob Ross noted that we do not use dV since it provides
redundant information.  However, inconsistent values may indicate that other
problems exist in the model.

Werner also discussed differential models and the fact that differential
terminations are not currently used in IBIS models for waveform specification.

Werner concluded that IBIS models are well-suited for SI analysis.  However,
manufacturers should spend more effort to make sure that the models are
correct, and users should not trust the model without doing simple
plausibility checks.

Gerald Bannert suggested that some of the plausibility checks could be done
automatically.

VALIDATION OF AN ENHANCED TWO WAVEFORM BEHAVIORAL MODEL
- Bernhard Unger, Siemens AG
Bernhard Unger presented some results that he had presented previously at the
February 1, 1999 IBIS Summit regarding two-waveform based IBIS models based on
using fixture loads of 18 ohms, 50 ohms and 100 ohms.  He also presented some
new results showing an improved method to model Simultaneous Switching Noise
(SSN).

The 18 ohm fixture was selected to produce about one-half the Vcc swing.
Bernhard conducted the test using the Fairchild CMOS driver VCX16244 HSPICE
model supplied by Peter LaFlamme as a reference and from which the IBIS
model (also supplied by Peter LaFlamme) was generated.  Four driver conditions
were tested:  

  (1) a 50 ohm, 1 ns transmission line loaded with 5 pF, 
  (2) a lumped 500 ohm parallel 30 pF load,
  (3) a distributed 66 ohm transmission line load,
  (4) and a DIMM module 66 ohm transmission line load.

The simulations were conducted with and without the Vdd/Vss package model
parasitics.

The simulations were done using two-waveform extracted Kpur(t), Kpdr(t),
Kpuf(t) and Kpdf(t) table multipliers according to the SPICE implemented
algorithm cited in previous presentations.

Bernhard showed a number of overlaying comparisons and concluded that the
50 ohm fixture load provided a good compromise.  The 18 ohm fixture load
provided better correlation for the DIMM module test case since the effective  
impedance seen by the buffer was about 25 ohms.  When the Vdd/Vss package
effects were included, the results were not as well correlated.

Bernhard presented an SSN analysis setup with ground and power rail package
models.  The comparisons with 6 outputs switching showed deviations from the
original Spice simulations.  To provide more accurate results, Bernard
proposed an enhanced two waveform behavioral model that contained multipliers
on the pullup and pulldown current sources.  Each multiplier is a function
of the difference between Vdd and Vss.  Each is derived using only one new
"SSN Golden Waveform V/T table" for a rising and falling using a prescribed
set of Vdd and Vss package pin models.  Bernhard showed some improved results,
and answered some questions regarding deriving the multipliers from actual
switching results.

Bernhard concluded with the following points:

  (1) Two waveform behavioral model simulations provide excellent agreement
      with transistor based simulations if the IBIS V/T-table loading 
      conditions are comparable with the simulation conditions.
  (2) The proposed model enhancement causes an important improvement regarding
      SSN simulations and dependence on package parasitics.  Only one
      additional "SSN Golden Waveform V/T-table" for each rising and falling
      edge and Vdd/Vss package models are necessary.
  (3) 50 ohm V/T-table loading conditions seem to be a good compromise for 
      most purposes.
  (4) IBIS models with different R_fixture loadings are a real need if timing 
      and noise are very critical issues.

IBIS VERSION 3.2 UPDATE
- Stephen Peters, Intel
Stephen Peters gave an IBIS Version 3.2 update similar to the presentation
at the February 1, 1999 IBIS Summit Meeting.  Version 3.2 was ratified by the
IBIS Open Forum at the January, 1999 teleconference meeting and will be
forwarded for ANSI/EIA-656A ratification.  The golden parser is uploaded (it
still needs some fixes).

As background, Stephen stated that IBIS Version 2.1 supported I/V tables
and V/T tables.  It provided initially for GTL plus technology.  However, it
was limited in describing passive elements, it did not provide adequate
multi-stage I/O buffer models and cartridge packaging technology, and lumped 
L/R/C package models were a practical limitation.

Stephen gave an overview and elaborated (showing related keywords) upon four 
areas of IBIS Version 3.2 enhancements: 

  (1) Support for additional device types
      - passive (2-pin) devices, terminators, bus switches
  (2) Extended model specs and simulation hooks
      - ringback and hysteresis specs, model selectors
  (3) Support for advanced driver/receiver technology
      - multi-staged outputs, bus hold, dynamic clamps
  (4) Enhanced package descriptions
      - transmission line package stubs, .ebd files.

Stephen noted that the future enhancements include uncoupled and coupled
connector models.  The [Add Submodel] concept can be a path for future
expansion since a submodel can be used for anything.  There is consideration
of a possible merger or incorporation of the IMIC specification.

MISCELLANEOUS AND BREAK
Before the break, Bob Ross added that prior work regarding the algorithms 
have been presented at previous IBIS Summits and are uploaded at

  http://www.eda.org/pub/ibis/summits/

under the feb99, and feb98 directories.  He also noted how to sign up on the
IBIS reflector (noted at the end of the minutes).

IBIS MANAGEMENT AND CUSTOMER'S CHECK ASPECTS
- Gerald Bannert (Siemens)
Gerald Bannert showed an overview of the Basic Input/Output Library (BIOLIB).
Source data includes Vendor HSPICE models, Measurement modes and Vendor
data sheets.  In the future, IBIS models may be used as a source.

A DOGEN utility (discussed in the next presentation) is used to convert the 
information to valid IBIS+ models.  The information includes the models, the 
pinning, the package, and index.  The DOGEN tool is also used to validate 
libraries based on the IBIS format and vendor specific formats.  Project 
libraries also can be automatically created.

Gerald discussed Today's IBIS model availability.  About 35% of the models are
not available, especially for ASICs and newer technologies.  About 65% of
the models are available, but these may have a number of problems, errors, and 
limitations which he listed.  He proposed some new parameters.  He noted that
selecting the proper junction temperature (25 deg. C of 50 deg. C) for typical
models strongly influenced the simulation results.  Only about 5% of the
available models satisfy their needs.

Gerald presented the physical background for overshoot.  He showed a number of
interacting aspects, failure mechanisms and conditions related to the
Dynamic_overshoot specification and parameter influence.  He also illustrated
some methods to establish some limits when manufacturer values were not 
available based on whether or not the clamping diodes existed.  With no
clamps, he suggested the D_overshoot values be set to 0.5 V above the rail for
a duration of 3 ns, and the S_overshoot values be set at the rail voltages.
With clamps, he suggested the voltages be based on a 1:2 ratio of S_overshoot
to D_overshoot current limits and the D_overshoot duration be set to 5 ns.

Gerald discussed further a number of physical parameter checks.  Included were
package parameters, power capacitance, min and max ratings beyond limits using 
D/S_overshoot currents, proper pullup, pulldown tables and realistic waveform 
table generation conditions, and frequency of operation.  Furthermore, Gerald 
formulated how scaling factors for actual temperature, voltage and process 
variations might be added to relate to actual application extremes (rather 
than given worst case conditions).  This might be considered for future IBIS 
and tool support.

Customers will demand IBIS Models for all "new" digital ICs for year 2000.  
The customer will expect the information of the current IBIS specification 
and a model that is error free and accurate.  Optional parameters are needed
for some customers and tools.  Some tool-specific parameters may also be
needed.  Siemens is developing a model specification which contain such 
information and requirements that is expected to be part of a semiconductor
purchase contract.  This specification should be available during the second 
quarter of 1999.

DOGEN, AN INTERNAL MODEL TOOL
- Hans Pichlmaier (Siemens)
Hans Pichlmaier gave functional overview of the previously mentioned DOGEN
utility.  It converts QUAD to IBIS, IBIS to QUAD, SPICE to IBIS.ebd, and  
SPICE to QUAD.top.  It does IBIS scaling from typ to min/max.  It does
syntax checks and can work with BIOLIB or as a stand-alone utility.  Currently
the database supports about 1200 devices for models needed in vendor specific
formats.

An in-house tool was needed to solve the internal model availability issue for
use between different EDA tool vendors.  Vendor tools have different needs,
and the supplied translation tools were not adequate for automated use.

Hans showed some details where using an internally standardized naming
convention and parameter files, details of which could be added to QUAD
formatted models to provide automatic translation into IBIS models.  Ramp
conversion is done by actual simulation.  Hans also showed an example of SPICE
netlist to .ebd conversion under development.  Part numbers and component pins
are defined in a parameter file.  Hans illustrated scaling of I/V and V/T data
to provide min and max tables from typ tables.  A parameter file defines
several factors for independent min and max scaling.

Hans showed the extensive DOGEN checking functionality.  It automatically
does checks based on 60 criteria on old Quad models, IBIS model and from
models generated in the tool library in support of several simulator specific
formats.

Sixteen checks are devoted to testing naming compatibility between pin, model 
and package names.  [Pin], [Diff Pin] and other blocks are checked for 
multiple and unused names in compliance with the in-house naming conventions.  
A number of common data checks include testing for monotonic data, testing 
typ is between min and max, checking that all columns contain numerical data 
without NA entries, and checking that all necessary data is defined.  Twenty
special data checks are done on such parameters as D_overshoot > S_overshoot >
Vcc (or Vinh for LVDS and ECL), range of D_overshoot time, value of the
clamp current at the D_overshoot values, etc.

Hans presented some future plans.  These include support of IBIS Version 3.0
[Driver Schedule], series models and [Series MOSFET], [Model Selector]
keywords.  An old internal LDRC data base will be transformed to an internal
"IBIS+" format.  He may also enhance the conversion from SPICE to IBIS+.  He
also added TOPSPEC to EBD conversions.

In response to questions Hans noted that different simulators may or may not
have some name length restrictions, but all are beyond the limits set within 
the IBIS format.  These are checked.

GENERATION OF IBIS MODELS AT STMICROELECTRONICS
- Fabrice Boissieres (STMicroelectronics)
Fabrice Boissieres shared his work for automatic IBIS model generation for 
ASICs.  The process is based on a s2ibis adaptation with ELDO models.  It
integrates the ASIC models with package model information.  His goals is to
integrate IBIS ASIC models to the application design and also to generate
IO libraries for several CMOS processes.

Fabrice presented the flow.  Included is an IbisGeneration.pl script for
configuring s2ibis for the particular IOcell characteristics, and an LSF
utility for distributing the computing over several machines.  A 
CheckAndCorrect.pl script checks the results for a non-monotonic behavior
and wrong values; graphically displays the corrected versus original model;
performs the ibischk3 syntax check.  The result is entered into the 
IOcell_final.ibs library.

An ICPack utility is used to integrate IBIS ASIC models.  It uses the IBIS IO
Library and the ICPack IO library along with connectivity information and
package models to produce IBIS ASIC models.  Currently the package models are
in two families that are linked to the application accuracy requirements.
When lead length is important compared to wire length, estimated R,L,C
parameters are used.  When wire length is not negligible, mutual inductance is
taken into account by simulation.

Fabrice outlined his current and future work.  Current work includes checking
the process with different test cases.  Future work includes more validation
by checking the models against silicon measurements and under different
simulation environments.

IBIS FUTURE REQUIREMENTS
- Stephen Peters, Intel
Stephen Peters gave an IBIS future requirements presentation similar to the 
one presented at the February 1, 1999 IBIS Summit meeting.  Stephen noted
IBIS handles several things well.  It handles CMOS/TTL/ECL technology and 
controlled rise time parts such as GTL.  Bus hold is now available.  The EBD 
and enhanced packages allow more complex paths - as long as coupling is not 
required.

However, what is lacking is multiple buffer switching effects taking into
account SSO effects due to pin to pin coupling and power/ground rail bounce.
A lossy transmission line is needed.  Perhaps it is time for the G matrix 
and/or a frequency dependent loss for .ebd and .pkg files.  Non-ideal ground
return paths need to be modeled in the next generation of simulators.

Stephen continued that the solution to these are important because of very 
fast processor buses and source synchronous signaling.  The timing budgets 
are tight and the second order effects are now dominant.

[Pin Mapping] is a start, but is not complete.  It does not include model
on-die capacitance.  Pin to pin coupling is almost there, but needs
improvement.  Perhaps a champion is needed to make use of the connector model
information that is is being considered.

Stephen stated that the key to SSO modeling is to make the buffer power
and ground nodes available.  IMIC is interesting, but does not use the 
standard I/V and V/T description of the buffer.  Stephen also noted that
the [Add Submodel] keyword has expansion possibilities for a model consisting
of a group of buffers and for embedding package descriptions.

FUTURE REQUIREMENTS ON FREQUENCY DEPENDENT PACKAGE AND MCM MODELING
- Werner Rissiek (INCASES Engineering)
Werner Rissiek presented some research work funded by BMBF showing that it
will be necessary to consider the frequency dependent behavior of MCM and
package interconnect structures in the future.  The requirements are to
limit the complexity of time domain simulation while still providing
reasonable accuracy.

Werner showed a typical MCM structure and then showed some  lumped element
approximations with and without skin effect.  He showed good comparisons
between scattering parameter S11 and S21 terms between simulation using the
lumped elements and measurement.  In fact the measurements are suspicious at
the higher frequencies for the S21 comparisons.

In addition, Werner proposed a 4 X 4 system of frequency dependent
transmission lines to consider coupling effects.  The complexity is limited
to allow efficient parameter extraction and simulations.

Werner concludes that 

  (1) Lumped element descriptions are sufficient for frequency dependent
      modeling of single signal paths on MCM and packages.
  (2) Currently IBIS is supporting only limited structures to support this
      kind of modeling.
  (3) The IBIS format has to become flexible to support various types of
      lumped element models efficiently.
  (4) Frequency dependent transmission line parameters will become important
      for modeling of signal paths including coupling in the future.

CONCLUSION
Bob Ross closed the meeting by again thanking the meeting sponsors, Karine 
Loudet, and the presenters for their outstanding presentations.  Werner 
Rissiek reminded people of the DATE99 conference and the PCB Symposium.  Bob 
stated that we should look forward to another IBIS Summit meeting next year 
in Paris associated with DATE2000.

NEXT MEETING:
The next teleconference meeting will be on Friday, March 26, 1999 from 8:00 AM 
to 10:00 AM. 
==============================================================================
                                      NOTES

IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            [email-masked]
            Modeling Engineer, Interconnectix BU of Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

VICE CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-4515
            [email-masked]
            Senior Hardware Engineer, Intel Corporation
            M/S JF1-56
            2111 NE 25th Ave. 
            Hillsboro, Oregon 97124-5961

SECRETARY:  Matthew Flora (425) 869-2320, Fax: (425) 881-1008
            [email-masked]
            Senior Engineer, HyperLynx, Inc.
            17641 NE 67th Court
            Redmond, WA 98052

LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Scientist, Viewlogic (formerly Quad Design)
            1385 Del Norte Rd., Camarillo, CA 93010
 
This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  [email-masked]
      To join, change, or drop from either the IBIS Open Forum Reflector
      ([email-masked]), the IBIS Users' Group Reflector ([email-masked])
      or both.  State your request.

  [email-masked]
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  [email-masked]
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  [email-masked]
      To send a message to the IBIS Users' Group Reflector.  This is 
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  [email-masked]
      To report ibischk2 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, 
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eia.org

Check the pub/ibis directory on eda.org for more information on previous 
discussions and results.  You can get on via FTP anonymous.
==============================================================================