Subject: ibis-users V1 #11
From: owner-ibis-users@ (ibis-users)
To: [email-masked]

ibis-users          Monday, November 11 2002          Volume 01 : Number 011

----------------------------------------------------------------------

Date: Mon, 30 Sep 2002 08:03:28 -0400
From: "Douglas Burns" <[email-masked]>
Subject: RE: [IBIS-Users] ibis pins (once more, this time more details)

Yoni,

 An IBIS model shows only 1 pin. This Pin is the Pin of the chip/package
that connects to the outside world. The stimulus nodes (EN, IN) and the
receiver node (Vout_of_IN) are assumed to exist based upon the model type.
For Hspice, these assumed nodes MUST be specified so that HSPICE can
stimulate them (The nodes in the IBIS pinlist DO NOT fully correlate with
the nodes required by the HSPICE netlist). The model you are using has the
following logical block diagram.

              IO PAD

	EN ---------
	             |\ |
	             | \
	IN ------- |  x-------------------OUT
      	             |  /		|
                         |/		|
				|
	               /|		|
   Vout_of_IN---- x  |----------------
     	               \|

In HSPICE you must specify the simulus for IN and EN. When Enabled, You
apply a 0-->1 transistion to IN to get a 0-->VDDQ transition on OUT.
(The Vout_of_IN input will also toggle from 0-->1

If Disabled, IN is disconnected from OUT, But changes applied to OUT
(0-->VDDQ) will result in a 0-->1 transition on Vout_of_in

Doug

Douglas Burns
Principal Consultant
Signal Integrity Software, Inc.
6 Clock Tower Place
Maynard, MA 01754
978-461-0449
[email-masked]

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On Behalf Of
Yoni Tzafrir
Sent: Sunday, September 29, 2002 1:54 PM
To: 'Ibis (E-mail); Ibis-Users (E-mail)
Subject: [IBIS-Users] ibis pins (once more, this time more details)

> hi,
> we were trying to connect an sstl2c2_a ibis model, as a reciever. since we
> know this an i/o buffer, we have called for all the i/o buffer nodes to
> our netlist, as specified in this file, on pages 7-16 to 7-19 :
>
>  <<2001.4_models_buffers.pdf>>
> in that manner:
>
> * node names     nd_pu    nd_pd     out    in        en     v_out_of_in
> b_output           nd_pu    nd_pd     out    pad_r     en     v_out_of_in
> + file='bsstl2c2_a.ibs'
> + model='bsstl2c2_a'
>
> connecting the in node (called here pad_r), to our circuit.
>
> but looking again in the ibis model once more we saw that there was only
> one pin:
>
> [Pin]        signal_name     model_name         R_pin   L_pin   C_pin
>   1             PAD          bsstl2c2_a          NA      NA      NA
>
> my quesion is what does it mean? is a pin = node? so this model has one
> node only? if so, how do i connect him to the netlist? does'nt that
> contradict the fact that i have called for 5 nodes to my netlist (which
> the hspice runs well, and also refuses to run it with less nodes)?
>
> the file attached above does refer to ibis pin-list in pages 7-44 to 7-50,
> but it is completely unclear to me, and don't answer the questions above.
>
> i'll appreciate your help,
> [Yoni Tzafrir]

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------------------------------

Date: Mon, 30 Sep 2002 12:03:28 -0700
From: "Angulo, John" <[email-masked]>
Subject: [IBIS-Users] hspice mailing list

The following is posted on behalf of Yoni Tzafrir at Siliquent Technologies.  Please send all private replies to [email-masked] only.

- --------------------------------

hi,
does anyone know on hspice mailing list, which i can join?

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------------------------------

Date: Wed, 2 Oct 2002 09:36:24 -0500
From: "Roy Leventhal" <[email-masked]>
Subject: FW: [IBIS-Users] EW UK article Critical about vendor IBIS models

- -----Original Message-----
From: Roy Leventhal [mailto:[email-masked]]
Sent: Friday, September 27, 2002 8:49 PM
To: Angulo, John; [email-masked]'
Subject: RE: [IBIS-Users] EW UK article Critical about vendor IBIS models

Sorry,

This is old news. I presented a paper on these issues at the Cadence User
Group meeting in September, 2000 and again at IPC Designers Learning
Symposium in July, 2001. The results I presented are basically the same and
are a synopsis of my experience screening some 800+ IBIS models for 3Com in
the 3-1/2 years that I was there. Prior to either presentation I gave a talk
at the IBIS Committee Summit at PCB East in 1999 or 1998 on these same
issues.

The new news is that there is an IBIS subcommittee working on making the
IBIS spec more readable and the IBIS parser more effective at catching
problems.

The really significant news would be that the semiconductor industry cared
enough to clean up their act. It took the Japanese quality revolution to
make our semiconductor industry change its ways. Most of them did not
survive that challenge as independent, vertically integrated USA entities.
In that revolution it took ultimate consumers buying from companies whose
products did not break, cost less and incorporated new useful features
quicker.

Based on my recollections of simulating amplifier strings, when I had to
obtain SPICE models things were not any better. Simulation was just coming
into real use and SPICE models were not used by the process engineers to
maintain process quality and consistency. Then, two things happened. The
Japanese ate our lunch over the quality issue and the semiconductor industry
had to respond with more attention paid to process control.

By hearsay evidence, or so I've been told, the semiconductor industry now
makes much more intensive use of SPICE, HSPICE in particular, to control
quality. Supposedly then, the quality of SPICE models has improved because
the process engineers now have a payoff in their accuracy, and I hope,
completeness. But, you would have to present some data to me that would
support the idea that SPICE models are any better. I'd say that the evidence
for SPICE improvement is thin based on the fact that almost all IBIS models
are produced by simulating the SPICE model. I would guess that (clamp) diode
resistance (a SPICE parameter) is not critical to process control based on
the number of IBIS clamp curves with magnitudes of E23 that I have seen.
This is a direct result of not modeling that parameter in the SPICE model.

There is no payoff in producing and maintaining accurate IBIS models in
anything the semiconductor industry is interested in, save one - turning a
profit.

Prior even to the quality and availability issue over SPICE models was the
exact same problems regarding data sheets. The JEDEC Committee was simply
ignored by the semiconductor industry when the former tried to enforce
discipline regarding 1N - - - - and 2N - - - - data sheets. At that point
the semiconductor suppliers simply issued their own data sheets and ignored
the JEDEC Committee and its Standards.

When you think about it, there is no inherent reason for the semiconductor
industry to produce good, plentiful data sheets, IBIS models, SPICE models,
Applications Notes or any other "knowledge collateral" without a direct
connection to the profit motive. Do you think for a minute that your
company's Purchasing Department would, or would not, place an order based on
the availability of any or all of the items I've just listed?

Nothing will change until the semiconductor vendors start loosing or gaining
sales over the IBIS model quality issue. Second, it must be made plain to
them that the lack of models and their poor quality is the cause of loosing
sales. Third, loosing sales will not happen until particular technologies
have more than one/multiple suppliers available as alternative sources to
users. Plus, the bottom line impact of line yield problems, stretched out
development times due to excessive debugs of (unsimulated) physical boards,
etc., must be known to a user company's money people.

Regards,

Roy

- -----Original Message-----
From: [email-masked]
[mailto:[email-masked]]On Behalf Of Angulo, John
Sent: Friday, September 27, 2002 3:49 PM
To: [email-masked]'; [email-masked]'
Subject: [IBIS-Users] EW UK article Critical about vendor IBIS models

The following is posted on behalf of Mike Ventham at Quantic EMC.  Please
send all private replies to [email-masked] only.

- -----------------------------------------
IBISians,

I thought you might be interested in this article.

http://www.electronicsweekly.co.uk/issue/dailyview.asp?vpath=/articles/2002/
09/25/daily06.htm

Any comments?

P.S. Apologies if you get two copies by being on both IBIS lists. There is
      no merged list to ensure everyone interested in IBIS only gets 1 copy.

Regards

Mike
________________________________________________________________
| Mike Ventham - Vice-President Engineering,                   |
| Quantic EMC Inc.                  Headquarters               |
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------------------------------

Date: Wed, 2 Oct 2002 16:20:11 -0400 
From: "ruston, matt" <[email-masked]>
Subject: [IBIS-Users] Accuracy of Motorola's IBIS models

Hello:

 Does anyone have any experience with Motorola IBIS models? In particular,
I'm talking about the Microprocessor division (Power PC). Were the models
accurate when comparing them to the bench? Any other concerns/questions that
I should know about? Any and all info is appreciated.

Thanks,

Matt
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------------------------------

Date: Mon, 14 Oct 2002 16:05:38 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] IBIS East Summit Teleconference Details

Hello All:

   This is a reminder that the IBIS East Summit will be held Tuesday, Oct.
15 from 1:00pm - 5:00pm Eastern time (10:00pm - 2:00pm Pacific time).  This
is a teleconference meeting, with attendees at both the NESA offices and
offsite.  The teleconference bridge information is below:

Dial-in:   (916) 356-2663
Bridge:    3 
Passcode:  8230829 
Title:     IBIS East Teleconference

The presentations can be downloaded from the following URL

   http://www.eda.org/pub/ibis/summits/oct02/

so can follow along if you phone in.

In addition to downloading the presentation, you can view the presentation
over the web by logging onto the Web Ex website.

http://ioscollaborate.com/intel

Meeting title:   IBIS Open Forum Summit
Meeting number:  2001399926
Password:        ibis123!

Type in the meeting number, then follow the instructions.  Individual
presentors will control there presentations.

I look forward to full and lively meeting.

  Regards,
  Stephen Peters
  Intel Corp.
  Chair, EIA/IBIS Open Forum

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------------------------------

Date: Tue, 15 Oct 2002 15:05:30 -0500
From: John Phillippe <[email-masked]>
Subject: [IBIS-Users] Making Pullup curves VCC relative.

IBIS Gurus:
  The more I try to figure out what the IBIS spec, and Cookbook say
about making the pullup curves VCC relative, the more confused I get. 
Here is what I know so far.

Spice2IBIS generates 4 different spice decks for a given process (typ or
min or max) described below:

dutpad.spi - Typ pullup curve (tristated), sweep range: -VCC to 2*VCC
putpad.spi - Typ pullup curve, sweep range: -VCC to 2*VCC
pctpad.spi - Typ power clamp curve, sweep range: VCC to 2*VCC
gctpad.spi - Typ ground clamp curve, sweep range: -VCC to VCC

All of the sweep voltages are referenced to ground.  My questions deal
with the post processing by the spice2ibis utility, and what the spec
wants.

For the pullup curve, does spice2ibis subtract the dutpad.spi results
from the putpad.spi results, and then take that data and put it into the
ibis file?  Does it do some kind of subtraction from VCC?

If I wanted to create a pullup curve by hand would I only need to
subtract the dutpad (clamp) data from putpad (driver) data?  Anyone have
a good/simple explanation of what "VCC relative" means?

Thanks for any and all info.
- -- 
John Phillippe
SPS, 32 Bit Embedded Controller Division, IC Creation
Motorola      -  512-895-1835
Austin, TX    -  [email-masked]
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------------------------------

Date: Tue, 15 Oct 2002 16:58:08 -0400
From: "Ingraham, Andrew" <[email-masked]>
Subject: RE: [IBIS-Users] Making Pullup curves VCC relative.

"VCC relative" means that 0V in the table, corresponds to Vin or Vout = VCC at the device pin or pad.

In addition, the tables are arranged so that positive table values mean I/O voltages mostly within the normal range between GND and VCC, and negative table values are voltages below GND or above VCC, toward the clamps.  (Obviously, if you go far enough in either direction, you will go beyond GND and VCC.  Large positive table values correspond to voltages beyond the opposite supply rail.)

Vtable = Vcc - Voutput.

This formula is applied only to the [Pullup] and [Power Clamp] tables.  No such adjustment is made to the [Pulldown] and [GND Clamp] tables.

The step of subtracting the clamp currents from the simulated or measured currents, to get the values for the [Pullup] and [Pulldown] tables, is different.  It has nothing to do with the fact that the [Pullup] and [Power Clamp] tables are VCC relative.  They are two independent steps in the process.  Subtracting the clamp currents prevents double counting when they are added back together by the simulator.

Andy

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------------------------------

Date: Tue, 15 Oct 2002 16:51:53 -0700
From: Eric Hsu <[email-masked]>
Subject: [IBIS-Users] model generation issue

This is a multi-part message in MIME format.
- --------------8D6E4297BB20778686F5E1A3
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi,

Fisrt, when using s2ibis2 to generate ibis file(ver 2.1), should I take
off "stand-alone" esd dummy diodes, which are not part of output buffer
but just only for enhancing esd protection?
Second, is there any free tool to generate ibis file for ver 3.2 or 4.1?

Best Regards

- -eric

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begin:vcard 
n:Hsu;Eric
tel;fax:650.961.1092
tel;work:650.961.6676 x198
x-mozilla-html:TRUE
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adr:;;450 National Ave.;Mountain. View;CA;94043;US
version:2.1
email;internet:[email-masked]
title:Sr. Design Engineer
x-mozilla-cpt:;1184
fn:Eric Hsu
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------------------------------

Date: Tue, 15 Oct 2002 17:45:51 -0700 (PDT)
From: Syed Huq <[email-masked]>
Subject: Re: [IBIS-Users] model generation issue

If it is for ESD leave that in.

NCSU is working on the next generation of s2ibis2..

Syed

>Date: Tue, 15 Oct 2002 16:51:53 -0700
>From: Eric Hsu <[email-masked]>
>X-Accept-Language: en
>MIME-Version: 1.0
>To: [email-masked]
>Subject: [IBIS-Users] model generation issue
>
>Hi,
>
>Fisrt, when using s2ibis2 to generate ibis file(ver 2.1), should I take
>off "stand-alone" esd dummy diodes, which are not part of output buffer
>but just only for enhancing esd protection?
>Second, is there any free tool to generate ibis file for ver 3.2 or 4.1?
>
>Best Regards
>
>-eric

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------------------------------

Date: Tue, 15 Oct 2002 17:50:57 -0700
From: Eric Hsu <[email-masked]>
Subject: [IBIS-Users] model generating issue

This is a multi-part message in MIME format.
- --------------B0F723F664B0D00E2E806458
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi,

Fisrt, when using s2ibis2 to generate ibis file(ver 2.1), should I take
off "stand-alone" esd dummy diodes, which are not part of output buffer
but just only for enhancing esd protection?
Second, is there any free tool to generate ibis file for ver 3.2 or 4.1?

Best Regards

- -eric

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 name="ehsu.vcf"
Content-Transfer-Encoding: 7bit
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begin:vcard 
n:Hsu;Eric
tel;fax:650.961.1092
tel;work:650.961.6676 x198
x-mozilla-html:TRUE
org:;Interface Technology
adr:;;450 National Ave.;Mountain. View;CA;94043;US
version:2.1
email;internet:[email-masked]
title:Sr. Design Engineer
x-mozilla-cpt:;1184
fn:Eric Hsu
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------------------------------

Date: Tue, 15 Oct 2002 19:21:53 -0600
From: Al Davis <[email-masked]>
Subject: Re: [IBIS-Users] Making Pullup curves VCC relative.

On Tuesday 15 October 2002 02:58 pm, Ingraham, Andrew wrote:
> "VCC relative" means that 0V in the table, corresponds to Vin
> or Vout = VCC at the device pin or pad.

What confuses people is that the sign is flipped from what it 
logically ought to be.  If you just flip the sign of the 
voltage, it makes sense.

>
> In addition, the tables are arranged so that positive table
> values mean I/O voltages mostly within the normal range
> between GND and VCC, and negative table values are voltages
> below GND or above VCC, toward the clamps.  (Obviously, if
> you go far enough in either direction, you will go beyond GND
> and VCC.  Large positive table values correspond to voltages
> beyond the opposite supply rail.)
>
> Vtable = Vcc - Voutput.

Read this carefully ....  It means the ground lead of your 
scope is hooked to the output, and the tip of the probe to the 
power supply.

The pullup is just like the pulldown except for the sign flip.  
It is a i/v table describing a nonlinear resistance, 
representing the channel of the output device.  For pulldown, 
it is hooked from output to pulldown_reference.  You measure 
the voltage across it.  It just happens that pulldown_reference 
is often the same as ground, so the voltage to ground happens 
to match.  For pullup, that device is hooked from output to the 
power supply (pullup_reference) and you measure the voltage 
across it.  Unfortunately, in the standard, the sign of the 
voltage is flipped.  Since the standard cannot be changed 
without breaking compatibility, we are stuck with it.

> This formula is applied only to the [Pullup] and [Power
> Clamp] tables.  No such adjustment is made to the [Pulldown]
> and [GND Clamp] tables.

except for ECL types.

> The step of subtracting the clamp currents from the simulated
> or measured currents, to get the values for the [Pullup] and
> [Pulldown] tables, is different.  It has nothing to do with
> the fact that the [Pullup] and [Power Clamp] tables are VCC
> relative.  They are two independent steps in the process. 
> Subtracting the clamp currents prevents double counting when
> they are added back together by the simulator.

But be careful when you subtract.  The way most people do it, 
they subtract two very large numbers and come up with a small 
number as the result.  The pullup and pulldown curves are often 
nonsense in this region, showing something non-monotonic, which 
is usually wrong and sometimes causes trouble for simulators, 
if your simulator handles ground bounce.  If you are not 
modeling ground bounce, they are in parallel and you don't see 
the problem.  It is only a problem if pulldown_reference and 
ground_clamp_reference are different nodes, or likewise if 
pullup_reference and power_clamp_reference are different nodes.

A better approach is to take the derivatives of both curves, 
subtract the derivatives, smooth out the nonsense in the clamp 
region, and then integrate it.  Simply dropping points is the 
best way to smooth the nonsense.

The data in this region is questionable anyway.  Its main 
purpose is to put the simulator back on track when a stray 
iteration sends it there.  It is important that it be well 
behaved.  It is not so important for it to be accurate.  This 
is fortunate, because you can't be accurate.  If you try it 
with a real device, you will destroy it.  If you try it with a 
simulator, you are operating devices in regions the models were 
not designed for.

You should always look at the derivatives of your curves 
anyway.  The derivative is more important than the data itself, 
and is often loaded with noise due to rounding and measurement 
noise.  Take the derivative of your actual data tables and plot 
it.  You may be in for a big surprise.
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------------------------------

Date: Tue, 15 Oct 2002 22:13:10 -0400
From: "Ingraham, Andrew" <[email-masked]>
Subject: RE: [IBIS-Users] model generation issue

> Fisrt, when using s2ibis2 to generate ibis file(ver 2.1), should I take
> off "stand-alone" esd dummy diodes, which are not part of output buffer
> but just only for enhancing esd protection?
 
No.  You should model how the device, the IC, behaves.  If actual ESD diodes are part of the device, include them, whether you think of them as part of the buffer, or separate from it.  From the point of view of someone outside the chip looking in, it doesn't matter if they were designed by the same person or not.  ESD diodes affect the [GND Clamp] and [Power Clamp] characteristics, as well as C_comp.

(But I am not sure exactly why you call them "dummy" diodes.  Sometimes "dummy" is used to mean place-holders that do not correctly represent how the circuit behaves.)

Andy

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------------------------------

Date: Wed, 16 Oct 2002 00:45:23 -0700 (PDT)
From: "Abdulrahman A. Rafiq" <[email-masked]>
Subject: Re: [IBIS-Users] Making Pullup curves VCC relative.

- --0-1525711088-1034754323=:482
Content-Type: text/plain; charset=us-ascii

Ibis Gurus, 
This brings up another question I have had for sometime now. I am wondering if there is a white paper on generating ibis models in the lab. I have upto now translated spice models to ibis, however if i ever needed to, how could i generate an ibis model from lab measurments? 
Thanks, 
Abdulrahman Rafiq  Al Davis <[email-masked]> wrote:
On Tuesday 15 October 2002 02:58 pm, Ingraham, Andrew wrote:
> "VCC relative" means that 0V in the table, corresponds to Vin
> or Vout = VCC at the device pin or pad.

What confuses people is that the sign is flipped from what it 
logically ought to be. If you just flip the sign of the 
voltage, it makes sense.

>
> In addition, the tables are arranged so that positive table
> values mean I/O voltages mostly within the normal range
> between GND and VCC, and negative table values are voltages
> below GND or above VCC, toward the clamps. (Obviously, if
> you go far enough in either direction, you will go beyond GND
> and VCC. Large positive table values correspond to voltages
> beyond the opposite supply rail.)
>
> Vtable = Vcc - Voutput.

Read this carefully .... It means the ground lead of your 
scope is hooked to the output, and the tip of the probe to the 
power supply.

The pullup is just like the pulldown except for the sign flip. 
It is a i/v table describing a nonlinear resistance, 
representing the channel of the output device. For pulldown, 
it is hooked from output to pulldown_reference. You measure 
the voltage across it. It just happens that pulldown_reference 
is often the same as ground, so the voltage to ground happens 
to match. For pullup, that device is hooked from output to the 
power supply (pullup_reference) and you measure the voltage 
across it. Unfortunately, in the standard, the sign of the 
voltage is flipped. Since the standard cannot be changed 
without breaking compatibility, we are stuck with it.

> This formula is applied only to the [Pullup] and [Power
> Clamp] tables. No such adjustment is made to the [Pulldown]
> and [GND Clamp] tables.

except for ECL types.

> The step of subtracting the clamp currents from the simulated
> or measured currents, to get the values for the [Pullup] and
> [Pulldown] tables, is different. It has nothing to do with
> the fact that the [Pullup] and [Power Clamp] tables are VCC
> relative. They are two independent steps in the process. 
> Subtracting the clamp currents prevents double counting when
> they are added back together by the simulator.

But be careful when you subtract. The way most people do it, 
they subtract two very large numbers and come up with a small 
number as the result. The pullup and pulldown curves are often 
nonsense in this region, showing something non-monotonic, which 
is usually wrong and sometimes causes trouble for simulators, 
if your simulator handles ground bounce. If you are not 
modeling ground bounce, they are in parallel and you don't see 
the problem. It is only a problem if pulldown_reference and 
ground_clamp_reference are different nodes, or likewise if 
pullup_reference and power_clamp_reference are different nodes.

A better approach is to take the derivatives of both curves, 
subtract the derivatives, smooth out the nonsense in the clamp 
region, and then integrate it. Simply dropping points is the 
best way to smooth the nonsense.

The data in this region is questionable anyway. Its main 
purpose is to put the simulator back on track when a stray 
iteration sends it there. It is important that it be well 
behaved. It is not so important for it to be accurate. This 
is fortunate, because you can't be accurate. If you try it 
with a real device, you will destroy it. If you try it with a 
simulator, you are operating devices in regions the models were 
not designed for.

You should always look at the derivatives of your curves 
anyway. The derivative is more important than the data itself, 
and is often loaded with noise due to rounding and measurement 
noise. Take the derivative of your actual data tables and plot 
it. You may be in for a big surprise.
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<P>Ibis Gurus, 
<P>This brings up another question I have had for sometime now. I am wondering if there is a white paper on generating ibis models in the lab. I have upto now translated spice models to ibis, however if i ever needed to, how could i generate an ibis model from lab measurments? 
<P>Thanks, 
<P>Abdulrahman Rafiq&nbsp;&nbsp;<B><I>Al Davis &lt;[email-masked]&gt;</I></B> wrote:</P>
<BLOCKQUOTE style="BORDER-LEFT: #1010ff 2px solid; MARGIN-LEFT: 5px; PADDING-LEFT: 5px">On Tuesday 15 October 2002 02:58 pm, Ingraham, Andrew wrote:<BR>&gt; "VCC relative" means that 0V in the table, corresponds to Vin<BR>&gt; or Vout = VCC at the device pin or pad.<BR><BR>What confuses people is that the sign is flipped from what it <BR>logically ought to be. If you just flip the sign of the <BR>voltage, it makes sense.<BR><BR>&gt;<BR>&gt; In addition, the tables are arranged so that positive table<BR>&gt; values mean I/O voltages mostly within the normal range<BR>&gt; between GND and VCC, and negative table values are voltages<BR>&gt; below GND or above VCC, toward the clamps. (Obviously, if<BR>&gt; you go far enough in either direction, you will go beyond GND<BR>&gt; and VCC. Large positive table values correspond to voltages<BR>&gt; beyond the opposite supply rail.)<BR>&gt;<BR>&gt; Vtable = Vcc - Voutput.<BR><BR>Read this carefully .... It means the ground lead of your <BR>scope is hooked to the output, and the tip of the probe to the <BR>power supply.<BR><BR>The pullup is just like the pulldown except for the sign flip. <BR>It is a i/v table describing a nonlinear resistance, <BR>representing the channel of the output device. For pulldown, <BR>it is hooked from output to pulldown_reference. You measure <BR>the voltage across it. It just happens that pulldown_reference <BR>is often the same as ground, so the voltage to ground happens <BR>to match. For pullup, that device is hooked from output to the <BR>power supply (pullup_reference) and you measure the voltage <BR>across it. Unfortunately, in the standard, the sign of the <BR>voltage is flipped. Since the standard cannot be changed <BR>without breaking compatibility, we are stuck with it.<BR><BR><BR>&gt; This formula is applied only to the [Pullup] and [Power<BR>&gt; Clamp] tables. No such adjustment is made to the [Pulldown]<BR>&gt; and [GND Clamp] tables.<BR><BR>except for ECL types.<BR><BR>&gt; The step of subtracting the clamp currents from the simulated<BR>&gt; or measured currents, to get the values for the [Pullup] and<BR>&gt; [Pulldown] tables, is different. It has nothing to do with<BR>&gt; the fact that the [Pullup] and [Power Clamp] tables are VCC<BR>&gt; relative. They are two independent steps in the process. <BR>&gt; Subtracting the clamp currents prevents double counting when<BR>&gt; they are added back together by the simulator.<BR><BR>But be careful when you subtract. The way most people do it, <BR>they subtract two very large numbers and come up with a small <BR>number as the result. The pullup and pulldown curves are often <BR>nonsense in this region, showing something non-monotonic, which <BR>is usually wrong and sometimes causes trouble for simulators, <BR>if your simulator handles ground bounce. If you are not <BR>modeling ground bounce, they are in parallel and you don't see <BR>the problem. It is only a problem if pulldown_reference and <BR>ground_clamp_reference are different nodes, or likewise if <BR>pullup_reference and power_clamp_reference are different nodes.<BR><BR>A better approach is to take the derivatives of both curves, <BR>subtract the derivatives, smooth out the nonsense in the clamp <BR>region, and then integrate it. Simply dropping points is the <BR>best way to smooth the nonsense.<BR><BR>The data in this region is questionable anyway. Its main <BR>purpose is to put the simulator back on track when a stray <BR>iteration sends it there. It is important that it be well <BR>behaved. It is not so important for it to be accurate. This <BR>is fortunate, because you can't be accurate. If you try it <BR>with a real device, you will destroy it. If you try it with a <BR>simulator, you are operating devices in regions the models were <BR>not designed for.<BR><BR>You should always look at the derivatives of your curves <BR>anyway. The derivative is more important than the data itself, <BR>and is often loaded with noise due to rounding and measurement <BR>noise. Take the derivative of your actual data tables and plot <BR>it. You may be in for a big surprise.<BR>|------------------------------------------------------------------<BR>|For help or to subscribe/unsubscribe, email [email-masked]<BR>|with just the appropriate command message(s) in the body:<BR>|<BR>| help<BR>| subscribe ibis <OPTIONAL different if address, e-mail><BR>| subscribe ibis-users <OPTIONAL different if address, e-mail><BR>| unsubscribe ibis <OPTIONAL different if address, e-mail><BR>| unsubscribe ibis-users <OPTIONAL different if address, e-mail><BR>|<BR>|or email a written request to [email-masked].<BR>|<BR>|IBIS reflector archives exist under:<BR>|<BR>| http://www.eda.org/pub/ibis/email_archive/ Recent<BR>| http://www.eda.org/pub/ibis/users_archive/ Recent<BR>| http://www.eda.org/pub/ibis/email/ E-mail since 1993</BLOCKQUOTE><p><br><hr size=1>Do you Yahoo!?<br>
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------------------------------

Date: Wed, 16 Oct 2002 00:45:33 -0700 (PDT)
From: "Abdulrahman A. Rafiq" <[email-masked]>
Subject: Re: [IBIS-Users] Making Pullup curves VCC relative.

- --0-1093519616-1034754333=:45811
Content-Type: text/plain; charset=us-ascii

Ibis Gurus, 
This brings up another question I have had for sometime now. I am wondering if there is a white paper on generating ibis models in the lab. I have upto now translated spice models to ibis, however if i ever needed to, how could i generate an ibis model from lab measurments? 
Thanks, 
Abdulrahman Rafiq  Al Davis <[email-masked]> wrote:
On Tuesday 15 October 2002 02:58 pm, Ingraham, Andrew wrote:
> "VCC relative" means that 0V in the table, corresponds to Vin
> or Vout = VCC at the device pin or pad.

What confuses people is that the sign is flipped from what it 
logically ought to be. If you just flip the sign of the 
voltage, it makes sense.

>
> In addition, the tables are arranged so that positive table
> values mean I/O voltages mostly within the normal range
> between GND and VCC, and negative table values are voltages
> below GND or above VCC, toward the clamps. (Obviously, if
> you go far enough in either direction, you will go beyond GND
> and VCC. Large positive table values correspond to voltages
> beyond the opposite supply rail.)
>
> Vtable = Vcc - Voutput.

Read this carefully .... It means the ground lead of your 
scope is hooked to the output, and the tip of the probe to the 
power supply.

The pullup is just like the pulldown except for the sign flip. 
It is a i/v table describing a nonlinear resistance, 
representing the channel of the output device. For pulldown, 
it is hooked from output to pulldown_reference. You measure 
the voltage across it. It just happens that pulldown_reference 
is often the same as ground, so the voltage to ground happens 
to match. For pullup, that device is hooked from output to the 
power supply (pullup_reference) and you measure the voltage 
across it. Unfortunately, in the standard, the sign of the 
voltage is flipped. Since the standard cannot be changed 
without breaking compatibility, we are stuck with it.

> This formula is applied only to the [Pullup] and [Power
> Clamp] tables. No such adjustment is made to the [Pulldown]
> and [GND Clamp] tables.

except for ECL types.

> The step of subtracting the clamp currents from the simulated
> or measured currents, to get the values for the [Pullup] and
> [Pulldown] tables, is different. It has nothing to do with
> the fact that the [Pullup] and [Power Clamp] tables are VCC
> relative. They are two independent steps in the process. 
> Subtracting the clamp currents prevents double counting when
> they are added back together by the simulator.

But be careful when you subtract. The way most people do it, 
they subtract two very large numbers and come up with a small 
number as the result. The pullup and pulldown curves are often 
nonsense in this region, showing something non-monotonic, which 
is usually wrong and sometimes causes trouble for simulators, 
if your simulator handles ground bounce. If you are not 
modeling ground bounce, they are in parallel and you don't see 
the problem. It is only a problem if pulldown_reference and 
ground_clamp_reference are different nodes, or likewise if 
pullup_reference and power_clamp_reference are different nodes.

A better approach is to take the derivatives of both curves, 
subtract the derivatives, smooth out the nonsense in the clamp 
region, and then integrate it. Simply dropping points is the 
best way to smooth the nonsense.

The data in this region is questionable anyway. Its main 
purpose is to put the simulator back on track when a stray 
iteration sends it there. It is important that it be well 
behaved. It is not so important for it to be accurate. This 
is fortunate, because you can't be accurate. If you try it 
with a real device, you will destroy it. If you try it with a 
simulator, you are operating devices in regions the models were 
not designed for.

You should always look at the derivatives of your curves 
anyway. The derivative is more important than the data itself, 
and is often loaded with noise due to rounding and measurement 
noise. Take the derivative of your actual data tables and plot 
it. You may be in for a big surprise.
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|with just the appropriate command message(s) in the body:
|
| help
| subscribe ibis 
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| unsubscribe ibis 
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<P>Ibis Gurus, 
<P>This brings up another question I have had for sometime now. I am wondering if there is a white paper on generating ibis models in the lab. I have upto now translated spice models to ibis, however if i ever needed to, how could i generate an ibis model from lab measurments? 
<P>Thanks, 
<P>Abdulrahman Rafiq&nbsp;&nbsp;<B><I>Al Davis &lt;[email-masked]&gt;</I></B> wrote:</P>
<BLOCKQUOTE style="BORDER-LEFT: #1010ff 2px solid; MARGIN-LEFT: 5px; PADDING-LEFT: 5px">On Tuesday 15 October 2002 02:58 pm, Ingraham, Andrew wrote:<BR>&gt; "VCC relative" means that 0V in the table, corresponds to Vin<BR>&gt; or Vout = VCC at the device pin or pad.<BR><BR>What confuses people is that the sign is flipped from what it <BR>logically ought to be. If you just flip the sign of the <BR>voltage, it makes sense.<BR><BR>&gt;<BR>&gt; In addition, the tables are arranged so that positive table<BR>&gt; values mean I/O voltages mostly within the normal range<BR>&gt; between GND and VCC, and negative table values are voltages<BR>&gt; below GND or above VCC, toward the clamps. (Obviously, if<BR>&gt; you go far enough in either direction, you will go beyond GND<BR>&gt; and VCC. Large positive table values correspond to voltages<BR>&gt; beyond the opposite supply rail.)<BR>&gt;<BR>&gt; Vtable = Vcc - Voutput.<BR><BR>Read this carefully .... It means the ground lead of your <BR>scope is hooked to the output, and the tip of the probe to the <BR>power supply.<BR><BR>The pullup is just like the pulldown except for the sign flip. <BR>It is a i/v table describing a nonlinear resistance, <BR>representing the channel of the output device. For pulldown, <BR>it is hooked from output to pulldown_reference. You measure <BR>the voltage across it. It just happens that pulldown_reference <BR>is often the same as ground, so the voltage to ground happens <BR>to match. For pullup, that device is hooked from output to the <BR>power supply (pullup_reference) and you measure the voltage <BR>across it. Unfortunately, in the standard, the sign of the <BR>voltage is flipped. Since the standard cannot be changed <BR>without breaking compatibility, we are stuck with it.<BR><BR><BR>&gt; This formula is applied only to the [Pullup] and [Power<BR>&gt; Clamp] tables. No such adjustment is made to the [Pulldown]<BR>&gt; and [GND Clamp] tables.<BR><BR>except for ECL types.<BR><BR>&gt; The step of subtracting the clamp currents from the simulated<BR>&gt; or measured currents, to get the values for the [Pullup] and<BR>&gt; [Pulldown] tables, is different. It has nothing to do with<BR>&gt; the fact that the [Pullup] and [Power Clamp] tables are VCC<BR>&gt; relative. They are two independent steps in the process. <BR>&gt; Subtracting the clamp currents prevents double counting when<BR>&gt; they are added back together by the simulator.<BR><BR>But be careful when you subtract. The way most people do it, <BR>they subtract two very large numbers and come up with a small <BR>number as the result. The pullup and pulldown curves are often <BR>nonsense in this region, showing something non-monotonic, which <BR>is usually wrong and sometimes causes trouble for simulators, <BR>if your simulator handles ground bounce. If you are not <BR>modeling ground bounce, they are in parallel and you don't see <BR>the problem. It is only a problem if pulldown_reference and <BR>ground_clamp_reference are different nodes, or likewise if <BR>pullup_reference and power_clamp_reference are different nodes.<BR><BR>A better approach is to take the derivatives of both curves, <BR>subtract the derivatives, smooth out the nonsense in the clamp <BR>region, and then integrate it. Simply dropping points is the <BR>best way to smooth the nonsense.<BR><BR>The data in this region is questionable anyway. Its main <BR>purpose is to put the simulator back on track when a stray <BR>iteration sends it there. It is important that it be well <BR>behaved. It is not so important for it to be accurate. This <BR>is fortunate, because you can't be accurate. If you try it <BR>with a real device, you will destroy it. If you try it with a <BR>simulator, you are operating devices in regions the models were <BR>not designed for.<BR><BR>You should always look at the derivatives of your curves <BR>anyway. The derivative is more important than the data itself, <BR>and is often loaded with noise due to rounding and measurement <BR>noise. Take the derivative of your actual data tables and plot <BR>it. You may be in for a big surprise.<BR>|------------------------------------------------------------------<BR>|For help or to subscribe/unsubscribe, email [email-masked]<BR>|with just the appropriate command message(s) in the body:<BR>|<BR>| help<BR>| subscribe ibis <OPTIONAL e-mail address, if different><BR>| subscribe ibis-users <OPTIONAL e-mail address, if different><BR>| unsubscribe ibis <OPTIONAL e-mail address, if different><BR>| unsubscribe ibis-users <OPTIONAL e-mail address, if different><BR>|<BR>|or email a written request to [email-masked].<BR>|<BR>|IBIS reflector archives exist under:<BR>|<BR>| http://www.eda.org/pub/ibis/email_archive/ Recent<BR>| http://www.eda.org/pub/ibis/users_archive/ Recent<BR>| http://www.eda.org/pub/ibis/email/ E-mail since 1993</BLOCKQUOTE><p><br><hr size=1>Do you Yahoo!?<br>
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------------------------------

Date: Wed, 16 Oct 2002 11:55:37 +0200
From: Yoni Tzafrir <[email-masked]>
Subject: [IBIS-Users] running scripts with CosmoScope & Hspice

hi,
we are running Hspice, and viewing the results on CosmoScope on pc. in the
future we want to use scripts which can automatically plot results like tpd,
risetime, falltime, etc. due the various results to our deck file (e.g.
changing resistance, capacitance and so on).
does anyone experienced in doing so? maybe we can use the Aim, which is a
variation of tcl used for CosmoScope?
please advice

Yonatan (Yoni) Tzafrir
*Tel:               (972) - 3 - 7552300 (T/L: 351)
*Fax:          (972) - 3  - 6177130
  *Mobile:       (972) -54- 459469
*E-mail:       <mailto:[email-masked]>

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------------------------------

Date: Wed, 16 Oct 2002 11:53:45 -0700
From: "Angulo, John" <[email-masked]>
Subject: [IBIS-Users] IBIS ver 3.2 and 2.1

The following is posted on behalf of Mike Lamson at Texas Instruments.  Please send all private replies to [email-masked] only.

- ----------
I would like to convert some package IBIS file from ver 2.1 to ver 3.2.  Is
there any significant issue?  Is there a known process, method, software,
etc.?

Where can one obtain the 3.2 spec.?

Regards,

Mike
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Date: Wed, 16 Oct 2002 11:50:18 -0700
From: Eric Hsu <[email-masked]>
Subject: [IBIS-Users] version issue

This is a multi-part message in MIME format.
- --------------657011D1771214E6F882BE33
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Hi ,

First, can I use ver2.1 ibis model to describe like SSTL_II  I/O buffer?
If not, which version I should use and what's difference?
Second, can I use different version ibis model to describe multiple chip
in the same package? just like "MCM" case? For example, one chip vendor
perhaps provide v2.1 but the other is v3.2.

- -eric

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adr:;;450 National Ave.;Mountain. View;CA;94043;US
version:2.1
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------------------------------

Date: Wed, 16 Oct 2002 12:18:19 -0700 (PDT)
From: Syed Huq <[email-masked]>
Subject: Re: [IBIS-Users] version issue

SSTL2, HSTL, LVDS etc all can be descrined within v2.1

The answer to the 2nd question is also yes. You can have v2.1 and v3.2
within the MCM.

Syed

>Date: Wed, 16 Oct 2002 11:50:18 -0700
>From: Eric Hsu <[email-masked]>
>X-Accept-Language: en
>MIME-Version: 1.0
>To: [email-masked]
>Subject: [IBIS-Users] version issue
>
>Hi ,
>
>First, can I use ver2.1 ibis model to describe like SSTL_II  I/O buffer?
>If not, which version I should use and what's difference?
>Second, can I use different version ibis model to describe multiple chip
>in the same package? just like "MCM" case? For example, one chip vendor
>perhaps provide v2.1 but the other is v3.2.
>
>-eric

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------------------------------

Date: Wed, 16 Oct 2002 15:22:16 -0700 (PDT)
From: Syed Huq <[email-masked]>
Subject: [IBIS-Users] Re: [IBIS] running scripts with CosmoScope & Hspice

The NCSU Perl script s2iplt does waveform plotting using GNUplot.
You could start from there..

You can find this script once you untar the s2ibis2 file.

Syed

>From: Yoni Tzafrir <[email-masked]>
>To: "Si-List (E-mail)" <[email-masked]>, "'Ibis (E-mail)" 
<[email-masked]>, "Ibis-Users (E-mail)" <[email-masked]>
>Subject: [IBIS] running scripts with CosmoScope & Hspice
>Date: Wed, 16 Oct 2002 11:55:37 +0200
>MIME-Version: 1.0
>
>hi,
>we are running Hspice, and viewing the results on CosmoScope on pc. in the
>future we want to use scripts which can automatically plot results like 
tpd,
>risetime, falltime, etc. due the various results to our deck file (e.g.
>changing resistance, capacitance and so on).
>does anyone experienced in doing so? maybe we can use the Aim, which is a
>variation of tcl used for CosmoScope?
>please advice
>
>Yonatan (Yoni) Tzafrir
>*Tel:               (972) - 3 - 7552300 (T/L: 351)
>*Fax:          (972) - 3  - 6177130
>  *Mobile:       (972) -54- 459469
>*E-mail:       <mailto:[email-masked]>
>
>
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------------------------------

Date: Thu, 17 Oct 2002 11:40:01 +0200
From: [email-masked]
Subject: [IBIS-Users] Ground Bounce/SSO analysis

Signal Integrity Engineers,

Can somebody inform me how Ground Bounce and SSO effects can be simulated with an IBIS simulator? Which IBIS simulator?

Looking forward to receiving your reactions.

Kind regards,

Rob

__________________________________________________________________________
Rob Mataheroe                                                                                           Philips Semiconductors bv
P.G. Logic Product Group PD&S                                                           Building AM1.108
Senior Design Modeling Engineer                                                       Gerstweg 2
Tel. ++31 (0)24 353 2370                                                                           6534 AE Nijmegen
Fax. ++31 (0)24 353 2820                                                                          The Netherlands
Email: [email-masked]

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------------------------------

Date: Thu, 17 Oct 2002 11:48:07 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] Minutes, IBIS Open Forum Summit 10/15

Date: 10/17/02

SUBJECT: October 15, 2002 EIA IBIS Open Forum Summit Minutes

VOTING MEMBERS AND 2002 PARTICIPANTS LIST:
Ansoft Corporation             (Eric Bracken)
Apple Computer                 Kim Helliwell
Applied Simulation Technology  Fred Balistreri, Norio Matsui
Cadence Design                 Lynne Green*, Patrick dos Santos, Lance Wang*
Cisco Systems                  Syed Huq, Abdulrahmun Rafiq, Zhiping Yang,
                               Mike LaBonte*, Todd Westerhoff*
Cypress Semiconductor          (Rajesh Manapat)
Huawei Technologies            (Jiang Xiang Zhong)
IBM                            Greg Edlund*, Pravin Patel
Innoveda (Merged with Mentor   John Angulo, Guy de Burgh, Steve Gascoigne
  Graphics)
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Will Hobbs,
                               Pete Block, Ben Silva, Tony Lewis,
                               Michael Mirmak
LSI Logic                      [Larry Barnes], Frank Gasparik
Matsushita (Panasonic)         Atsuji Ito
Mentor Graphics                Bob Ross*, Ian Dodd*, Mike Donnelly,
                               Matt Hogan, Sherif Hammad, [Tom Dagostino],
                               Eric Rongere, Karine Loudet, Kevin Cohan*
Micron Technology              Randy Wolff
Mitsubishi                     Pat Hefferan
Molex Incorporated             Gus Panella
Motorola                       Rick Kingen
National Semiconductor         Milt Schwartz
NEC Corporation                (Akimoto Tetsuya)
North East Systems Associates  Edward Sayre*, Kathy Breda* 
Philips Semiconductor          (D.C. Sessions)
Quantic EMC                    (Mike Ventham)
Siemens (& Automotive) AG      Helmut Katzier, Katja Koller, Eckhard Lenski
Signal Integrity Software      Barry Katz*, Walter Katz, Robert Moles,
                               Daniel Nilsson, Kevin Fisher, Steve Coe,
                               Wiley Gillmor, Douglas Burns, Eric Brock,
                               Bob Haller*
Sigrity                        Raj Raghuram
SiQual                         [Scott McMorrow], Dave Macemon, Rob Hinz
Texas Instruments              Thomas Fisher*, Jean-Claude Perrin
Teraspeed                      (Scott McMorrow), Tom Dagostino*
Time Domain Analysis Systems   Steve Corey, Dima Smolyansky
Via Technologies               (Weber Chuang)
Zuken (& Incases)              Caroline Legendre, Ralf Bruening

OTHER PARTICIPANTS IN 2002:
3Com (& CommWorks)             [Roy Leventhal], James Goshorn
Actel                          Prabhu Mohan
Agilent                        Herbert Lage*
Airbus                         Claude Huet
Alstom Transport               Luca Giacotto*
Apt Software                   Atul Agarwal
Astrium                        Olivier Prieur
Bee Technologies Corporation   Tsuyoshi Horigome
Brocade Communications         Robert Badal
Compaq                         Shafier-ur-Rahman
EADS CCR                       Alix de la Villeguerin
EFM                            Ekkehard Miersch
EIA                            [Cecilia Fleming], Chris Denham
EMC Corporation                Brian Arsenault*, Jeanne Hereth*,
                               Elena Gutman*, Julian Simbu*
Fairchild Semiconductor        Adam Tambone
Force Computers                Roger Sukiennik
Harman/Becker Automotive       Hartmut Exler
  Systems
Hatachi                        Nonoyama Sadahiro*, Shoji Kazuyoshi*
Japan Electronics and          Kiyomi Daishido
  Information Technology
  Industries Association
  (JEITA)
Leventhal Design and           Roy Leventhal
  Communication
National Institute of Applied  Sebastian Calvet (& Motorola)
Science (INSA)                 Etienne Sicard, Stephane Baffreau
Northrup (Litton)              Robert Bremer
Sagam SA                       Quang Ngo, Matthieu Fontaines
Shindengen Elecric Mfg. Co.    [Tsuyoshi Horigome]
Sintecs                        Hans Klos
STMicroelectronics             Fabrice Boissieres
Synopsys (Avanti)              (Hailong Wang)
TDK                            Yoshikazu Fujishiro
Thales                         Saverio Lerose
Tyco Electronics               (Tim Minnick)
UTMC                           Greg Haynes
Xilinx                         Susan Wu, J.L. de Long
Independent                    Larry Barnes

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are
as follows:

  Date                Bridge Number    Reservation #    Passcode
  November 1, 2002    (916) 356-2663        2           2855166

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after.  When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES -----------------------------------
The fifth annual IBIS East Summit Meeting was held on October 15, 2002 at
the North East Systems Associates offices in Westford, Massachusetts, in
conjunction with the PCB Conference East in Boxborough Massachusetts.
Because of general industrial travel restrictions, a phone bridge and
optional web cast link were setup by Intel Corporation.

A total of 24 people representing 13 organizations participated.  Seven of
the participants attended by telephone.

INTRODUCTIONS AND BUSINESS
Stephen Peters welcomed the participants and thanked North East Systems
Associates (NESA), Cadence Design Systems, Intel Corporation, the IBIS Open
Forum and the IBIS Users group for there support in co-sponsoring the 
summit.  Stephen also thanked Kathy Breda and NESA for handling the
administrative and logistical details, and Cadence for supplying for the
delicious pre-meeting lunch.  Stephen also thanked Arpad Muranyi from Intel
for enabling the web based presentations.  Finally, Stephen noted that
questions and interactive discussion was encouraged.  

All of the presentations and meeting documentation were available at the
meeting and were also uploaded to the IBIS web site at:

   http://www.eda.org/pub/ibis/summits/oct02/ or
   http://www.eda.org/pub/ibis/summits/

Stephen stated that there were no business issues.  Stephen asked for any
open topics. None were offered.

KEYNOTE REMARKS
Stephen Peters introduced Ed Sayre, Chair of the IBIS Users Group for some 
keynote remarks.

Ed stated that IBIS is now a key ingredient for success in industry. While 
IBIS quality remains an issue, it is being addressed.  Ed believes that the
interconnect specification will become extremely important to the industry,
along with the ability for IBIS to contain many different types of models.

On the subject of IBIS versus SPICE models, Ed noted that the "best" model
depends on the application.  Ed also felt that tools should be categorized
by application, not what models the tool runs.  Ed remarked that the
industry does not need religious wars between SPICE and IBIS, the issue is
selecting the 'correct hammer for job'.

Ed expressed the concern that as each version of IBIS is released the syntax
is becoming more and more specialized.  He cautioned the Open Forum that it
is important to keep the syntax clean and self-consistent. Finally, Ed
noted that the vast majority of problems don't require models that use the 
complete IBIS feature set.

                  PRESENTATIONS AND DISCUSSION TOPICS
The rest of the meeting consisted of presentations and discussions.  These
notes capture some of the content and discussion.  See the uploaded
documents for more detail.

IBIS STATUS REPORT
Stephen Peters, Intel Corporation
Presenting via telephone, Stephen began his presentation by stating that
the organization remains a strong and relevant force in the industry.  We 
continue with 30 paid members, and the IBIS quality group is aggressively 
and successfully addressing the industry wide issue with model quality.  In
addition, over the last few months there has been active discussion on the
multi-lingual modeling proposal (BIRD75), with a vote scheduled during
the next regularly scheduled IBIS teleconference.  Stephen expects BIRD75
to significantly extend the life of IBIS modeling. 

On the subject of IBIS 4.0 parser development, Stephen announced that we
have selected (subject to ratification by the Open Forum) Atul Agarwal
as the parser developer. The winning bid was for $25,000. On the
downside, Stephen noted that the money we had set aside from previous years
to pay for parser development is no longer available.  The result is that
the IBIS Open Forum will have to raise substantially more money from the
member companies than was expected.  Stephen stated that the parser funding
issue will be fully discussed at the next teleconference meeting.
 
Finally, Stephen noted that the long awaited IBIS Interconnect Modeling
(ICM) specification has been released for review, and that work continues
on adding EMI and EMC support to IBIS.

The question was asked if the parser price included development of a parser
for the interconnect specification. Stephen replied that the quoted price
was for development of the IBIS 4.0 parser only. Ed Sayre then asked the
EDA vendors what their plans were for supporting IBIS 4.0 features.  Both
Mentor Graphics and Cadence responded that they plan support next year or
in the next release.

IBIS INTERCONNECT SPECIFICATION
Stephen Peters, Intel Corporation
Stephen opened this presentation by noting that a draft version of the 
Interconnect Specification (ICM version 1.0) has been released for
review and is available on the IBIS web site under the "connector
Info" link.

  http://www.eda.org/pub/ibis/connector/

So far, one extensive comment on the specification has been received.
Although there were no feature changes or additions to the specification
since the last update in June 2002, some minor technical and wording issues
were resolved.  Moving forward, Stephen stated that the next step is to
figure out how to pay for ICM parser development.  Stephen also mentioned
that the ICM specification can be used with the proposed multi-lingual
modeling bird to provide a complete model of the interconnect from the 
die on thru the package.

In a quick overview of the technical details, Stephen stated that the 
specification supports a single interconnect family; a family consists of
one or more individual models.  Models are described in terms of such basic
information as maximum slew rate allowed, the model type (single line or
multi-line model), a path description, and information that allows the EDA
tool to map model pins to the rows of an RLGC or S-parameter matrix.
Stephen also noted that the specification supports three different types
of interconnect -- regular (no pins missing) and rectangular, regular and
non-rectangular, and irregular.  Only regular interconnect is swathable.

Multi-line models (MLM) contain full coupling between pins or traces and are
intended to be used for simulations involving crosstalk and ground return
paths.  On the other hand, single line models (SLM) do not support crosstalk
information and are primarily intended to model a pin under specific
conditions.  Several different types of SLMs are available, including ones
created under even-mode, odd-mode and quiescent switching conditions.
Stephen noted that, for these models, the ground return path used to derive
the models values are documented in the models pin map.

Finally, Stephen pointed out that the data in the RLGC matrices can be 
interpreted as either lumped elements or as per-unit-length values. This 
interpretation is determined by a "Len" or "Mult" argument in the 
path description and the [Derivation Method] keyword in the matrix section.
Lumped elements result from 3-D field solver extraction of irregular
structures, and are suited for describing most connectors.  "Lump size" is
determined by the model created, and is based upon the maximum risetime the
connector is expected to support.  On the other hand, per-unit-length values
result from 2-D field extraction and are suited for describing the parallel
traces in a package.  Per-unit-length values are expected to be used in a
distributed transmission line model. 

Ed Sayre asked how time domain simulators were expected to use the frequency
based S-parameters matrix.  Arpad Muranyi replied that there are numerical
techniques that make S-parameters usable in a time domain simulator.  In
the reverse case, a frequency domain simulator can always take an IBIS
model, find the DC operating point, then linearize the model.  In the
following discussion it was noted that while most SI simulators are time
domain based, there are free to incorporate and use frequency domain based
models and techniques.  

Brian Arsenault from EMC asked how much support there is among the connector
vendors for the ICM spec.  Stephen replied that Gus Panella from Molex was
very active in defining the specification, so there is at least one 
connector vendor interested.  Stephen stated, however, that he would like
to see more than one vendor release ICM models.

IBIS QUALITY COMMITTEE REPORT
Barry Katz, Signal Integrity Software (SiSoft)
Barry began by presenting data on the number of downloadable IBIS files
that contain errors. Barry also made the point that even if a file passes
IBISCHK3 with no warnings or errors the model may still not be usable.
The parser doesn't capture everything that makes a good model.  Recognizing
this fact, the quality committee was formed.  Its charter is to develop
a checklist that defines levels of IBIS model quality and is usable
by purchasing and procurement organizations.  The committee was also tasked 
with suggesting enhancements to the current IBISCHK3 parser.  Barry noted
that the goal of any quality rating system is ease of use and understanding.
This is important because these specifications have to be communicated
to non engineers. 

Barry mentioned that the quality committee, which meets every two weeks,
includes participants from Europe, US and Japan.  Barry went on to
announce that the IBIS Quality Checklist is available at

  http://www.sisoft.com/ibis-quality/

Kevin Cohan asked if the quality level of a file is established by the
component as a whole or by each individual model.  Barry replied that this
is open for discussion, but that in general all models in a component must
be at level 1 for the component to be at level 1.  Barry went on to note
that at a minimum all models should parse with no errors and no warnings. 
Arpad Murani asked if this applies to version 1.1 and 2.1 models as well.
In the following discussion it was noted that different versions of the
parser check for different things, and it may be impossible to get 
earlier versions of the parser to a 'no warning' standard.  The question
was also asked if it was appropriate to fix non-monotonic warnings.  
According to Tom Dagostino, there are logic families that contain
outputs with non-monotonic I-V characteristics and the 'no-warning/no-error'
standard may not apply to these components.  A model creator must be aware
of them and document them appropriately.

The quality checklist documents four levels of quality.  A Level 0 model 
passes the parser and includes the data required to do a timing analysis
(values for Vinh and Vinl as well as the timing test loads). Level 1 models
are complete and correct with various levels of detail, including visual
inspection of I-V and V-T tables.  Also, to be classed as level 1 the model
must have been run thru a simulator.  It was noted that the model creator
should document what simulator ran model in.   Level 2 models addresses the
correlation of models to SPICE or silicon and leverages off the work of
the accuracy committee.  Level 3 models are correlated to both silicon and
SPICE.

Stephen Peters asked if the quality committee has considered taking on the
task of updating the s2ibis2 program. The committee has not discussed  
this, and suggested that this may be better handled by a new subcommittee.

MEASUREMENT BASED MODELING
Tom Dagostino, Teraspeed Consulting Group LLC
Tom stated that there are several advantages to creating IBIS models from
measurement.  Chief among them are the ability to create a model without
having to obtaining a Non-disclosure agreement (NDA) and the ability to  
create a model without needing access to a semiconductor companies
proprietary SPICE. Tom stated that it is also relatively easy to measure
the AC and DC characteristics of a device to the accuracy required (1% DC, 
>10Ghz bandwidth AC). However, Tom noted that AC measurements are limited
by the probing and fixturing.  Tom contend that anything you can do with 
SPICE you can do with SPICE, and in response to a question he stated that he

does have a measurement approach to multi-stage outputs.  If min/typ/max 
models are needed then access is required to full process silicon.

The required equipment includes a high bandwidth sampling scope, various
power supplies and a word generator (stimulus source) that is compatible
with the standard logic families (CMOS, ECL, PECL, CML, etc.)  In response
to a question, Tom stated that he uses a TDR for measuring C_comp, however
one can also use a VNA. Arpad Muranyi then asked how the outputs of a
complex chip are put into the correct logic state for I-V and V-T 
measurements.  Tom replied that, when available, he uses the JTAG port to
control output buffer state.

Tom controls the hardware setup via a software program that also writes 
the models. The measurement process starts with V-T data collection into
the standard 50 ohm loads, followed by I-V data acquisition.  I-V data is
collected by sweeping the output with a variable supply.  Arpad Muranyi
asked if he has seen any variations or errors because of die self heating.
Tom replied that he has not seen much I-V data variation due to this effect.

Tom did note that out of the 17,000 parts he has modeled, 98% of them have 
been at typical.

Tom then asked the audience if models that include temperature and voltage
variations but not process variations are useful.  Ed Sayre replied that
in real systems temperature variations across a chassis are a big variable,
so models of this type would be very useful.  Arpad Muranyi also pointed
out that many buffers incorporate compensation circuits that adjust their
output impedance based on temperature, so models created at various
temperatures may be required in order to do real corner testing. 

Finally, Stephen Peters asked how the effects of packaging are de-embedded
from the V-T data.  Arpad mentioned that this could be done numerically.
Tom replied that he does not try and de-embed package effects from the 
V-T data, and it would take several TDR/TDT measurements to characterize a
package.

SPICE VERSUS IBIS
Bob Haller, Signal Integrity Software (SiSoft)  
Bob opened his presentation by stating that contrary to popular belief
one can create IBIS models that produce waveforms which overlay
waveforms generated by transistor level SPICE circuits.

Bob noted that SPICE models can be accurate because they model such effects
as rail collapse, ground bounce and other buffer effects that are not
covered by IBIS.  Return paths can also be modeled using SPICE, although
Stephen Peters contended that modeling return paths was a tool capability 
issue, not an IBIS issue.  Disadvantage to using SPICE are performance and
inconsistencies between various versions.  There was a long discussion 
regarding how various SPICE vendors qualify there models and the tendency of
users to use only the SPICE version that the model was qualified under.

On the other hand, IBIS models don't reveal proprietary information and they
give a complete description of the component level pin out and AC/DC specs.
Disadvantages to using IBIS are the industry quality issues, and the 
previously mentioned limitations on packages.  Also mentioned was the 
simplistic model for C_comp modeling, and the amount of time it takes to
get things thru the IBIS committee.

In the discussion that followed Stephen Peters asked if anyone was able to
comment on practical limit to the I-V / V-T methodology of behavioral
modeling.  Arpad Muranyi mentioned that he is seeing buffers that employ
de-emphasis circuits that interact with standard I-V curves in ways that
may not be capturable by I-V curves alone.  Ed Sayre also mentioned the
difficulty of de-embedding V-T data thru a package. 

In summary, Bob states that the industry need both SPICE and IBIS models,
and the Open Forum must keep pushing forward.

MORE DETAILS ON TRUE DIFFERENTIAL BUFFER CHARACTERIZATION
Arpad Muranyi, Intel Corp. (presentation delivered via telephone)
Arpad presented a follow-up to the presentation given by Hazem Hegazy at
the January 2001 and March 2001 IBIS summits on how to model differential
models using single ended IBIS buffers.  In the previous presentations,
Hazem pointed out weakness in Aprad modeling methodology, and presented
a method that relied on determining both the differential and common mode
currents.  In this presentation Arpad proposes generalizing Hazem's method
by using the [Series Pin Mapping] keyword to include components that mimic
the differential currents of a true differential buffer. 

Arpads proposed method is to sweep the voltage and measure current on one
pin of the differential output, then step the voltage on the other pin and
repeat the sweep.  The result is then plotted on a 3-dimensional plot (a
surface plot in Excel).  The surface plot is used to both visualize the
currents as well as separate the common mode current from the differential
currents in a buffer.  This is done by normalizing the Ipin1 vs. Vpin1 vs.
Vpin2 plots to the common mode current.  The resulting plot is a plot of the
difference current.  As a proof that this method works, Arpad first
showed the surface plot of a buffer with a 1.4Kohm output impedance in the
operating region.  He then added a 100 ohm resistor across the output.  The
surface plot now showed that the output impedance of the buffer was 93
ohms, with is the parallel combination of 1.4Kohm and 100 ohm.  Finally,
while it may appear that multiple I-V curves are required to implement this
method, in the operating region the difference current is linear enough
to be represented by a fixed resistance, thus the use of the [R_series]
keyword.

Arpad noted that further study is required on developing a method to
extract differential C_comp.  In additon, experiments designed to figure
out how differential current varies with respect to time are required.
Arpad also urged CAE vendors to implement the series element keywords as
soon as possible.

Finally, Barry Katz offered that the method offered by Arpad was the 
mathematically correct way to represent a differential buffer. 

CLOSE OF MEETING
Stephen again thanked the participants for their contributions and thanked
the co-sponsors.  

NEXT MEETING:
The next teleconference meeting will be on Friday, November 1, 2002 from
8:00 AM to 10:00 AM Pacific time.  A vote on BIRD75.6 and BIRD77.2 is
scheduled.

============================================================================

                                      NOTES

IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
            [email-masked]
            Senior Hardware Engineer, Intel Corporation
            M/S JF4-215
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

VICE CHAIR: Lynne Green (425) 788-0412, Fax (425) 788-4289
            [email-masked]
            Senior Modeling Engineer, Cadence Design Systems
            20 120th Ave NE, Suite 103, Bellevue, WA 98005-3016

SECRETARY:  Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            [email-masked]
            Senior Manager, Mentor Graphics
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN:  Roy Leventhal (847) 590-9398
            [email-masked]
            Consultant, Leventhal Design and Communications
            1924 North Burke Drive
            Arlington Heights, Illinois 60004

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            [email-masked]
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008
            [email-masked]
            Development Engineer, Mentor Graphics
            14715 N.E. 95th Street, Suite 200
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This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

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Information on IBIS technical contents, IBIS participants, and actual
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Check the pub/ibis directory on eda.org for more information on previous
discussions and results.  You can get on via FTP anonymous.

============================================================================

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------------------------------

Date: Thu, 17 Oct 2002 13:01:38 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: RE: [IBIS-Users] Ground Bounce/SSO analysis

Hello Rob:

  We don't discuss specific simulator capabilities on the mail list, but in
general there are two ways of dealing with simulating ground bounce.  If you
have access to a 2D/3D field solver and the low level package/chip design,
you can approximate the on-die power distribution then use the [Pin Mapping]
keyword to describe the on-die power distribution. I personally haven't seen
a model that uses [Pin Mapping], and not many simulators support it (or
ground bounce simulations in general).

The other method is to take your V-T and I-V data under SSO conditions --
i.e. create a model with the effects of SSO imbedded in the data.  Of
course, the model is fixed for a specific number of outputs switching, but
the model can then be used in any simulator that supports IBIS.

 Hope this helps.
 
 Regards,
 Stephen Peters
 Intel Corp.

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]
Sent: Thursday, October 17, 2002 2:40 AM
To: [email-masked]
Subject: [IBIS-Users] Ground Bounce/SSO analysis

Signal Integrity Engineers,

Can somebody inform me how Ground Bounce and SSO effects can be simulated
with an IBIS simulator? Which IBIS simulator?

Looking forward to receiving your reactions.

Kind regards,

Rob

__________________________________________________________________________
Rob Mataheroe
Philips Semiconductors bv
P.G. Logic Product Group PD&S
Building AM1.108
Senior Design Modeling Engineer
Gerstweg 2
Tel. ++31 (0)24 353 2370
6534 AE Nijmegen
Fax. ++31 (0)24 353 2820
The Netherlands
Email: [email-masked]

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------------------------------

Date: Fri, 18 Oct 2002 10:00:37 -0700
From: Lieby David <[email-masked]>
Subject: [IBIS-Users] IBIS Model quality observation

Dear IBIS user colleagues,

I have been looking closely at some IBIS models for ECL
with an eye to cooking up a model for a chip that has no
model available from the manufacturer.  For this I am 
making a perhaps erroneous assumption that the IO cells
for portions of the ECL families are designed somewhat
the same.  I looked at the models for several devices in
each group, like EL and LVEL, and found that there were
small changes but not too much more than a few percent.

Some of the models had differences between the pins of
differential drivers and receivers.  I was sort of puzzled
over this until I looked closely at the [Pin] listing and
noted the differences in the contribution of the connecting
wire/pin combination.  The differences has some correlation.
When I reviewed what appeared to be the pin location VS the
numbers in the curve it looks like they measured one pin 
and then another (not the associated diff pin) and used 
them for the model.  So when the IBIS file is used the 
data for the driver is somewhat erroneous to start with
and then the pin data is folded in again.  Each pin has
a different set of pin impedance values though there is 
some symmetry.  What I am wondering is if there is a way
to use negative values for the pin impedance to adjust 
for the way the tables were generated.  (I have not tried
this yet.)

While I realize that most of the investigations I do are
going to only be close in the real world because of 
manufacturing tolerances, I would like to not have things
skewed to begin with.

Does anyone have a rule of thumb they use that could make
things like this a little less messy?

Best Regards,
dav0
David Lieby, SI Engineering
Acuson Corporation, a Siemens Company
1230 Shorebird Way
Mountain View, CA 94043

Building E
P.O. Box 7393
Mountain View, Ca 94039-7393
(650)694-5030
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------------------------------

Date: Mon, 21 Oct 2002 19:23:34 -0600
From: Al Davis <[email-masked]>(by way of Al Davis <[email-masked]>)
Subject: [IBIS-Users] A program for checking the derivatives

I have said several times that checking the derivative of
tables will reveal problems, and have been asked how and what
tools do it.

Following is a simple program that I use to check the
derivatives.  It takes an IBIS file as input, and produces an
output that looks like an IBIS file, but isn't.  It has the
derivatives substituted for the tables.

You can get the second derivative by running its output through
the program again, and the third derivative by running that
through the program.

It is hereby placed in the public domain, and is provided
without any warranty of any kind.  If it breaks, you get to
keep both pieces.

It is written in "awk", which is provided with most unix-type
systems.  I tested it on Mandrake gnu/linux, using gawk 3.1.0 .

Now that you have the tool, PLEASE check the derivatives of any
IBIS file that you release to the public!!!  If you really
care, check the second and third derivatives, too.

Here it is:
=====================================
#!/usr/bin/awk -f

/[a-df-zA-DF-Z|\*]/ {
  d1=0;
  d2=0;
  d3=0;
  d4=0;
  print;
  skip=1;
  next;
}

{
  if (skip) {
    printf("%16g skip\n", $1);
    skip=0;
  }else{
    dx = $1-d1;
    printf("%-16g %-16g %-16g %-16g\n", $1, ($2-d2)/dx,
           ($3-d3)/dx, ($4-d4)/dx);
  }
  d1=$1;
  d2=$2;
  d3=$3;
  d4=$4;
}
=====================================
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------------------------------

Date: Fri, 25 Oct 2002 08:18:00 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] Agenda, IBIS Open Forum Teleconference 11/01

		     IBIS Open Forum Meeting Agenda
			      for 11/01/02

		 Bridge Number    Reservation #   Passcode
             1-916-356-2663      2            2855166
                 (International Dial-In: 1-617-801-9781)

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Stephen Peters and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Peters

     - Intros of New IBIS Participants, Meeting Quorum       Peters
     - Call for Patents                                      Peters
     - Membership Update and Treasurers Report               Peters
     - Review of Previous Meeting's Minutes (and ARs)        Peters
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Leventhal, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters

     PCB Conference East IBIS Summit Meeting Feedback        Peters/Green

     DesignCon2002 IBIS Summit Meeting Planning              Peters

     IBIS Version 4.0 Parser Funding                         Peters

     IBIS Quality Committee                                  Katz

     IBIS Model Review Committee                             Green

     New Administrative Issues                               All

8:45 Technical Discussion

     IBIS Connector and Futures Group Report                 Peters/Green

     BIRD75.6 - Multi-Lingual IBIS Model Support             Ross/Muranyi
     BIRD77.1 - Differential Subparameter Additions          Ross
                (Vote)

     BIRD74.1 - EMI Parameters                               de Burgh

     BIRD78 - Comment Line Length Limit                      Green

     ibischk3 Status                                         Ross
     - BUG71 - Monotonic Checking for Combined I-V Tables    Haller
     - BUG74 - Missing Timing Test Load Warning Messages     Haller
     - BUG76 - External Package Under Win32 Requires         Ross
               Writeable Root

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Peters

9:55 Sign Off

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------------------------------

Date: Tue, 29 Oct 2002 15:38:02 +0530
From: Anshuli Goel <[email-masked]>
Subject: [IBIS-Users] Rload in s2ibis2 script

Hello IBIS users

I see that in s2ibis2 script we can ddefine the rload but if I want to
define capacitive load , how should I do it ?

Regards
Anshuli Goel

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------------------------------

Date: Tue, 29 Oct 2002 08:22:55 -0500
From: "Mike LaBonte" <[email-masked]>
Subject: RE: [IBIS-Users] Rload in s2ibis2 script

Rload specifies the resistor load for the ramp rate test. There
must be no other load elements for this test. The waveform simulations
can have capacitive loads, however. From the s2ibis2 doc:

    [Rising waveform]  R_f  V_f  V_f_min  V_f_max  L_f  C_f  R_d  C_d  L_d
    [Falling waveform] R_f  V_f  V_f_min  V_f_max  L_f  C_f  R_d  C_d  L_d

        R_f =     test fixture resistance
        V_f =     test fixture load voltage
        V_f_min = test fixture load voltage for MIN curve
        V_f_max = test fixture load voltage for MAX curve
        L_f =     test fixture inductance
        C_f =     test fixture capacitance
        R_d =     package parasitic resistance
        L_d =     package parasitic inductance
        C_d =     package parasitic capacitance

        Optional.
        Default: none.

        These keywords specify that s2ibis2 is to generate a rising or
        falling waveform using the parameters listed. Note that _all_
        columns must be filled, although only R_f and V_f must be
        specified. Please use the reserved word NA to fill a column
        whose value you do not wish to specify. You may have up to 100
        rising waveforms and 100 falling waveforms per model.

Mike LaBonte

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On
Behalf Of Anshuli Goel
Sent: Tuesday, October 29, 2002 5:08 AM
To: [email-masked]
Subject: [IBIS-Users] Rload in s2ibis2 script

Hello IBIS users

I see that in s2ibis2 script we can ddefine the rload but if I want to
define capacitive load , how should I do it ?

Regards
Anshuli Goel

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------------------------------

Date: Tue, 29 Oct 2002 12:21:09 -0800
From: Eric Hsu <[email-masked]>
Subject: [IBIS-Users] characteriztion issue

This is a multi-part message in MIME format.
- --------------3E4A9959DC964E878EA19DFF
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi all,

In case I wanna use s2ibis2 to generate individual ibis model(ver2.1)
from IO library, but not including header and component portion ( like
[IBIS ver], [File name], ...etc.), just model portion ( like [Model],
[Temperature Range],...etc.). Is there some option I should pick in my
control file?(*.s2i)

Best Regards,

~eric

- --------------3E4A9959DC964E878EA19DFF
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tel;fax:650.961.1092
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------------------------------

Date: Tue, 29 Oct 2002 12:50:44 -0800 (PST)
From: Syed Huq <[email-masked]>
Subject: Re: [IBIS-Users] characteriztion issue

If you are eventually going to run the parser on your IO library, you will 
need all those headers. You could leave the fields blank in the .s2i file.

I think you need the [IBIS ver] at least..

Syed

>Date: Tue, 29 Oct 2002 12:21:09 -0800
>From: Eric Hsu <[email-masked]>
>X-Accept-Language: en
>MIME-Version: 1.0
>To: ibis-users <[email-masked]>
>Subject: [IBIS-Users] characteriztion issue
>
>Hi all,
>
>In case I wanna use s2ibis2 to generate individual ibis model(ver2.1)
>from IO library, but not including header and component portion ( like
>[IBIS ver], [File name], ...etc.), just model portion ( like [Model],
>[Temperature Range],...etc.). Is there some option I should pick in my
>control file?(*.s2i)
>
>Best Regards,
>
>~eric

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------------------------------

Date: Tue, 29 Oct 2002 16:11:03 -0800
From: [email-masked]
Subject: Re: [IBIS-Users] s2ibis2

This is a multipart message in MIME format.
- --=_alternative 000102ED88256C62_=
Content-Type: text/plain; charset="us-ascii"

Thank you Syed, your input was very helpful.
Now I tried s2ibs2 with my data and could generate curve list in the e.g. 
"put58.lis" but cannot create ibs file with the message:

"Data begin marker transfer not found in output file"

Output file is:
Output strored in file => put58.lis
HSPICE job put58.spi completed

What is missing?

Thanks and Regards
Arzu Simsek 
#949 - 483 - 5714
- --=_alternative 000102ED88256C62_=
Content-Type: text/html; charset="us-ascii"

<br><font size=2 face="sans-serif">Thank you Syed, your input was very helpful.</font>
<br><font size=2 face="sans-serif">Now I tried s2ibs2 with my data and could generate curve list in the e.g. &quot;put58.lis&quot; but cannot create ibs file with the message:</font>
<br>
<br><font size=2 face="sans-serif">&quot;Data begin marker transfer not found in output file&quot;</font>
<br>
<br><font size=2 face="sans-serif">Output file is:</font>
<br><font size=2 face="sans-serif">Output strored in file =&gt; put58.lis</font>
<br><font size=2 face="sans-serif">HSPICE job put58.spi completed</font>
<br>
<br><font size=2 face="sans-serif">What is missing?<br>
<br>
<br>
Thanks and Regards<br>
Arzu Simsek <br>
#949 - 483 - 5714</font>
- --=_alternative 000102ED88256C62_=--
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------------------------------

Date: Tue, 29 Oct 2002 16:18:27 -0800 (PST)
From: Syed Huq <[email-masked]>
Subject: Re: [IBIS-Users] s2ibis2

It is most likely a simple error in the .s2i file. 

Look thru the .lis files to see if any errors.
Look at the .out file to see if the V/I tables are there.

Syed

>From: <[email-masked]>
>To: Syed Huq <[email-masked]>
>Cc: [email-masked], [email-masked]
>Subject: Re: [IBIS-Users] s2ibis2
>MIME-Version: 1.0
>Date: Tue, 29 Oct 2002 16:11:03 -0800
>X-MIMETrack: Serialize by Router on NPBSMTP1/Server/Conexant(Release 
5.0.11  |July 24, 2002) at 10/29/2002 04:11:01 PM, Serialize complete at 
10/29/2002 04:11:01 PM
>
>Thank you Syed, your input was very helpful.
>Now I tried s2ibs2 with my data and could generate curve list in the e.g. 
>"put58.lis" but cannot create ibs file with the message:
>
>"Data begin marker transfer not found in output file"
>
>Output file is:
>Output strored in file => put58.lis
>HSPICE job put58.spi completed
>
>What is missing?
>
>
>Thanks and Regards
>Arzu Simsek 
>#949 - 483 - 5714

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------------------------------

Date: Thu, 31 Oct 2002 08:41:36 -0800
From: "Ross, Bob" <[email-masked]>
Subject: [IBIS-Users] No Vendor/Commercial Discussions

To All:

We need to move ALL vendor specific questions and discussions
off of the IBIS lists.  These topics can be handled privately
or on another list.

The IBIS policy, through its affiliation with the national
standards organizations EIA and GEIA, is to forbid commercial
discussions regarding company plans, and products (features,
price, promotion, etc.).

Bob Ross
Mentor Graphics
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------------------------------

Date: Thu, 31 Oct 2002 11:36:13 -0800 (PST)
From: "Milton Schwartz x3261" <[email-masked]>
Subject: [IBIS-Users] Wire characteristics

Looking for curves of Lo and Co vs frequency for 22 guage wire.
Appreciate any links etc.
Tried Belden web site; unsuccessful

regards, milt

email: [email-masked]
phone: 408 721 3261

Milt Schwartz
Interface Applications
National Semiconductor

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------------------------------

Date: Thu, 31 Oct 2002 15:49:57 -0500
From: "Ingraham, Andrew" <[email-masked]>
Subject: RE: [IBIS-Users] Wire characteristics

> Looking for curves of Lo and Co vs frequency for 22 guage wire.

Both Lo and Co are strongly (i.e., mostly) dependent on the
separation between the wire and the return path, usually ground.

If the wire is not placed close to a ground plane, you may have
a hard time quantifying them.  (You need to ask: capacitance to
what?)  Think about the characteristic impedance of just a wire
by itself.  Is there one?  Zo = sqrt(Lo/Co).

There are formulas for the inductance of a wire alone, but these
are relatively useless because the self inductance of a straight
wire is moderately meaningless.  You really need to look at the
loop that the current takes, out and back.

If you want an earful on the subject, you could direct this question
to the Signal Integrity si-list on freelists.org.

Regards,
Andy

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------------------------------

Date: Mon, 4 Nov 2002 17:56:29 -0800 
From: "Angulo, John" <[email-masked]>
Subject: [IBIS-Users] using ibis with spice/ specctra

The following is posted on behalf of Bill Panos at Sanmina-SCI Corp.  Please send any private replies to [email-masked] only.

- -------------------------------------------

typical is there is no power or gnd pins assigned in the ibis model
(right?) just output and input pins. How does one really adjust say the
nominal VCC (VDD) to say the maximum voltage value...possibly I'm just
missing something on how ibis models functions.

thanks

Bill

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------------------------------

Date: Mon, 4 Nov 2002 17:59:11 -0800 
From: "Angulo, John" <[email-masked]>
Subject: [IBIS-Users] IBIS questions

The following is posted on behalf of Peleg Itzik at Galileo.  Please send any private replies to [email-masked] only.  

- -----------------------------------

Hello Ibis users

I have made several ibis models by spice to ibis converter (s2ibis2
from NCSU) also I did simulations on both spice and ibis models.

I have some questions regarding the ibis format:

1) C_comp parameter: what are the ways to extract this parameter from
the
spice model of the pad & of the package?
2) What do I lose if my ibis model does not include the C_comp
parameter?
3) Ibis standard 3.2 allow a more precise package modelling for
substrate
and bonding wire separately. Does the simulation software vendors
support
package modelling of ibis standard 3.2? Please let me know about the
vendors
or products supporting ibis standard 3.2 package modelling ?
4) I got recommendation to model the package using *.EBD file. Does the
EBD
format widely supported by the ibis simulation software vendors  ? which
format is preferred for package modelling: EBD or  package modelling of
ibis standard 3.2?

Thank you

Peleg itzik
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------------------------------

Date: Wed, 6 Nov 2002 09:37:48 -0800 
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] BIRD79 - Non-linear buffer impedance (extension to C_comp)

Greetings:

  Below is a new BIRD submitted by Luca Giacotto and Arpad Muranyi.  BIRD79
greatly enhances IBIS's ability to describe the non-linear and frequency
dependant characteristics of buffer impedance.

BIRD79 will be discussed at the November 22 teleconference.

  Regards,
  Stephen Peters
  Intel Corp.
  Chair, EIA/IBIS Open Forum

========================================================================
                   Buffer Issue Resolution Document  (BIRD)

BIRD ID#:      79
ISSUE TITLE:   Non-linear buffer impedance (extension to C_comp)
REQUESTOR:     Luca Giacotto (Alstom Transport) and Arpad Muranyi (Intel
               Corp.)

DATE SUBMITTED:  November 6, 2002
DATE REVISED:    
DATE ACCEPTED BY IBIS OPEN FORUM:

****************************************************************************
**
****************************************************************************
**

STATEMENT OF THE ISSUE:

This BIRD aims to improve the modeling of the reactive component of the
buffer
impedance, currently represented by keywords C_comp and C_comp_*.  (C_comp_*
was introduced in BIRD 65.2 and is now part of the IBIS 4.0 specification).
This extension models the non-linear (voltage dependent),
frequency-dependent
and state-dependent impedance behaviour of real buffers (as represented by
the
transistor-level model).  These improvements were already foreseen in the
bottom comments of BIRD 65.2.

****************************************************************************
**

STATEMENT OF THE RESOLVED SPECIFICATIONS:

A new optional keyword [PZ Impedance] (abbreviation for "Pole/Zero
Impedance")
shall be introduced, with 24 possible subparameters. The new keyword should
be
placed in the Model section, after the [Model] keyword.

|===========================================================================
==
|     Keyword:  [PZ Impedance] 
|    Required:  No
| Description:  Used to enhance the modeling of the buffer impedance, beyond
|               the possibilities given by the C_comp* subparameters in the
|               [Model] keyword. It allows to account for the
|                  a) non-linear,
|                  b) frequency-dependent,
|                  c) state-dependent
|               behavior of the buffer impedance.
|  Sub-Params:  Pole_high_pullup, Zero_high_pullup, Pole_high_pulldown,
|               Zero_high_pulldown, Pole_high_gndclamp, Zero_high_gndclamp,
|               Pole_high_pwrclamp, Zero_high_pwrclamp,
|               Pole_low_pullup, Zero_low_pullup, Pole_low_pulldown,
|               Zero_low_pulldown, Pole_low_gndclamp, Zero_low_gndclamp,
|               Pole_low_pwrclamp, Zero_low_pwrclamp,
|               Pole_in_pullup, Zero_in_pullup, Pole_in_pulldown,
|               Zero_in_pulldown, Pole_in_gndclamp, Zero_in_gndclamp,
|               Pole_in_pwrclamp, Zero_in_pwrclamp.
| Usage Rules:  These subparameters define the pole/zero behavior of the
|               buffer impedance at various die-node voltage values, and in
|               each of the three basic states (whichever applicable to the 
|               specific buffer type): "output high", "output low" and
input".
|               The four impedances in each state should be thought as a
|               reactive network shunted to the corresponding I-V table.
|               Moreover, the pole/zero data account for the presence of the
|               I-V tables.
|
|               Each of these subparameters, when present, is followed by a
|               F-V table. The first column
|               contains the voltage value at the die node, and the three
|               remaining columns hold the typical, minimum, and maximum
|               frequency values in [Hz]. The four entries, Voltage,
req(typ),
|               Freq(min), and Freq(max) must be placed on a single line and
|               must be separated by at least one white space.
|
|               All four columns are required under these subparameters. If
|               typical, minimum and/or maximum frequency values are not
|               available, the reserved word "NA" must be used.
|
| Other Notes:  A typical [PZ Impedance] description could contain two sets
of
|               Pole* tables and one set of Zero* tables. Or, just one set
of
|               Pole* tables.
|---------------------------------------------------------------------------
- --
[PZ Impedance]
|"HIGH-state":
| *) a 2nd order non-linear impedance for the pullup element
| *) a 1st order non-linear impedance for the pulldown element
|pole_high_pullup    |this is pole "1" in the high-state, related to the
pullup
                    |element
| [Volt]     typ [Hz]     min [Hz]      max [Hz]
    0V        6.37E7        NA            NA
    1V        5.36E7        NA            NA
    2V        1.15E8        NA            NA
|   ...       ...           ...           ...
    5V        2.53E8        NA            NA
|
zero_high_pullup    |this is the zero in the high-state, related to the
pullup
                    |element
    0V        3.00E8        NA            NA
    1V        2.83E7        NA            NA
|   ...       ...           ...           ...
    5V        2.56E8        NA            NA
|
pole_high_pullup    |this is pole "2" in the high-state, related to the
pullup
                    |element
    0V        9.28E8        NA            NA
|   ...       ...           ...           ...
|
pole_high_pulldown  |this is the pole in the high-state related to the
pulldown
                    |element
    0V        5.37E7        NA            NA
    1V        5.22E7        NA            NA
    2V        9.05E7        NA            NA
|   ...       ...           ...           ...
    5V        2.03E8        NA            NA
|
|"LOW-state":
|(1st order NL impedance for both the pullup and pulldown elements)
pole_low_pullup    |this is the pole in the low-state related to the pullup
    0V        2.00E8        NA            NA
|   ...       ...           ...           ...
|
pole_low_pulldown  |this is the pole in the high-state related to the
pulldown
    0V        5.25E9        NA            NA
|   ...       ...           ...           ...
    5V        4.24E8        NA            NA
|
|===========================================================================
==

****************************************************************************
**

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

The fixed valued (constant) C_comp or C_comp* subparameters don't have the
ability to describe the voltage-dependent (i.e., non-linear) and
state-dependent behaviour of the die capacitance. Moreover, there are
buffers
showing an impedance that is also strongly frequency-dependent. This BIRD
intend to extend the concept of "die-capacitance" to "die-impedance",
making the necessary data available for a simulator to implement it.

The improvement in the impedance modeling that can be obtained with the
adoption of a second order non-linear "die-impedance" has been demonstrated
in
the presentation at the June'02 IBIS Summit by Luca Giacotto (the URL is
http://www.eda.org/pub/ibis/summits/jun02/giacotto.pdf). Formulas and a
modeling method can be found in the presentation too. 

To meet the needs of power delivery or supply noise simulations, the 
non-linear network from the above presentation has been splitted into four 
networks, following the idea of BIRD 65.2. 

How to arrange the data in IBIS

Three options were considered for arranging the new data in the
specification:

1) A new keyword with 24 subparameters (as in this version of the BIRD).

2) 6 new subparameters in each of the I-V table keywords (pole_high, 
zero_high, pole_low, zero_low, pole_in, zero_in).

3) Adding the subparameters directly in the [Model] keyword, beside the
basic
C_comp* subparameters. Actually, this option has been avoided because of the
high number of subparameters (24) needed to cover all the types of buffers.

****************************************************************************
**
ANY OTHER BACKGROUND INFORMATION:

Documents related to this BIRD (available on the IBIS website):
  - presentations at the Paris (March 2002) and New Orleans (June 2002) IBIS
    summits;
  - BIRD 65.2;
  - Arpad Muranyi's presentation at the June 2001 IBIS summit, in which the
problem of the non-linear impedance modeling was first brought up (pp.
10-13).

****************************************************************************
**
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------------------------------

Date: Thu, 7 Nov 2002 10:57:51 -0800
From: "Laxmi Vishwanathan" <[email-masked]>
Subject: [IBIS-Users] LVDS TERMINATION 

Hi All,
It looks the my simulations did not show the 100 ohm internal resistor
terminator. It seems that not all simulators support the or take account of
100ohm of internal resistor. Is my understanding correct? If so, the data
cannot be used as it is for IBIS simulation. Please let me know how to
simulation on the differential input, like LVDS and LVPECL?or which
simulators could I use.
thanks,
Laxmi.

Laxmi Vishwanathan
Application Engineer
Lattice Semiconductor

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------------------------------

Date: Thu, 7 Nov 2002 18:16:32 -0500
From: "Lynne Green" <[email-masked]>
Subject: [IBIS-Users] First Call for IBIS DesignCon Summit

- -----------------------------------------------------------------------
		IBIS SUMMIT
		FIRST CALL FOR
	PARTICIPATION & PRESENTATIONS
- -----------------------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

              I B I S   S U M M I T   M E E T I N G

Time/Date:      Monday January 27, 2003,  8:00 AM to 5:00 PM

Location:   Magnolia Room 
                Santa Clara Convention Center
                Santa Clara, CA

Content:       Presentations and Discussions

Purpose:       Solicit and Exchange IBIS Model Related Information and
Ideas.

Sponsors:     DesignCon, National Semiconductor

DesignCon: January 27-30, 2003
		Santa Clara Convention Center
		Santa Clara, California
		See <http://www.designcon.com/2003/> for more
information.

BACKGROUND

DesignCon is the premier annual Silicon Valley event for the electronic
design automation (EDA) and semiconductor industry.  Topics of current
interest to the EIA IBIS Open Forum are addressed at DesignCon.

This meeting will be conducted as a formal IBIS Summit Meeting.
Presentation are expected to be available and archived in an electronic
format, and minutes of the meeting will be issued.  Any pending formal
decisions (votes) will be announced at least two weeks prior to the
meeting.

CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development, and
digital circuit design are invited to participate to the Summit meeting.
If you plan to participate, please register with the information below:

   Name:
   E-mail address:
   Company:
   Telephone:

Send to:

    Milt Swartz at National Semiconductor ([email-masked])

CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS experiences
or issues.

Format of Presentation:  Overhead Projections.
			LCD Projection may be available.  It is
recommended
			that those wishing to use LCD projection bring
their
			presentation on a CD or send it electronically.
Time:			15-30 Minutes
Electronic Archival:	We request electronic versions so that the
			presentations can be archived and also made
			available to non-attendees.  Formats used in
			the past have been text, Power Point, Word,
			Postscript, and Acrobat.  Electronic
presentations
			should be made available by January 22, 2003
			for uploading and copying.

If you plan a presentation, please supply

   Title:
   Presenter:
   E-mail address:
   Company:
   Telephone:

   Estimate Time:

Send this to:

  Lynne Green ([email-masked])

AGENDA

The agenda includes presentations, discussions, breaks, and a luncheon
(which will be provided).  This will be developed as presentation
proposals are received.

LIST OF NEARBY HOTELS

See <http://www.designcon.com/2003/hotel.html> for travel directions,
hotels and other information.
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------------------------------

Date: Fri, 8 Nov 2002 15:39:25 +0100
From: [email-masked]
Subject: [IBIS-Users] Inputs and I/Os with

Hello Ibis collegues,

I have the following questions about input and I/O buffers with bus hold:

1. If the bushold characteristic is present in the ground clamp curve, how would you find this:
1a Wrong, since it causes non-monotonic warnings
1b. Useless
1c. Okay, since it represents the actual behavior.
1d. Other ....

2. Did anyone ever create a Bus Hold submodel?
2.1 Which part of the circuit is described by the sub model?
2.2 How can I get more information about this subject?

Thank you in anticipation for your reactions.

Kind regards,

Rob

__________________________________________________________________________
Rob Mataheroe                                                                     Philips Semiconductors bv
P.G. Logic Product Group PD&S                                     Building AM1.108
Senior Design Modeling Engineer                                  Gerstweg 2
Tel. ++31 (0)24 353 2370                                                      6534 AE Nijmegen
Fax. ++31 (0)24 353 2820                                                     The Netherlands
Email: [email-masked]

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------------------------------

Date: Fri, 8 Nov 2002 15:48:03 -0800
From: [email-masked]
Subject: [IBIS-Users] Dual Pads

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Does anyone have experience with dual pads. If yes, how do you simulate 
these pads and what is the correct way to put them in IBIS format?

Thanks and Regards
Arzu Simsek 
#949 - 483 - 5714
- --=_alternative 0082BDE688256C6B_=
Content-Type: text/html; charset="us-ascii"

<br><font size=2 face="sans-serif">Does anyone have experience with dual pads. If yes, how do you simulate these pads and what is the correct way to put them in IBIS format?<br>
<br>
<br>
Thanks and Regards<br>
Arzu Simsek <br>
#949 - 483 - 5714</font>
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------------------------------

Date: Fri, 8 Nov 2002 16:15:17 -0800
From: "Tom Dagostino" <[email-masked]>
Subject: RE: [IBIS-Users] Dual Pads

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Do you mean by dual pads, 2 pins on a package driven by the same internal
driver?

If this is the case the easiest way of modeling this is to model one of the
pins with the model statement and then use a series R of 1 milliOhm to
connect the two pins together.

23 TestcaseA Outputbuffer R  L  C
24 TestcaseB NC              R  L  C

Series Pin mapping section
23   24

Series R model
model for a 1 milliOhm resistor

[Model] Outputbuffer
Buffer model

Tom Dagostino

Device Modeling Division

Teraspeed Consulting Group LLC

2926 SE Yamhill St.

Portland, OR 97214

(503) 430-1065

[email-masked]

http://www.teraspeed.com

  -----Original Message-----
  From: [email-masked]
[mailto:[email-masked]]On Behalf Of
[email-masked]
  Sent: Friday, November 08, 2002 3:48 PM
  To: [email-masked]'; [email-masked]
  Subject: [IBIS-Users] Dual Pads

  Does anyone have experience with dual pads. If yes, how do you simulate
these pads and what is the correct way to put them in IBIS format?

  Thanks and Regards
  Arzu Simsek
  #949 - 483 - 5714

- ------=_NextPart_000_0217_01C28742.07878B30
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	charset="us-ascii"
Content-Transfer-Encoding: quoted-printable

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<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">

<META content=3D"MSHTML 5.50.4916.2300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =

size=3D2>Do&nbsp;you mean by dual pads, 2 pins on a package driven by =
the same=20
internal driver?</FONT></SPAN></DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =
size=3D2>If=20
this is the case the easiest way of modeling this is to model one of the =
pins=20
with the model statement and then use a series R of 1 milliOhm to =
connect the=20
two pins together.</FONT></SPAN></DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =
size=3D2>23=20
TestcaseA Outputbuffer R&nbsp; L&nbsp; C</FONT></SPAN></DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =
size=3D2>24=20
TestcaseB=20
NC&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;=20
R&nbsp; L&nbsp; C</FONT></SPAN></DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =
size=3D2>Series=20
Pin mapping section</FONT></SPAN></DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =

size=3D2>23&nbsp;&nbsp; 24</FONT></SPAN></DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =
size=3D2>Series=20
R model</FONT></SPAN></DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =
size=3D2>model=20
for a 1 milliOhm resistor</FONT></SPAN></DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =

size=3D2>[Model] Outputbuffer</FONT></SPAN></DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =
size=3D2>Buffer=20
model</FONT></SPAN></DIV>
<DIV><SPAN class=3D118270900-09112002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV class=3DSection1>
<P style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Tom Dagostino</SPAN></P>
<P style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Device Modeling =
Division</SPAN></P>
<P style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Teraspeed Consulting Group =

LLC</SPAN></P>
<P style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">2926 SE Yamhill =
St.</SPAN></P>
<P style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Portland, OR =
97214</SPAN></P>
<P style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">(503) 430-1065</SPAN></P>
<P style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial">[email-masked]</SPAN></P>
<P style=3D"MARGIN: 0in 0in 0pt"><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Arial">http://www.teraspeed.com</SPAN></P></DIV>
<BLOCKQUOTE>
  <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B>=20
  [email-masked] =
[mailto:[email-masked]]<B>On=20
  Behalf Of </B>[email-masked]<BR><B>Sent:</B> Friday, =
November 08,=20
  2002 3:48 PM<BR><B>To:</B> [email-masked]';=20
  [email-masked]<BR><B>Subject:</B> [IBIS-Users] Dual=20
  Pads<BR><BR></FONT></DIV><BR><FONT face=3Dsans-serif size=3D2>Does =
anyone have=20
  experience with dual pads. If yes, how do you simulate these pads and =
what is=20
  the correct way to put them in IBIS format?<BR><BR><BR>Thanks and=20
  Regards<BR>Arzu Simsek <BR>#949 - 483 - =
5714</FONT></BLOCKQUOTE></BODY></HTML>

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------------------------------

Date: Mon, 11 Nov 2002 12:00:10 -0800
From: Eric Hsu <[email-masked]>
Subject: [IBIS-Users] C_comp issue?

Hi All,

What is the [c_comp] role in ibis? If changing [c_comp] value, will I
get different results in rising/falling waveform?

Best Regards,

- -eric

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------------------------------

Date: Mon, 11 Nov 2002 12:46:53 -0800
From: "Peters, Stephen" <[email-masked]>
Subject: RE: [IBIS-Users] C_comp issue?

Hello Eric:

  C_comp represents the I/O (input or ouptut) capacitance of the driver or
reciever itself.  It is the capacitace seen when standing on the pad of the
die and looking back into the I/O cell.  

  Changing C_comp will effect a number of things, but yes -- C_comp has a
direct effect on a drivers rise or fall time and waveforms.

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: Eric Hsu [mailto:[email-masked]]
Sent: Monday, November 11, 2002 12:00 PM
To: [email-masked]
Cc: [email-masked]
Subject: [IBIS-Users] C_comp issue?

Hi All,

What is the [c_comp] role in ibis? If changing [c_comp] value, will I
get different results in rising/falling waveform?

Best Regards,

- -eric

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------------------------------

Date: Mon, 11 Nov 2002 12:39:41 -0800
From: bpanos <[email-masked]>
Subject: Re: [IBIS-Users] C_comp issue?

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C_comp I believe refers to component capacitance, its role is to account
for the capacitance associated with the component itself as it is
attached to the pcb and yes, if you change the component capacitance the
risetimes/falltimes of the waveforms will change

regards,
Bill

Eric Hsu wrote:

> Hi All,
>
> What is the [c_comp] role in ibis? If changing [c_comp] value, will I
> get different results in rising/falling waveform?
>
> Best Regards,
>
> -eric
>
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------------------------------

Date: Mon, 11 Nov 2002 16:34:23 -0500
From: "Todd Westerhoff" <[email-masked]>
Subject: RE: [IBIS-Users] C_comp issue?

There are a few points here worth mentioning - if only to verify that I
understand how this stuff is *supposed* to work.

If you vary the C_comp value of the *receiver* on a net - then yes, I expect
to see the waveforms change, as you're effectively changing the loading the
receiver places on the net.

However, if you vary the value of C_comp for the *driving* device, then the
fact that you've changed C_comp will *only* affect any reflections on the
net that get back to the driver.  In other words, changing the driving
device's C_comp value does *NOT* affect its actual behavior as a driver;
only its behavior as a load is affected.  This is true whether the driver is
acting as a receiver (i.e. an I/O in the "input" state), or whether the
driver is absorbing reflections (i.e. the driver is "quiet" because it has
stopped sweeping the V-T curve).

... all of which is a long-winded way of saying that IBIS simulators place
C_comp in parallel with the driver's output and then compensate its presence
out; thereby reproducing the V-T behavior from the IBIS model.  So, changing
the value of C_comp doesn't actually change the output's *driving* behavior.

Am I understanding this correctly, or have I gotten myself confused again?

Todd ;-}

Todd Westerhoff
Signal Integrity Engineer
Cisco Systems
250 Apollo Drive - Chelmsford, MA - 01824
email:[email-masked]
ph: 978-497-0272
============================================

"When did the choices get so hard, with so much more at stake?
 Life gets mighty precious when there's less of it to waste"

- - Bonnie Raitt, "Nick of Time"

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On
Behalf Of Peters, Stephen
Sent: Monday, November 11, 2002 3:47 PM
To: 'Eric Hsu'; [email-masked]
Subject: RE: [IBIS-Users] C_comp issue?

Hello Eric:

  C_comp represents the I/O (input or ouptut) capacitance of the driver or
reciever itself.  It is the capacitace seen when standing on the pad of the
die and looking back into the I/O cell.

  Changing C_comp will effect a number of things, but yes -- C_comp has a
direct effect on a drivers rise or fall time and waveforms.

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: Eric Hsu [mailto:[email-masked]]
Sent: Monday, November 11, 2002 12:00 PM
To: [email-masked]
Cc: [email-masked]
Subject: [IBIS-Users] C_comp issue?

Hi All,

What is the [c_comp] role in ibis? If changing [c_comp] value, will I
get different results in rising/falling waveform?

Best Regards,

- -eric

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------------------------------

Date: Mon, 11 Nov 2002 14:44:30 -0600
From: "Lamson, Mike" <[email-masked]>
Subject: [IBIS-Users] IBIS Package Model with Multiple Ground Planes and Redundant Port s

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How can an IBIS package model be constructed with multiple ground planes
that have the same input ports at the chip and the same output ports at the
package ball?  That is, there are two current paths starting at the same
chip bump and going to the same package ball but on different planes.  Does
anyone have an example?

Mike Lamson

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<TITLE>IBIS Package Model with Multiple Ground Planes and Redundant =
Ports</TITLE>
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<BODY>

<P><FONT SIZE=3D2 FACE=3D"Arial">How can an IBIS package model be =
constructed with multiple ground planes that have the same input ports =
at the chip and the same output ports at the package ball?&nbsp; That =
is, there are two current paths starting at the same chip bump and =
going to the same package ball but on different planes.&nbsp; Does =
anyone have an example?</FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Mike Lamson</FONT>
</P>
<BR>

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------------------------------

Date: Mon, 11 Nov 2002 15:07:17 -0800
From: "Angulo, John" <[email-masked]>
Subject: RE: [IBIS-Users] C_comp issue?

This is a subtle issue, and you're right Todd.  In an actual device, driver behavior obviously depends on capacitance characteristics.  If you raise the overall capacitance, you might decrease the slew rate, and the IBIS model would record both a higher C_comp and slower waveforms in its V-T tables.  But the simulation tool must always obey the slew rate information in the [Rising Waveform]/[Falling Waveform] or the [Ramp] keywords, whatever the value of C_comp.  A good simulator will always produce waveforms that match the V-T tables when you attach the resistive loads documented in those tables, and must assume that whatever C_comp value the model provides is consistent with those V-T data.  When you change the C_comp value in the IBIS model, the reflection behavior will certainly change, but you must also provide updated V-T information to give the model a new slew rate.

John Angulo
Hyperlynx Products
Mentor Graphics Corp.
[email-masked]
425-869-2320
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------------------------------

Date: Mon, 11 Nov 2002 15:46:03 -0800
From: "Muranyi, Arpad" <[email-masked]>
Subject: RE: [IBIS-Users] C_comp issue?

Todd,

Your description is absolutely correct, and Stephen Peters and Bill Panos
are only partially correct.  Thank you for the excruciating and unambiguous
details in your description.

All,

To reiterate what Todd said, C_comp is the capacitance you see when you look
into the die.  Package is not included.  The waveforms in the model (Vt curves)
are not effected by C_comp, i.e. the model should reproduce the same waveforms
if simulated using the same R_fixture and V_fixture combinations that are
in the Vt curves REGARDLESS of what C_comp is.

Waveforms will only change due to C_comp if the signal comes from the outside
world, either due to reflections while the driver is driving, or when it is
in the receiver mode.

If a particular tool does not give these results it is time to talk to the
tool vendor.  Most tools I know of do it this way.

Arpad Muranyi
Intel Corporation
===========================================================================

- -----Original Message-----
From: Todd Westerhoff [mailto:[email-masked]]
Sent: Monday, November 11, 2002 1:34 PM
To: [email-masked]
Subject: RE: [IBIS-Users] C_comp issue?

There are a few points here worth mentioning - if only to verify that I
understand how this stuff is *supposed* to work.

If you vary the C_comp value of the *receiver* on a net - then yes, I expect
to see the waveforms change, as you're effectively changing the loading the
receiver places on the net.

However, if you vary the value of C_comp for the *driving* device, then the
fact that you've changed C_comp will *only* affect any reflections on the
net that get back to the driver.  In other words, changing the driving
device's C_comp value does *NOT* affect its actual behavior as a driver;
only its behavior as a load is affected.  This is true whether the driver is
acting as a receiver (i.e. an I/O in the "input" state), or whether the
driver is absorbing reflections (i.e. the driver is "quiet" because it has
stopped sweeping the V-T curve).

... all of which is a long-winded way of saying that IBIS simulators place
C_comp in parallel with the driver's output and then compensate its presence
out; thereby reproducing the V-T behavior from the IBIS model.  So, changing
the value of C_comp doesn't actually change the output's *driving* behavior.

Am I understanding this correctly, or have I gotten myself confused again?

Todd ;-}

Todd Westerhoff
Signal Integrity Engineer
Cisco Systems
250 Apollo Drive - Chelmsford, MA - 01824
email:[email-masked]
ph: 978-497-0272
============================================

"When did the choices get so hard, with so much more at stake?
 Life gets mighty precious when there's less of it to waste"

- - Bonnie Raitt, "Nick of Time"

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On
Behalf Of Peters, Stephen
Sent: Monday, November 11, 2002 3:47 PM
To: 'Eric Hsu'; [email-masked]
Subject: RE: [IBIS-Users] C_comp issue?

Hello Eric:

  C_comp represents the I/O (input or ouptut) capacitance of the driver or
reciever itself.  It is the capacitace seen when standing on the pad of the
die and looking back into the I/O cell.

  Changing C_comp will effect a number of things, but yes -- C_comp has a
direct effect on a drivers rise or fall time and waveforms.

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: Eric Hsu [mailto:[email-masked]]
Sent: Monday, November 11, 2002 12:00 PM
To: [email-masked]
Cc: [email-masked]
Subject: [IBIS-Users] C_comp issue?

Hi All,

What is the [c_comp] role in ibis? If changing [c_comp] value, will I
get different results in rising/falling waveform?

Best Regards,

- -eric

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------------------------------

Date: Mon, 11 Nov 2002 15:59:43 -0800
From: Fred Balistreri <[email-masked]>
Subject: Re: [IBIS-Users] C_comp issue?

I think that perhaps there is confusion. It is agreed that the
simulators should reproduce the v/t curves no matter what the
c_comp that is specified. What is not agreed is that for the
same model if you have two different c_comps then the v/t curve
will be the same. I think what you mean is that for a given
ibis model the v/t curves contain the c_comp. In other words
what ever c_comp is given in the ibis model, that is what
produced the v/t curve.
 
Given that you have the same transistor level model,
then changing the capacitance in the
original netlist will give you a different v/t curve and
a different c_comp and therefore a different IBIS model.   

What it sounds that you are suggesting is that no matter what  
the physical capacitance is, that the waveform does not change. 
That surely is not true.

Best regards,

"Muranyi, Arpad" wrote:
> 
> Todd,
> 
> Your description is absolutely correct, and Stephen Peters and Bill Panos
> are only partially correct.  Thank you for the excruciating and unambiguous
> details in your description.
> 
> All,
> 
> To reiterate what Todd said, C_comp is the capacitance you see when you look
> into the die.  Package is not included.  The waveforms in the model (Vt curves)
> are not effected by C_comp, i.e. the model should reproduce the same waveforms
> if simulated using the same R_fixture and V_fixture combinations that are
> in the Vt curves REGARDLESS of what C_comp is.
> 
> Waveforms will only change due to C_comp if the signal comes from the outside
> world, either due to reflections while the driver is driving, or when it is
> in the receiver mode.
> 
> If a particular tool does not give these results it is time to talk to the
> tool vendor.  Most tools I know of do it this way.
> 
> Arpad Muranyi
> Intel Corporation
> ===========================================================================
> 
> -----Original Message-----
> From: Todd Westerhoff [mailto:[email-masked]]
> Sent: Monday, November 11, 2002 1:34 PM
> To: [email-masked]
> Subject: RE: [IBIS-Users] C_comp issue?
> 
> There are a few points here worth mentioning - if only to verify that I
> understand how this stuff is *supposed* to work.
> 
> If you vary the C_comp value of the *receiver* on a net - then yes, I expect
> to see the waveforms change, as you're effectively changing the loading the
> receiver places on the net.
> 
> However, if you vary the value of C_comp for the *driving* device, then the
> fact that you've changed C_comp will *only* affect any reflections on the
> net that get back to the driver.  In other words, changing the driving
> device's C_comp value does *NOT* affect its actual behavior as a driver;
> only its behavior as a load is affected.  This is true whether the driver is
> acting as a receiver (i.e. an I/O in the "input" state), or whether the
> driver is absorbing reflections (i.e. the driver is "quiet" because it has
> stopped sweeping the V-T curve).
> 
> ... all of which is a long-winded way of saying that IBIS simulators place
> C_comp in parallel with the driver's output and then compensate its presence
> out; thereby reproducing the V-T behavior from the IBIS model.  So, changing
> the value of C_comp doesn't actually change the output's *driving* behavior.
> 
> Am I understanding this correctly, or have I gotten myself confused again?
> 
> Todd ;-}
> 
> Todd Westerhoff
> Signal Integrity Engineer
> Cisco Systems
> 250 Apollo Drive - Chelmsford, MA - 01824
> email:[email-masked]
> ph: 978-497-0272
> ============================================
> 
> "When did the choices get so hard, with so much more at stake?
>  Life gets mighty precious when there's less of it to waste"
> 
> - Bonnie Raitt, "Nick of Time"
> 
> -----Original Message-----
> From: [email-masked] [mailto:[email-masked]]On
> Behalf Of Peters, Stephen
> Sent: Monday, November 11, 2002 3:47 PM
> To: 'Eric Hsu'; [email-masked]
> Subject: RE: [IBIS-Users] C_comp issue?
> 
> Hello Eric:
> 
>   C_comp represents the I/O (input or ouptut) capacitance of the driver or
> reciever itself.  It is the capacitace seen when standing on the pad of the
> die and looking back into the I/O cell.
> 
>   Changing C_comp will effect a number of things, but yes -- C_comp has a
> direct effect on a drivers rise or fall time and waveforms.
> 
>   Regards,
>   Stephen Peters
>   Intel Corp.
> 
> -----Original Message-----
> From: Eric Hsu [mailto:[email-masked]]
> Sent: Monday, November 11, 2002 12:00 PM
> To: [email-masked]
> Cc: [email-masked]
> Subject: [IBIS-Users] C_comp issue?
> 
> Hi All,
> 
> What is the [c_comp] role in ibis? If changing [c_comp] value, will I
> get different results in rising/falling waveform?
> 
> Best Regards,
> 
> -eric
> 
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- -- 
Fred Balistreri
[email-masked]

http://www.apsimtech.com
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------------------------------

Date: Mon, 11 Nov 2002 16:45:24 -0800
From: "Muranyi, Arpad" <[email-masked]>
Subject: RE: [IBIS-Users] C_comp issue?

Fred,

I think you are correct.  What we often forget in these
discussions is to define our frame of reference.  So we end
up talking about something and someone else reading the same
words may still misunderstand it because they see it from a
different point of view.

To reiterate then, I agree, that if I keep everything the same
in a transistor level model and change only the amount of
capacitance in it, for example, by tweaking the capacitance
parameters in the process file (Cj and the like), than that
model will give different waveforms, or Vt curves.

I think we also agree that when we simulate with a particular
IBIS model, then no matter what the C_comp parameter says, the
output should reproduce the same waveforms when the model is
driving and no reflections are present.

In case anyone wonders, this difference is by design, and not
because IBIS is inferior or incapable to reproduce the real
world.  This is why:

When we obtain a waveform from a transistor model, the shape of
that waveform includes the capacitive effects.  In IBIS simulators
this waveform is basically used as if it was a scaling coefficient
as a function of time to scale the size of the IV curve to make that
also vary as a function of time (to account for the transients).
(Remember the IV curve by itself is purely steady state and contains
no transient information).

IV curves are usually implemented as some sort of a current source.
Whether they are scaled with respect to time or not, they are a pure
current source, not including any capacitive parasitics.  So if we
want the driver or receiver to exhibit any capacitance, we need to
have a capacitor in parallel with this current source.  But if we
did that, then the shape of the Vt curve would also get slowed down,
which we don't want, because that would "double count" the effects
of the capacitance.  So IBIS simulators usually have a compensation
algorithm to avoid this double counting, yet preserving the capacitance
so that it is still visible to the signals coming from the outside world.

I hope this helps clarifying anyone's doubts.

Arpad Muranyi
Intel Corporation
======================================================================

- -----Original Message-----
From: Fred Balistreri [mailto:[email-masked]]
Sent: Monday, November 11, 2002 4:00 PM
To: Muranyi, Arpad
Cc: [email-masked]
Subject: Re: [IBIS-Users] C_comp issue?

I think that perhaps there is confusion. It is agreed that the
simulators should reproduce the v/t curves no matter what the
c_comp that is specified. What is not agreed is that for the
same model if you have two different c_comps then the v/t curve
will be the same. I think what you mean is that for a given
ibis model the v/t curves contain the c_comp. In other words
what ever c_comp is given in the ibis model, that is what
produced the v/t curve.
 
Given that you have the same transistor level model,
then changing the capacitance in the
original netlist will give you a different v/t curve and
a different c_comp and therefore a different IBIS model.   

What it sounds that you are suggesting is that no matter what  
the physical capacitance is, that the waveform does not change. 
That surely is not true.

Best regards,

"Muranyi, Arpad" wrote:
> 
> Todd,
> 
> Your description is absolutely correct, and Stephen Peters and Bill Panos
> are only partially correct.  Thank you for the excruciating and unambiguous
> details in your description.
> 
> All,
> 
> To reiterate what Todd said, C_comp is the capacitance you see when you look
> into the die.  Package is not included.  The waveforms in the model (Vt curves)
> are not effected by C_comp, i.e. the model should reproduce the same waveforms
> if simulated using the same R_fixture and V_fixture combinations that are
> in the Vt curves REGARDLESS of what C_comp is.
> 
> Waveforms will only change due to C_comp if the signal comes from the outside
> world, either due to reflections while the driver is driving, or when it is
> in the receiver mode.
> 
> If a particular tool does not give these results it is time to talk to the
> tool vendor.  Most tools I know of do it this way.
> 
> Arpad Muranyi
> Intel Corporation
> ===========================================================================
> 
> -----Original Message-----
> From: Todd Westerhoff [mailto:[email-masked]]
> Sent: Monday, November 11, 2002 1:34 PM
> To: [email-masked]
> Subject: RE: [IBIS-Users] C_comp issue?
> 
> There are a few points here worth mentioning - if only to verify that I
> understand how this stuff is *supposed* to work.
> 
> If you vary the C_comp value of the *receiver* on a net - then yes, I expect
> to see the waveforms change, as you're effectively changing the loading the
> receiver places on the net.
> 
> However, if you vary the value of C_comp for the *driving* device, then the
> fact that you've changed C_comp will *only* affect any reflections on the
> net that get back to the driver.  In other words, changing the driving
> device's C_comp value does *NOT* affect its actual behavior as a driver;
> only its behavior as a load is affected.  This is true whether the driver is
> acting as a receiver (i.e. an I/O in the "input" state), or whether the
> driver is absorbing reflections (i.e. the driver is "quiet" because it has
> stopped sweeping the V-T curve).
> 
> ... all of which is a long-winded way of saying that IBIS simulators place
> C_comp in parallel with the driver's output and then compensate its presence
> out; thereby reproducing the V-T behavior from the IBIS model.  So, changing
> the value of C_comp doesn't actually change the output's *driving* behavior.
> 
> Am I understanding this correctly, or have I gotten myself confused again?
> 
> Todd ;-}
> 
> Todd Westerhoff
> Signal Integrity Engineer
> Cisco Systems
> 250 Apollo Drive - Chelmsford, MA - 01824
> email:[email-masked]
> ph: 978-497-0272
> ============================================
> 
> "When did the choices get so hard, with so much more at stake?
>  Life gets mighty precious when there's less of it to waste"
> 
> - Bonnie Raitt, "Nick of Time"
> 
> -----Original Message-----
> From: [email-masked] [mailto:[email-masked]]On
> Behalf Of Peters, Stephen
> Sent: Monday, November 11, 2002 3:47 PM
> To: 'Eric Hsu'; [email-masked]
> Subject: RE: [IBIS-Users] C_comp issue?
> 
> Hello Eric:
> 
>   C_comp represents the I/O (input or ouptut) capacitance of the driver or
> reciever itself.  It is the capacitace seen when standing on the pad of the
> die and looking back into the I/O cell.
> 
>   Changing C_comp will effect a number of things, but yes -- C_comp has a
> direct effect on a drivers rise or fall time and waveforms.
> 
>   Regards,
>   Stephen Peters
>   Intel Corp.
> 
> -----Original Message-----
> From: Eric Hsu [mailto:[email-masked]]
> Sent: Monday, November 11, 2002 12:00 PM
> To: [email-masked]
> Cc: [email-masked]
> Subject: [IBIS-Users] C_comp issue?
> 
> Hi All,
> 
> What is the [c_comp] role in ibis? If changing [c_comp] value, will I
> get different results in rising/falling waveform?
> 
> Best Regards,
> 
> -eric
> 
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- -- 
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[email-masked]

http://www.apsimtech.com
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------------------------------

Date: Mon, 11 Nov 2002 19:55:43 -0500
From: "Todd Westerhoff" <[email-masked]>
Subject: RE: [IBIS-Users] C_comp issue?

Well, you know what they say ...

... God is in the excruciating details!

Todd ;-}

Todd Westerhoff
Signal Integrity Engineer
Cisco Systems
250 Apollo Drive - Chelmsford, MA - 01824
email:[email-masked]
ph: 978-497-0272
============================================

"When did the choices get so hard, with so much more at stake?
 Life gets mighty precious when there's less of it to waste"

- - Bonnie Raitt, "Nick of Time"

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On
Behalf Of Muranyi, Arpad
Sent: Monday, November 11, 2002 6:46 PM
To: [email-masked]
Subject: RE: [IBIS-Users] C_comp issue?

Todd,

Your description is absolutely correct, and Stephen Peters and Bill Panos
are only partially correct.  Thank you for the excruciating and unambiguous
details in your description.

All,

To reiterate what Todd said, C_comp is the capacitance you see when you look
into the die.  Package is not included.  The waveforms in the model (Vt
curves)
are not effected by C_comp, i.e. the model should reproduce the same
waveforms
if simulated using the same R_fixture and V_fixture combinations that are
in the Vt curves REGARDLESS of what C_comp is.

Waveforms will only change due to C_comp if the signal comes from the
outside
world, either due to reflections while the driver is driving, or when it is
in the receiver mode.

If a particular tool does not give these results it is time to talk to the
tool vendor.  Most tools I know of do it this way.

Arpad Muranyi
Intel Corporation
===========================================================================

- -----Original Message-----
From: Todd Westerhoff [mailto:[email-masked]]
Sent: Monday, November 11, 2002 1:34 PM
To: [email-masked]
Subject: RE: [IBIS-Users] C_comp issue?

There are a few points here worth mentioning - if only to verify that I
understand how this stuff is *supposed* to work.

If you vary the C_comp value of the *receiver* on a net - then yes, I expect
to see the waveforms change, as you're effectively changing the loading the
receiver places on the net.

However, if you vary the value of C_comp for the *driving* device, then the
fact that you've changed C_comp will *only* affect any reflections on the
net that get back to the driver.  In other words, changing the driving
device's C_comp value does *NOT* affect its actual behavior as a driver;
only its behavior as a load is affected.  This is true whether the driver is
acting as a receiver (i.e. an I/O in the "input" state), or whether the
driver is absorbing reflections (i.e. the driver is "quiet" because it has
stopped sweeping the V-T curve).

... all of which is a long-winded way of saying that IBIS simulators place
C_comp in parallel with the driver's output and then compensate its presence
out; thereby reproducing the V-T behavior from the IBIS model.  So, changing
the value of C_comp doesn't actually change the output's *driving* behavior.

Am I understanding this correctly, or have I gotten myself confused again?

Todd ;-}

Todd Westerhoff
Signal Integrity Engineer
Cisco Systems
250 Apollo Drive - Chelmsford, MA - 01824
email:[email-masked]
ph: 978-497-0272
============================================

"When did the choices get so hard, with so much more at stake?
 Life gets mighty precious when there's less of it to waste"

- - Bonnie Raitt, "Nick of Time"

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On
Behalf Of Peters, Stephen
Sent: Monday, November 11, 2002 3:47 PM
To: 'Eric Hsu'; [email-masked]
Subject: RE: [IBIS-Users] C_comp issue?

Hello Eric:

  C_comp represents the I/O (input or ouptut) capacitance of the driver or
reciever itself.  It is the capacitace seen when standing on the pad of the
die and looking back into the I/O cell.

  Changing C_comp will effect a number of things, but yes -- C_comp has a
direct effect on a drivers rise or fall time and waveforms.

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: Eric Hsu [mailto:[email-masked]]
Sent: Monday, November 11, 2002 12:00 PM
To: [email-masked]
Cc: [email-masked]
Subject: [IBIS-Users] C_comp issue?

Hi All,

What is the [c_comp] role in ibis? If changing [c_comp] value, will I
get different results in rising/falling waveform?

Best Regards,

- -eric

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------------------------------

End of ibis-users V1 #11
************************