Subject: ibis-users V1 #13
From: owner-ibis-users@ (ibis-users)
To: [email-masked]

ibis-users         Thursday, December 19 2002         Volume 01 : Number 013

----------------------------------------------------------------------

Date: Wed, 20 Nov 2002 21:06:17 -0800 (PST)
From: whiz kid <[email-masked]>
Subject: [IBIS-Users] Information about IBIS Warnings .

Hi Gurus,
I have few questions about what the warnings mean. I
am using Specctraquest for my simulations.

1) PullDown : Overall Typical Area exceeds Maximun
Area. What has area goto do ????
2) Duplicate Points removed. This may sound dumb but
why will the curves have duplicate points in the first
place.
3) TV curves should asymptotically approach a final
value- Point added. what does asymptotically mean.

4) Falling wave form Fall1 Non monotic dv=-- at time
dt=-- exceeds 1% of voltage span. Do we need to worry
that the calculated value is off compared to the VI
curves . How is the best way to fix the above warning.

5) Also, I have a open drain IBIS model with a built
in Pull up resistor modelled into it. Is there a way
to create a new model with out the pull up so I can
play with different values of the Pullup in my
simulation. How do I go about creating this new model.

Any suggestions are welcome.

Thanks,
Rahul.

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------------------------------

Date: Thu, 21 Nov 2002 13:20:11 +0100
From: "Henrik G. Madsen" <[email-masked]>
Subject: [IBIS-Users] Modelling an open drain driver

Hey

I'm trying to make an IBIS model (from SPICE) for an open drain driver.

The driver is powered from 2.5V and the Vpullup is either 2.5V or 3.3V.

I have tried to sketch the end user application below
                                                              
                        ___Vpullup                            
                        |                                     
                        |                                     
                        /                                     
                        \ Rpullup                __________   
         OD driver      /                       |          |  
                        \     ____________      |          |  
              ______.___|____|   60 ohm   |_____| Receiver |  
             |               |____________|     |          |  
            _|                                  |          |  
          -|_                                   |__________|  
             |                                                
             |                                                
             |__ VSS                                          
                                                              
                    |
      -----Driver---|-----------normal use circuit--------------
 
I'm in doubt how to write the S2IBIS setup file (.s2i) for an OD driver.
I know that I should use the 'Open_sink' modeltype, but how should I define the rising and falling waveforms. 
I would assume that R_fixture = 60 ohm and V_fixture = 0V

Moreover I imagine that I should only do the falling waveform and not the rising, which would be controlled by the external pullup resistor.

_____________________________________
Henrik G Madsen
Sr. HW Engineer 
Vitesse Semiconductor Corporation A/S
Ethernet Products Division
Hoerkaer 16,  DK-2730 Herlev, DENMARK
Direct: +45 4485 5920
Phone: +45 4485 5900, Fax: +45 4485 5901
mail: [email-masked]
web: http://www.vitesse.com
_____________________________________

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------------------------------

Date: Thu, 21 Nov 2002 13:30:23 +0100
From: "Henrik G. Madsen" <[email-masked]>
Subject: [IBIS-Users] FW: Modelling an open drain driver

Sorry, I managed to send the mail before I had finished the question

/Henrik

- -----Original Message-----
From: Henrik G. Madsen 
Sent: 21. november 2002 13:20
To: [email-masked]
Subject: Modelling an open drain driver

Hey

I'm trying to make an IBIS model (from SPICE) for an open drain driver.

The driver is powered from 2.5V and the Vpullup is either 2.5V or 3.3V.

I have tried to sketch the end user application below
                                                              
                        ___Vpullup                            
                        |                                     
                        |                                     
                        /                                     
                        \ Rpullup                __________   
         OD driver      /                       |          |  
                        \     ____________      |          |  
              ______.___|____|   60 ohm   |_____| Receiver |  
             |               |____________|     |          |  
            _|                                  |          |  
          -|_                                   |__________|  
             |                                                
             |                                                
             |__ VSS                                          
                                                              
                    |
      -----Driver---|-----------normal use circuit--------------

1) 
I'm in doubt how to write the S2IBIS setup file (.s2i) for an OD driver.
I know that I should use the 'Open_sink' modeltype, but how should I define the rising and falling waveforms. 
I would assume that R_fixture = 60 ohm and V_fixture = Vpullup

Moreover I imagine that I should only do the falling waveform and not the rising, which would be controlled by the external pullup resistor.

2)
Additionally it is possible to include both cases in the same model, i.e. Vpullup equals either 2.5V or 3.3V

and would a simulator be able to select the right waveforms to use?

_____________________________________
Henrik G Madsen
Sr. HW Engineer 
Vitesse Semiconductor Corporation A/S
Ethernet Products Division
Hoerkaer 16,  DK-2730 Herlev, DENMARK
Direct: +45 4485 5920
Phone: +45 4485 5900, Fax: +45 4485 5901
mail: [email-masked]
web: http://www.vitesse.com
_____________________________________

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------------------------------

Date: Thu, 21 Nov 2002 10:47:23 -0500
From: "Ingraham, Andrew" <[email-masked]>
Subject: RE: [IBIS-Users] Information about IBIS Warnings .

> I have few questions about what the warnings mean. I
> am using Specctraquest for my simulations.
> 
> 1) PullDown : Overall Typical Area exceeds Maximun
> Area. What has area goto do ????
 
If it is talking about transistor area, then it must be coming from a
non-IBIS model in your simulation.

But perhaps it is checking the areas under the curves in the IBIS model.
Generally speaking, I(V) ought to be bigger in the Max column than the
Typ column.  But exceptions may exist at certain points or ranges (since
Vcc also changes, etc.).  So Specctraquest may be comparing the areas
under the I(V) curves to make sure the Max data is indeed "stronger"
than the Typ data, and it sees that it isn't.  That's my guess, but it's
only a rough guess.

> 2) Duplicate Points removed. This may sound dumb but
> why will the curves have duplicate points in the first
> place.
 
Round-off?  (Closely-spaced points became the same.)

Or, if two or more tables were combined, resulting in overlap.

> 3) TV curves should asymptotically approach a final
> value- Point added. what does asymptotically mean.
 
Asymptotically means the curve should continually approach the final
value = its asymptote.  This is not a precise definition.  It means that
the curve would eventually reach the final value if you could look out
along the curve toward infinite time.  Technically it approaches but
never quite reaches it, in finite time.

Asymptotically often also implies that the difference between the curve
and its asymptote always gets smaller as you move farther out (i.e., the
polarity of the slope does not change).

> 4) Falling wave form Fall1 Non monotic dv=-- at time
> dt=-- exceeds 1% of voltage span. Do we need to worry
> that the calculated value is off compared to the VI
> curves . How is the best way to fix the above warning.
 
Yes; if I understand correctly, this warning message (or its earlier
version which was slightly different) has come up often in discussion
groups.

The V-T waveforms and I-V curves should be consistent with one another.
If the V-T waveform begins, or ends, at a value that is not consistent
with the I-V tables, then something is wrong, and "all bets are off."
In other words, what comes out of the simulator may be garbage, because
it is trying to satisfy both requirements simultaneously, which it
can't.

It means there is something wrong with the IBIS model, and should be
fixed.

> 5) Also, I have a open drain IBIS model with a built
> in Pull up resistor modelled into it. Is there a way
> to create a new model with out the pull up so I can
> play with different values of the Pullup in my
> simulation. How do I go about creating this new model.
 
The pull-up resistor's effects are probably in the Clamp curves.

If you know the typ/min/max resistor values that were used when the
model was created, you could try calculating the resistor current vs.
voltage, and subtract it from the tables.  Then add your own pull-up
resistor currents.

But this assumes the pull-up resistor was linear ... i.e., a real
resistor and not a pull-up FET which is how many ICs today implement
on-die pull-ups.

If you assume that nearly all of the current in the Clamp tables,
between GND and VCC, was due to the pull-up resistor, then you might try
zero'ing the current in the [GND Clamp] table for positive voltages.
But this is kludgy and not very accurate.

I wouldn't know how to modify the V-T waveforms, so maybe it's better to
just remove them from the model and rely on [Ramp] data instead.  But
the old [Ramp] data (especially dv/dt_r) probably isn't right either!

It is probably better to go to the source of the IBIS models and have
new models created.

Regards,
Andy

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------------------------------

Date: Thu, 21 Nov 2002 11:16:44 -0500
From: "Ingraham, Andrew" <[email-masked]>
Subject: RE: [IBIS-Users] FW: Modelling an open drain driver

> 1) 
> I'm in doubt how to write the S2IBIS setup file (.s2i) for an OD
> driver.
> I know that I should use the 'Open_sink' modeltype, but how should I
> define the rising and falling waveforms. 
> I would assume that R_fixture = 60 ohm and V_fixture = Vpullup
 
For R_fixture, using 60 ohms in parallel with Rpullup, would come closer
to the actual circuit.  Unless you intended for Rpullup to be on the far
(receiver) end of the 60 ohm trace.

> Moreover I imagine that I should only do the falling waveform and not
> the rising, which would be controlled by the external pullup resistor.
 
No; I think you should have both rising and falling waveforms.  While
the external circuit dominates the rising edge, it doesn't control it
100%.  Driver capacitance affects it.  If the driver transistors turn
off slowly, they may affect it too.

As a user, I would definitely want to simulate rising edges, so I'd want
the IBIS model to be accurate.  Include rising waveforms.

> 2)
> Additionally it is possible to include both cases in the same model,
> i.e. Vpullup equals either 2.5V or 3.3V
 
Yes.  IBIS models let you include up to 100 waveform tables per model.

> and would a simulator be able to select the right waveforms to use?
 
It has the means to, but this depends on the simulator.  Some have
limitations.  (HSpice, for example, can use at most two waveform
tables.)

Regards,
Andy

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------------------------------

Date: Thu, 21 Nov 2002 11:54:05 -0500
From: "Ingraham, Andrew" <[email-masked]>
Subject: RE: [IBIS-Users] FW: Modelling an open drain driver

I wrote:

> For R_fixture, using 60 ohms in parallel with Rpullup, would come
> closer
> to the actual circuit.  Unless you intended for Rpullup to be on the
> far
> (receiver) end of the 60 ohm trace.
 
I forgot to say ... you should have a waveform with V_fixture = 0V and
another with V_fixture = Vpullup.

Andy

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------------------------------

Date: Thu, 21 Nov 2002 14:45:10 -0500
From: "Lynne Green" <[email-masked]>
Subject: re: RE: [IBIS-Users] Information about IBIS Warnings .

re: questions on SPECCTRAQuest warnings.

1) SPECCTRAQuest checks area under the curves.  The warning tells you
that you should
visually check the curves to verify the V-t columns are in the correct
typ/min/max order.
Note that V-t curves can be viewed in Model Integrity, released in
SPECCTRAQuest 14.2.

4) The "hump" in the V-t curve probably exceeded 1%.  The warning just
tells you that you
should visually check the V-t curves.  This is probably not an
indication of an error in the
model.  This is not related to any I-V mismatch problems.

5) To model a _change_ in pullup resistance, _IF_ the change is
resistance is "small", you
can try adding or subtracting the current delta_I caused by the change
in resistance.  This
has the advantage of preserving some of the non-linearity of a pullup
resistance implemented
as a MOSFET.
delta_I = -delta_R * V / (R*R)
delta_I = -delta_R * I / R
delta_I = -delta_R * I * I / V

Note that this does NOT apply to DETECTING resistor terminators.  For
further information on
detecting these, see Arpad's "JEDEC" presentation at
http://www.eda.org/pub/ibis/training/.

Best regards,
Lynne

Dr. Lynne Green
Senior Member of Consulting Staff
Cadence Design Systems, Inc.

"All the world's an analog stage, whereon digital plays bit parts."
Fred Field , Hughes Aircraft

- -----------------------------------------------------

- -----Original Message-----
From: Ingraham, Andrew [mailto:[email-masked]] 
Sent: Thursday, November 21, 2002 7:47 AM
To: whiz kid
Cc: [email-masked]
Subject: RE: [IBIS-Users] Information about IBIS Warnings .

> I have few questions about what the warnings mean. I
> am using Specctraquest for my simulations.
> 
> 1) PullDown : Overall Typical Area exceeds Maximun
> Area. What has area goto do ????
 
If it is talking about transistor area, then it must be coming from a
non-IBIS model in your simulation.

But perhaps it is checking the areas under the curves in the IBIS model.
Generally speaking, I(V) ought to be bigger in the Max column than the
Typ column.  But exceptions may exist at certain points or ranges (since
Vcc also changes, etc.).  So Specctraquest may be comparing the areas
under the I(V) curves to make sure the Max data is indeed "stronger"
than the Typ data, and it sees that it isn't.  That's my guess, but it's
only a rough guess.

> 2) Duplicate Points removed. This may sound dumb but
> why will the curves have duplicate points in the first
> place.
 
Round-off?  (Closely-spaced points became the same.)

Or, if two or more tables were combined, resulting in overlap.

> 3) TV curves should asymptotically approach a final
> value- Point added. what does asymptotically mean.
 
Asymptotically means the curve should continually approach the final
value = its asymptote.  This is not a precise definition.  It means that
the curve would eventually reach the final value if you could look out
along the curve toward infinite time.  Technically it approaches but
never quite reaches it, in finite time.

Asymptotically often also implies that the difference between the curve
and its asymptote always gets smaller as you move farther out (i.e., the
polarity of the slope does not change).

> 4) Falling wave form Fall1 Non monotic dv=-- at time
> dt=-- exceeds 1% of voltage span. Do we need to worry
> that the calculated value is off compared to the VI
> curves . How is the best way to fix the above warning.
 
Yes; if I understand correctly, this warning message (or its earlier
version which was slightly different) has come up often in discussion
groups.

The V-T waveforms and I-V curves should be consistent with one another.
If the V-T waveform begins, or ends, at a value that is not consistent
with the I-V tables, then something is wrong, and "all bets are off." In
other words, what comes out of the simulator may be garbage, because it
is trying to satisfy both requirements simultaneously, which it can't.

It means there is something wrong with the IBIS model, and should be
fixed.

> 5) Also, I have a open drain IBIS model with a built
> in Pull up resistor modelled into it. Is there a way
> to create a new model with out the pull up so I can
> play with different values of the Pullup in my
> simulation. How do I go about creating this new model.
 
The pull-up resistor's effects are probably in the Clamp curves.

If you know the typ/min/max resistor values that were used when the
model was created, you could try calculating the resistor current vs.
voltage, and subtract it from the tables.  Then add your own pull-up
resistor currents.

But this assumes the pull-up resistor was linear ... i.e., a real
resistor and not a pull-up FET which is how many ICs today implement
on-die pull-ups.

If you assume that nearly all of the current in the Clamp tables,
between GND and VCC, was due to the pull-up resistor, then you might try
zero'ing the current in the [GND Clamp] table for positive voltages. But
this is kludgy and not very accurate.

I wouldn't know how to modify the V-T waveforms, so maybe it's better to
just remove them from the model and rely on [Ramp] data instead.  But
the old [Ramp] data (especially dv/dt_r) probably isn't right either!

It is probably better to go to the source of the IBIS models and have
new models created.

Regards,
Andy

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------------------------------

Date: Thu, 21 Nov 2002 14:45:06 -0800
From: "Ross, Bob" <[email-masked]>
Subject: Re: [IBIS-Users] Questions about Bus Hold (2nd try)

Rob:

I am going to try to address your questions directly based
on what I have seen in some Philips models and Philips modeling
processes.

Ironically, the primary reason for bus_hold was to document a
receiver triggered switching circuit to give extra strength at
the receiver from a weak driver.  This circuit performed just
like a bus hold circuit, but with much stronger currents.  Because
it was a similar effect as bus hold, it was named bus hold.

As a general rule, for most modeling situations, the true
bus hold effect can and should be ignored.  What commonly
occurs in s2ibis typ extractions is that the [Gnd Clamp]
table is non-monotonic in the 0 to Vcc region, with a
negative and then positive glitch around approximately
Vcc/2 - corresponding to a bus hold circuit switching
during the DC sweep.  However, this current is negligable
with respect to overall signal integrity and timing
considerations and can be ignored.  Most tools have 
loads on the net (including the characteristic impedance
of the traces) that swamp out the non-monotonic effect
during switching, so it is no factor.  Other tools may
smooth out the glitch.

My responses are in your text.

Bob Ross
Mentor Graphics

[email-masked] wrote:
> 
> Hello Ibis collegues,
> 
> I want to make accurate IBIS models for input buffers and I/O buffers with bus hold.
> Existing models, I have seen on the web, show the bus hold characteristic in the ground clamp curve.
> When running the IBIS checker, this causes non-monotonic warnings.
> Therefore I am not sure whether this way of modeling is correct.

My recommendation is to simply zero out the clamp currents and remove
the glitch - for the purpose of correct simulation and removal of
warning messages (versus exact characterization).  If needed, put in
the full bus hold submodel statements.

> 
> This brings me to the following questions:
> 
> 1. If the bus hold characteristic is present in the ground clamp curve, how would you qualify this:

> 1a Wrong, since it causes non-monotonic warnings

It is correct as far as a DC sweep and approximation effect is 
concerned.  However, see 1b, 1c

> 1b. Useless

Probably not needed for most situations.  A 75 uA current is
negligable compared to mA level switching current flows, and
it is zero at the end-points anyway where circuits tend to
settle.

> 1c. Okay, since it represents the actual behavior.

It mimics actual behavior through only a DC sweep mechanism.
However since the mechanism is dynamic (e.g., a flip flop),
the DC characterization is not correct.  So the correct
approach is to zero out the currents.  If you really want
it, use the true submodel characterization based on switching.
See 1a :-)

> 1d. Other ....

True Bus Hold submodel.  Plus 1b for many real situations.

> 
> 2. The IBIS standard describes the Bus Hold Submodel.
> I assume the Top Model describes the buffer without bus hold characteristic.
> From the IBIS standard I cannot understand what part of the circuit I must simulate in order to gather the data for the Bus Hold Submodel, namely the pullup, pulldown and last but not least the ramp figures.

The bus hold requires internal knowledge for construction.  Basically
the strength of the bus hold pullup and pulldown "resistors" are needed,
and the speed of transition is needed, and the approximate switching
thresholds are needed.  I recommend just a very simple model with ramps
since the effect is already on top of more dominant effects.  So the
bus hold serves as a first order adjustment.  When a real internal
switch is characterized with mA level strength, then more detail is
needed.  However, the Semiconductor manufacturer modeler should have
access to the necessary details including the bus hold circuit itself.

> 
> Of course those who have designed the IBIS standard must know the idea behind the Submodel.
> Therefore I would appreciate it very much if somebody could tell me:
> 2.1 Which part of the circuit is described by the sub model?

Just the bus hold switch mechanisms.

> 2.2 How can I get more information about this subject?

Let me know if you have further questions.

> 
> Thank you in anticipation for your reactions.
> 
> Kind regards,
> 
> Rob
>
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------------------------------

Date: Thu, 21 Nov 2002 16:43:28 -0800
From: Shee Kian Wong <[email-masked]>
Subject: [IBIS-Users] IBIS Questions

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C291C0.2C8112C0
Content-Type: text/plain

Hi all,

I have several IBIS questions:
 
1.	I was wondering how an IBIS simulator read and interpret the data
tabulated in an IBIS file? What is the common algorithm used by most of the
	simulators? For example a simple driver and receiver interconnected
by a transmission line. Then how do the data in pullup/pulldown/clamp/ramp
play their roles in forming the simulation waveform? Can one 	tell what
data constitute to a particular portion of the waveform?    

2.	Lumped RLC package is often used in IBIS models. Can they be used in
higher frequency environment? Will parasitics in an IBIS file
(c_comp,C_pkg,C_pin,L_pkg,L_pin) alter the output impedance as
	operating frequency goes higher? Is there a maximum frequency that a
package model can withstand?
	If that is the case, is distributed package model a better choice?
How do we go about it?

Can someone shed some light here?

Have a nice day.
Thks & Rgds,
 
Shee Kian Wong

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<P><FONT SIZE=3D2 FACE=3D"Arial">Hi all,</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">I have several IBIS questions:</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&nbsp;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">1.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; I =
was wondering how an IBIS simulator read and interpret the data =
tabulated in an IBIS file? What is the common algorithm used by most of =
the</FONT></P>

<P>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">simulators? For example a simple driver and receiver =
interconnected by a transmission line. Then how do the data in =
pullup/pulldown/clamp/ramp play their roles in forming the simulation =
waveform? Can one &nbsp;&nbsp;&nbsp; tell what data constitute to a =
particular portion of the waveform?&nbsp;&nbsp;&nbsp; </FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Arial">2.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Lumped RLC package is often used in IBIS models. Can they be used in =
higher frequency environment? Will parasitics in an IBIS file =
(c_comp,C_pkg,C_pin,L_pkg,L_pin) alter the output impedance =
as</FONT></P>

<P>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">operating frequency goes higher? Is there a maximum =
frequency that a package model can withstand?</FONT>
<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; <FONT SIZE=3D2 =
FACE=3D"Arial">If that is the case, is distributed package model a =
better choice? How do we go about it?</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Can someone shed some light =
here?</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Have a nice day.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Thks &amp; Rgds,</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">&nbsp;</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Shee Kian Wong</FONT>
</P>

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------------------------------

Date: Fri, 22 Nov 2002 12:20:18 -0800
From: "Eric Hsu" <[email-masked]>
Subject: [IBIS-Users] IBIS bump question

Hi all,

For a wire-bond package, the RLC of the bondwire is generally considered
to be part of the package.  For a flip-chip package, is there a convention
for how the bump parasitics should be handled?  Is the bump to be
considered part of the package, or part of the die(C_comp)?

Regards,

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------------------------------

Date: Fri, 22 Nov 2002 13:59:09 -0800
From: "Tom Dagostino" <[email-masked]>
Subject: RE: [IBIS-Users] IBIS bump question

I started to say the bump C should be part of the package but in reflection
it seems to be part of the die.  I'd vote for as part of C_comp because it
is part of the metalization on the die.

Tom Dagostino
Device Modeling Division
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 430-1065
[email-masked]
http://www.teraspeed.com

- -----Original Message-----
From: [email-masked]
[mailto:[email-masked]]On Behalf Of Eric Hsu
Sent: Friday, November 22, 2002 12:20 PM
To: [email-masked]
Subject: [IBIS-Users] IBIS bump question

Hi all,

For a wire-bond package, the RLC of the bondwire is generally considered
to be part of the package.  For a flip-chip package, is there a convention
for how the bump parasitics should be handled?  Is the bump to be
considered part of the package, or part of the die(C_comp)?

Regards,

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------------------------------

Date: Fri, 22 Nov 2002 14:29:48 -0800
From: Fred Balistreri <[email-masked]>
Subject: Re: [IBIS-Users] IBIS bump question

It does not matter, so long as it does not get double counted. I believe
the solder bump may appear in the CAD package data base. If so it should
be made part of the package not the IC. 

Best Regards,

Tom Dagostino wrote:
> 
> I started to say the bump C should be part of the package but in reflection
> it seems to be part of the die.  I'd vote for as part of C_comp because it
> is part of the metalization on the die.
> 
> Tom Dagostino
> Device Modeling Division
> Teraspeed Consulting Group LLC
> 2926 SE Yamhill St.
> Portland, OR 97214
> (503) 430-1065
> [email-masked]
> http://www.teraspeed.com
> 
> -----Original Message-----
> From: [email-masked]
> [mailto:[email-masked]]On Behalf Of Eric Hsu
> Sent: Friday, November 22, 2002 12:20 PM
> To: [email-masked]
> Subject: [IBIS-Users] IBIS bump question
> 
> Hi all,
> 
> For a wire-bond package, the RLC of the bondwire is generally considered
> to be part of the package.  For a flip-chip package, is there a convention
> for how the bump parasitics should be handled?  Is the bump to be
> considered part of the package, or part of the die(C_comp)?
> 
> Regards,
> 
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- -- 
Fred Balistreri
[email-masked]

http://www.apsimtech.com
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------------------------------

Date: Fri, 22 Nov 2002 15:07:45 -0800 (PST)
From: Syed Huq <[email-masked]>
Subject: Re: [IBIS-Users] IBIS bump question

A 'bump' is on the die and a RDL(redistribution later)connects the bump to 
the package..

Maybe it should be part of the die instead..

Syed

>Date: Fri, 22 Nov 2002 14:29:48 -0800
>From: Fred Balistreri <[email-masked]>
>X-Accept-Language: en
>MIME-Version: 1.0
>To: [email-masked]
>CC: "'Eric Hsu'" <[email-masked]>, [email-masked]
>Subject: Re: [IBIS-Users] IBIS bump question
>Content-Transfer-Encoding: 7bit
>
>It does not matter, so long as it does not get double counted. I believe
>the solder bump may appear in the CAD package data base. If so it should
>be made part of the package not the IC. 
>
>Best Regards,
>
>Tom Dagostino wrote:
>> 
>> I started to say the bump C should be part of the package but in 
reflection
>> it seems to be part of the die.  I'd vote for as part of C_comp because 
it
>> is part of the metalization on the die.
>> 
>> Tom Dagostino
>> Device Modeling Division
>> Teraspeed Consulting Group LLC
>> 2926 SE Yamhill St.
>> Portland, OR 97214
>> (503) 430-1065
>> [email-masked]
>> http://www.teraspeed.com
>> 
>> -----Original Message-----
>> From: [email-masked]
>> [mailto:[email-masked]]On Behalf Of Eric Hsu
>> Sent: Friday, November 22, 2002 12:20 PM
>> To: [email-masked]
>> Subject: [IBIS-Users] IBIS bump question
>> 
>> Hi all,
>> 
>> For a wire-bond package, the RLC of the bondwire is generally considered
>> to be part of the package.  For a flip-chip package, is there a 
convention
>> for how the bump parasitics should be handled?  Is the bump to be
>> considered part of the package, or part of the die(C_comp)?
>> 
>> Regards,
>> 
>> |------------------------------------------------------------------
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>
>-- 
>Fred Balistreri
>[email-masked]
>
>http://www.apsimtech.com
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------------------------------

Date: Fri, 22 Nov 2002 15:17:50 -0800
From: "Muranyi, Arpad" <[email-masked]>
Subject: RE: [IBIS-Users] IBIS bump question

I don't have any strong preferences where it is modeled, but
for the sake of consistency I would mention that solder balls
are part of the package, not the PCB to which the chip is soldered.
So similarly, I would think that the bumps should be part of the
die and not the package to which it is soldered (welded?).

Arpad Muranyi
Intel Corporation
===================================================================

- -----Original Message-----
From: Syed Huq [mailto:[email-masked]]
Sent: Friday, November 22, 2002 3:08 PM
To: [email-masked]; [email-masked]
Cc: [email-masked]; [email-masked]
Subject: Re: [IBIS-Users] IBIS bump question

A 'bump' is on the die and a RDL(redistribution later)connects the bump to 
the package..

Maybe it should be part of the die instead..

Syed

>Date: Fri, 22 Nov 2002 14:29:48 -0800
>From: Fred Balistreri <[email-masked]>
>X-Accept-Language: en
>MIME-Version: 1.0
>To: [email-masked]
>CC: "'Eric Hsu'" <[email-masked]>, [email-masked]
>Subject: Re: [IBIS-Users] IBIS bump question
>Content-Transfer-Encoding: 7bit
>
>It does not matter, so long as it does not get double counted. I believe
>the solder bump may appear in the CAD package data base. If so it should
>be made part of the package not the IC. 
>
>Best Regards,
>
>Tom Dagostino wrote:
>> 
>> I started to say the bump C should be part of the package but in 
reflection
>> it seems to be part of the die.  I'd vote for as part of C_comp because 
it
>> is part of the metalization on the die.
>> 
>> Tom Dagostino
>> Device Modeling Division
>> Teraspeed Consulting Group LLC
>> 2926 SE Yamhill St.
>> Portland, OR 97214
>> (503) 430-1065
>> [email-masked]
>> http://www.teraspeed.com
>> 
>> -----Original Message-----
>> From: [email-masked]
>> [mailto:[email-masked]]On Behalf Of Eric Hsu
>> Sent: Friday, November 22, 2002 12:20 PM
>> To: [email-masked]
>> Subject: [IBIS-Users] IBIS bump question
>> 
>> Hi all,
>> 
>> For a wire-bond package, the RLC of the bondwire is generally considered
>> to be part of the package.  For a flip-chip package, is there a 
convention
>> for how the bump parasitics should be handled?  Is the bump to be
>> considered part of the package, or part of the die(C_comp)?
>> 
>> Regards,
>> 
>> |------------------------------------------------------------------
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>
>-- 
>Fred Balistreri
>[email-masked]
>
>http://www.apsimtech.com
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------------------------------

Date: Fri, 22 Nov 2002 15:17:35 -0800
From: Fred Balistreri <[email-masked]>
Subject: Re: [IBIS-Users] IBIS bump question

We know the bump is on the die. The question is does it appear
in the CAD data base of the package. If so then putting in the
IC model would not be the correct thing to do because it would
be counted in the IC package data as well. I do not know the
answer to this. It probably depends on the CAD tool used to
model the package. Some IC package tools go all the way to
including some of the die information. At any rate I believe
the answer lies in knowing what is included in the package data.

Best Regards,

"Muranyi, Arpad" wrote:
> 
> I don't have any strong preferences where it is modeled, but
> for the sake of consistency I would mention that solder balls
> are part of the package, not the PCB to which the chip is soldered.
> So similarly, I would think that the bumps should be part of the
> die and not the package to which it is soldered (welded?).
> 
> Arpad Muranyi
> Intel Corporation
> ===================================================================
> 
> -----Original Message-----
> From: Syed Huq [mailto:[email-masked]]
> Sent: Friday, November 22, 2002 3:08 PM
> To: [email-masked]; [email-masked]
> Cc: [email-masked]; [email-masked]
> Subject: Re: [IBIS-Users] IBIS bump question
> 
> A 'bump' is on the die and a RDL(redistribution later)connects the bump to
> the package..
> 
> Maybe it should be part of the die instead..
> 
> Syed
> 
> >Date: Fri, 22 Nov 2002 14:29:48 -0800
> >From: Fred Balistreri <[email-masked]>
> >X-Accept-Language: en
> >MIME-Version: 1.0
> >To: [email-masked]
> >CC: "'Eric Hsu'" <[email-masked]>, [email-masked]
> >Subject: Re: [IBIS-Users] IBIS bump question
> >Content-Transfer-Encoding: 7bit
> >
> >It does not matter, so long as it does not get double counted. I believe
> >the solder bump may appear in the CAD package data base. If so it should
> >be made part of the package not the IC.
> >
> >Best Regards,
> >
> >Tom Dagostino wrote:
> >>
> >> I started to say the bump C should be part of the package but in
> reflection
> >> it seems to be part of the die.  I'd vote for as part of C_comp because
> it
> >> is part of the metalization on the die.
> >>
> >> Tom Dagostino
> >> Device Modeling Division
> >> Teraspeed Consulting Group LLC
> >> 2926 SE Yamhill St.
> >> Portland, OR 97214
> >> (503) 430-1065
> >> [email-masked]
> >> http://www.teraspeed.com
> >>
> >> -----Original Message-----
> >> From: [email-masked]
> >> [mailto:[email-masked]]On Behalf Of Eric Hsu
> >> Sent: Friday, November 22, 2002 12:20 PM
> >> To: [email-masked]
> >> Subject: [IBIS-Users] IBIS bump question
> >>
> >> Hi all,
> >>
> >> For a wire-bond package, the RLC of the bondwire is generally considered
> >> to be part of the package.  For a flip-chip package, is there a
> convention
> >> for how the bump parasitics should be handled?  Is the bump to be
> >> considered part of the package, or part of the die(C_comp)?
> >>
> >> Regards,
> >>
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> >
> >--
> >Fred Balistreri
> >[email-masked]
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> >http://www.apsimtech.com
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------------------------------

Date: Fri, 22 Nov 2002 17:29:17 -0800
From: "Ross, Bob" <[email-masked]>
Subject: Re: [IBIS-Users] FW: Modelling an open drain driver

Andy:

As a correction to the last statement, only V_fixture voltages
at around Vcc or above make sense for Open_drain models.  There
should be no switching action when V_fixture = 0.

Bob Ross
Mentor Graphics

"Ingraham, Andrew" wrote:
> 
> I wrote:
> 
> > For R_fixture, using 60 ohms in parallel with Rpullup, would come
> > closer
> > to the actual circuit.  Unless you intended for Rpullup to be on the
> > far
> > (receiver) end of the 60 ohm trace.
> 
> I forgot to say ... you should have a waveform with V_fixture = 0V and
> another with V_fixture = Vpullup.
> 
> Andy
> 
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------------------------------

Date: Mon, 25 Nov 2002 09:06:08 +0100
From: "Henrik G. Madsen" <[email-masked]>
Subject: RE: [IBIS-Users] FW: Modelling an open drain driver

An extra comment

Andrew Ingraham made the following comment, and I think he might be right.

"When the driver initially switches, and until the round-trip delay of the attached transmission line, the driver effectively sees a load of Rpullup in parallel with 60 ohms.  After reflections on the transmission line have died out, it sees mostly just the Rpullup.  So maybe you should provide waveforms for both values of R_fixture in the model file, and hope that the simulator knows how to figure it out and interpolate between them."

Currently, I just have the following 4 waveforms
[Rising waveform]  60 3.3 3.0 3.6 NA NA NA NA NA
[Falling waveform]  60 3.3 3.0 3.6 NA NA NA NA NA
[Rising waveform]  60 2.5 2.3 2.7 NA NA NA NA NA
[Falling waveform]  60 2.5 2.3 2.7 NA NA NA NA NA

The final value for the high voltage is dependent on Vpullup and Rpullup and not the transmission line.

As Andy suggest, should I also include some extra waveforms, which shows this situation and do the simulators have the ability to use these anyway?

******** Original circuit ********************
Vpullup is either 2.5V or 3.3V. Rpullup > 1.5k ohm
                                                              
                        ___Vpullup                            
                        |                                     
                        |                                     
                        /                                     
                        \ Rpullup                __________   
         OD driver      /                       |          |  
                        \     ____________      |          |  
              ______.___|____|   60 ohm   |_____| Receiver |  
             |               |____________|     |          |  
            _|                                  |          |  
          -|_                                   |__________|  
             |                                                
             |                                                
             |__ VSS                                          
                                                              
                    |
      -----Driver---|-----------normal use circuit--------------

_____________________________________
Henrik G Madsen
Sr. HW Engineer 
Vitesse Semiconductor Corporation A/S
Ethernet Products Division
Hoerkaer 16,  DK-2730 Herlev, DENMARK
Direct: +45 4485 5920
Phone: +45 4485 5900, Fax: +45 4485 5901
mail: [email-masked]
web: http://www.vitesse.com
_____________________________________

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------------------------------

Date: Mon, 25 Nov 2002 09:05:16 +0100
From: "Henrik G. Madsen" <[email-masked]>
Subject: RE: [IBIS-Users] FW: Modelling an open drain driver

Thanks for the clarification.

Having waveforms with V_fixture = 0, creates the below ERROR message, where you are told that your endpoint is where it should be, but you are 100% off.

ERROR - Model osoc2_od: The [Rising Waveform] 
      with [R_fixture]=60 Ohms and [V_fixture]=0V
      has TYP column DC endpoints of  0.00V and  0.00v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages (-0.00V and  0.00V),
      a difference of -100.00% and 100.00%, respectively.

/Henrik
- -----Original Message-----
From: Ross, Bob [mailto:[email-masked]]
Sent: 23. november 2002 02:29
To: Ingraham, Andrew
Cc: Henrik G. Madsen; [email-masked]
Subject: Re: [IBIS-Users] FW: Modelling an open drain driver

Andy:

As a correction to the last statement, only V_fixture voltages
at around Vcc or above make sense for Open_drain models.  There
should be no switching action when V_fixture = 0.

Bob Ross
Mentor Graphics

"Ingraham, Andrew" wrote:
> 
> I wrote:
> 
> > For R_fixture, using 60 ohms in parallel with Rpullup, would come
> > closer
> > to the actual circuit.  Unless you intended for Rpullup to be on the
> > far
> > (receiver) end of the 60 ohm trace.
> 
> I forgot to say ... you should have a waveform with V_fixture = 0V and
> another with V_fixture = Vpullup.
> 
> Andy
> 
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------------------------------

Date: Mon, 25 Nov 2002 00:16:35 -0800
From: "Scott McMorrow" <[email-masked]>
Subject: Re: [IBIS-Users] IBIS bump question

Eric,

In reality, there is no convention.  It depends upon how the flip-chip 
package is engineered.  In some cases the bump is directly on the pad. 
In this case, there is an added capacitance that is often not modeled by 
the silicon vendor.  Whether it is lumped in with the package or with 
the die makes little difference, as long as model is construced 
consistent with the approach used.

Another type of flip-chip package uses a redistribution layer, a layer 
of additional metalization on top of the original die, that 
redistributes the IO pads at the edge of the die back in to where the 
die bumps are located.  In this case, the redistribution layer can have 
significant length and must be modeled as additional package.  (This is 
especially the case for mixed analog and digital ICs, where great pains 
have been taken to isolate the two sections.)  The redistribution metal 
will have R, L and C characteristics that need to be modeled.  In many 
cases, this area is not modeled, even in the vendor delivered Spice files.

regards,

scott

- -- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com

Eric Hsu wrote:

>Hi all,
>
>For a wire-bond package, the RLC of the bondwire is generally considered
>to be part of the package.  For a flip-chip package, is there a convention
>for how the bump parasitics should be handled?  Is the bump to be
>considered part of the package, or part of the die(C_comp)?
>
>Regards,
>
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------------------------------

Date: Mon, 25 Nov 2002 14:40:26 -0800
From: "Angulo, John" <[email-masked]>
Subject: RE: [IBIS-Users] FW: Modelling an open drain driver

In the case of most open-drain or open-source models, a single pair of V-T tables, one rising and one falling, is generally adequate to define the turn-on and turn-off behavior of the buffer.  Since the intended net load on your buffer is about 60 ohms at the start of switching (Rpullup > 1.5 kohm), R_fixture = 60 ohms sounds fine.  The point is to characterize the transient behavior of the device.  A V_fixture of either 2.5 or 3.3 V will probably be adequate.  No harm in keeping all four tables you currently have, however.  No tool should be confused by them, and the additional information may result in slightly better accuracy.  I would recommend double checking that the model passes the official parser and submitting it to the Model Review Committee for feedback from tool vendors.

Best regards,

John Angulo
Hyperlynx Products
Mentor Graphics Corp.
[email-masked]
425-869-2320
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------------------------------

Date: Tue, 26 Nov 2002 10:24:29 +0100
From: "Henrik G. Madsen" <[email-masked]>
Subject: [IBIS-Users] s2ibis2 problem with 3-stateable OD drivers

To me it seems that s2ibis2 do not support generation of open-drain models with tri-state outputs properly.
I'm using the Windows version, but I believe that the issue is of general nature.

********** From .s2i file
[Pin]
pad pad pad osoc2_od
- -> D EN
D D D input
EN EN EN enable
VDD VDD VDD POWER
VSS VSS VSS GND

[Model]  osoc2_od
[Model type]  Open_sink
[Polarity]  Non-Inverting
[Enable]  Active-low
*************

The above will not generate the correct VI tables.

By using the above info, s2ibis2 will generate spice simulations for
 1) 'Pulldown curve'
 2) 'Pulldown curve with output disabled'
but no 'Ground clamp' simulation.
I assume it then  creates the IBIS PULLDOWN curve by subtraction the second curve from the first one (only for negative voltages).
The resulting IBIS model only has one VI curve, the modified PULLDOWN where the clamping has been subtracted. But it does not add the missing current by adding a 'Ground Clamp' curve.

It seems that a correct result only can be obtained by removing the enable signal and run s2ibis2 with that, Or create the missing 'Ground Clamp' curve manually.

Can it be true that s2ibis2 do not support OD-drivers with enable signal?

_____________________________________
Henrik G Madsen
Sr. HW Engineer 
Vitesse Semiconductor Corporation A/S
Ethernet Products Division
Hoerkaer 16,  DK-2730 Herlev, DENMARK
Direct: +45 4485 5920
Phone: +45 4485 5900, Fax: +45 4485 5901
mail: [email-masked]
web: http://www.vitesse.com
_____________________________________

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------------------------------

Date: Tue, 26 Nov 2002 10:14:57 -0800
From: Fred Balistreri <[email-masked]>
Subject: Re: [IBIS-Users] s2ibis2 problem with 3-stateable OD drivers

Hello Henrik, your information below says Open_sink not Open_drain.
No matter, you may want to try I/O_open_drain (or sink) as the proper
pin type. 

Best Regards,

"Henrik G. Madsen" wrote:
> 
> To me it seems that s2ibis2 do not support generation of open-drain models with tri-state outputs properly.
> I'm using the Windows version, but I believe that the issue is of general nature.
> 
> ********** From .s2i file
> [Pin]
> pad pad pad osoc2_od
> -> D EN
> D D D input
> EN EN EN enable
> VDD VDD VDD POWER
> VSS VSS VSS GND
> 
> [Model]  osoc2_od
> [Model type]  Open_sink
> [Polarity]  Non-Inverting
> [Enable]  Active-low
> *************
> 
> The above will not generate the correct VI tables.
> 
> By using the above info, s2ibis2 will generate spice simulations for
>  1) 'Pulldown curve'
>  2) 'Pulldown curve with output disabled'
> but no 'Ground clamp' simulation.
> I assume it then  creates the IBIS PULLDOWN curve by subtraction the second curve from the first one (only for negative voltages).
> The resulting IBIS model only has one VI curve, the modified PULLDOWN where the clamping has been subtracted. But it does not add the missing current by adding a 'Ground Clamp' curve.
> 
> It seems that a correct result only can be obtained by removing the enable signal and run s2ibis2 with that, Or create the missing 'Ground Clamp' curve manually.
> 
> Can it be true that s2ibis2 do not support OD-drivers with enable signal?
> 
> _____________________________________
> Henrik G Madsen
> Sr. HW Engineer
> Vitesse Semiconductor Corporation A/S
> Ethernet Products Division
> Hoerkaer 16,  DK-2730 Herlev, DENMARK
> Direct: +45 4485 5920
> Phone: +45 4485 5900, Fax: +45 4485 5901
> mail: [email-masked]
> web: http://www.vitesse.com
> _____________________________________
> 
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- -- 
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[email-masked]

http://www.apsimtech.com
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------------------------------

Date: Wed, 27 Nov 2002 11:01:55 +0100
From: "Henrik G. Madsen" <[email-masked]>
Subject: RE: [IBIS-Users] s2ibis2 problem with 3-stateable OD drivers

Fred, 

Thanks for the input.

As far as I can read the IBIS standard, 'Open_sink' and 'Open_drain' are the same, where the first one is the preffered type. Correct me if I'm wrong.

It actually works to use the I/O_open_sink :-)

I will use the I/O_open_sink model type in the .s2i file to get the correct VI curves, but change the modeltype back to 'Open_sink' in the final IBIS file to get the correct model type.

/Henrik

- -----Original Message-----
From: Fred Balistreri [mailto:[email-masked]]
Sent: 26. november 2002 19:15
To: Henrik G. Madsen
Cc: [email-masked]
Subject: Re: [IBIS-Users] s2ibis2 problem with 3-stateable OD drivers

Hello Henrik, your information below says Open_sink not Open_drain.
No matter, you may want to try I/O_open_drain (or sink) as the proper
pin type. 

Best Regards,

"Henrik G. Madsen" wrote:
> 
> To me it seems that s2ibis2 do not support generation of open-drain models with tri-state outputs properly.
> I'm using the Windows version, but I believe that the issue is of general nature.
> 
> ********** From .s2i file
> [Pin]
> pad pad pad osoc2_od
> -> D EN
> D D D input
> EN EN EN enable
> VDD VDD VDD POWER
> VSS VSS VSS GND
> 
> [Model]  osoc2_od
> [Model type]  Open_sink
> [Polarity]  Non-Inverting
> [Enable]  Active-low
> *************
> 
> The above will not generate the correct VI tables.
> 
> By using the above info, s2ibis2 will generate spice simulations for
>  1) 'Pulldown curve'
>  2) 'Pulldown curve with output disabled'
> but no 'Ground clamp' simulation.
> I assume it then  creates the IBIS PULLDOWN curve by subtraction the second curve from the first one (only for negative voltages).
> The resulting IBIS model only has one VI curve, the modified PULLDOWN where the clamping has been subtracted. But it does not add the missing current by adding a 'Ground Clamp' curve.
> 
> It seems that a correct result only can be obtained by removing the enable signal and run s2ibis2 with that, Or create the missing 'Ground Clamp' curve manually.
> 
> Can it be true that s2ibis2 do not support OD-drivers with enable signal?
> 
> _____________________________________
> Henrik G Madsen
> Sr. HW Engineer
> Vitesse Semiconductor Corporation A/S
> Ethernet Products Division
> Hoerkaer 16,  DK-2730 Herlev, DENMARK
> Direct: +45 4485 5920
> Phone: +45 4485 5900, Fax: +45 4485 5901
> mail: [email-masked]
> web: http://www.vitesse.com
> _____________________________________
> 
> |------------------------------------------------------------------
> |For help or to subscribe/unsubscribe, email [email-masked]
> |with just the appropriate command message(s) in the body:
> |
> |  help
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> |
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> |
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> |
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- -- 
Fred Balistreri
[email-masked]

http://www.apsimtech.com

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------------------------------

Date: Wed, 27 Nov 2002 16:05:45 +0100
From: "Henrik G. Madsen" <[email-masked]>
Subject: [IBIS-Users] LVDS driver modeling

This is a multi-part message in MIME format.

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Hey All,

I'm trying to model a LVDS driver using the methods decribed by Adam =
Tambone in the article "Creating accurate LVDS models"

1)
Is it possible to use the above approach along with the s2ibis2 tool =
with an appropriate circuit file?

2)
If YES, do anybody have a .s2i setup file and necessary circuits file, =
they would like to share?

Regards
_____________________________________
Henrik G Madsen
Sr. HW Engineer=20
Vitesse Semiconductor Corporation A/S
Ethernet Products Division
Hoerkaer 16,  DK-2730 Herlev, DENMARK
Direct: +45 4485 5920
Phone: +45 4485 5900, Fax: +45 4485 5901
mail: [email-masked]
web: http://www.vitesse.com
_____________________________________

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charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
6.0.5762.3">
<TITLE>LVDS driver modeling</TITLE>
</HEAD>
<BODY>
<!-- Converted from text/rtf format -->

<P><FONT SIZE=3D2 FACE=3D"Arial">Hey All,</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">I'm trying to model a LVDS driver using =
the methods decribed by Adam Tambone in the article &quot;Creating =
accurate LVDS models&quot;</FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Arial">1)</FONT>

<BR><FONT SIZE=3D2 FACE=3D"Arial">Is it possible to use the above =
approach along with the s2ibis2 tool with an appropriate circuit =
file?</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">2)</FONT>

<BR><FONT SIZE=3D2 FACE=3D"Arial">If YES, do anybody have a .s2i setup =
file and necessary circuits file, they would like to share?</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Regards</FONT>

<BR><FONT SIZE=3D2 =
FACE=3D"Arial">_____________________________________</FONT>

<BR><FONT SIZE=3D2 FACE=3D"Arial">Henrik G Madsen</FONT>

<BR><SPAN LANG=3D"da"><FONT SIZE=3D2 =
FACE=3D"Arial">Sr.</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"> <FONT SIZE=3D2 FACE=3D"Arial">HW Engineer </FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">Vitesse =
Semiconductor Corporation A/S</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">Ethernet Products =
Division</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">Hoerkaer =
16,&nbsp; DK-2730 Herlev, DENMARK</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">Direct: +45 4485 =
5920</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">Phone: +45 4485 =
5900, Fax: +45 4485 5901</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">mail: =
[email-masked]</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">web: <A =
HREF=3D"http://www.vitesse.com">http://www.vitesse.com</A></FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial">_____________________________________</FONT></SPAN>
</P>
<BR>

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|
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|
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------------------------------

Date: Wed, 27 Nov 2002 08:18:29 -0800
From: Fred Balistreri <[email-masked]>
Subject: Re: [IBIS-Users] s2ibis2 problem with 3-stateable OD drivers

Hello Henrik, the correct pin type to use is I/O_open_sink or drain 
which ever you prefer. If you use Open_sink or Open_drain then it
is assumed that the part is a driver only. The I/O is what tells the
simulators that there is an enable/disable pin that puts the output
stage in tri-state or receiving mode. The mechanism also tells S2ibis
how to test the part. If it is just an open sink without the tri-state
or input then the gnd/pwr clamps are not needed because they are 
contained in the pullup or pulldown data. Sorry I misread open_sink 
as open_source. 

Best Regards,

"Henrik G. Madsen" wrote:
> 
> Fred,
> 
> Thanks for the input.
> 
> As far as I can read the IBIS standard, 'Open_sink' and 'Open_drain' are the same, where the first one is the preffered type. Correct me if I'm wrong.
> 
> It actually works to use the I/O_open_sink :-)
> 
> I will use the I/O_open_sink model type in the .s2i file to get the correct VI curves, but change the modeltype back to 'Open_sink' in the final IBIS file to get the correct model type.
> 
> /Henrik
> 
> -----Original Message-----
> From: Fred Balistreri [mailto:[email-masked]]
> Sent: 26. november 2002 19:15
> To: Henrik G. Madsen
> Cc: [email-masked]
> Subject: Re: [IBIS-Users] s2ibis2 problem with 3-stateable OD drivers
> 
> Hello Henrik, your information below says Open_sink not Open_drain.
> No matter, you may want to try I/O_open_drain (or sink) as the proper
> pin type.
> 
> Best Regards,
> 
> "Henrik G. Madsen" wrote:
> >
> > To me it seems that s2ibis2 do not support generation of open-drain models with tri-state outputs properly.
> > I'm using the Windows version, but I believe that the issue is of general nature.
> >
> > ********** From .s2i file
> > [Pin]
> > pad pad pad osoc2_od
> > -> D EN
> > D D D input
> > EN EN EN enable
> > VDD VDD VDD POWER
> > VSS VSS VSS GND
> >
> > [Model]  osoc2_od
> > [Model type]  Open_sink
> > [Polarity]  Non-Inverting
> > [Enable]  Active-low
> > *************
> >
> > The above will not generate the correct VI tables.
> >
> > By using the above info, s2ibis2 will generate spice simulations for
> >  1) 'Pulldown curve'
> >  2) 'Pulldown curve with output disabled'
> > but no 'Ground clamp' simulation.
> > I assume it then  creates the IBIS PULLDOWN curve by subtraction the second curve from the first one (only for negative voltages).
> > The resulting IBIS model only has one VI curve, the modified PULLDOWN where the clamping has been subtracted. But it does not add the missing current by adding a 'Ground Clamp' curve.
> >
> > It seems that a correct result only can be obtained by removing the enable signal and run s2ibis2 with that, Or create the missing 'Ground Clamp' curve manually.
> >
> > Can it be true that s2ibis2 do not support OD-drivers with enable signal?
> >
> > _____________________________________
> > Henrik G Madsen
> > Sr. HW Engineer
> > Vitesse Semiconductor Corporation A/S
> > Ethernet Products Division
> > Hoerkaer 16,  DK-2730 Herlev, DENMARK
> > Direct: +45 4485 5920
> > Phone: +45 4485 5900, Fax: +45 4485 5901
> > mail: [email-masked]
> > web: http://www.vitesse.com
> > _____________________________________
> >
> > |------------------------------------------------------------------
> > |For help or to subscribe/unsubscribe, email [email-masked]
> > |with just the appropriate command message(s) in the body:
> > |
> > |  help
> > |  subscribe   ibis       <optional e-mail address, if different>
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> > |  unsubscribe ibis-users <optional e-mail address, if different>
> > |
> > |or email a written request to [email-masked].
> > |
> > |IBIS reflector archives exist under:
> > |
> > |  http://www.eda.org/pub/ibis/email_archive/  Recent
> > |  http://www.eda.org/pub/ibis/users_archive/  Recent
> > |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
> 
> --
> Fred Balistreri
> [email-masked]
> 
> http://www.apsimtech.com
> 
> |------------------------------------------------------------------
> |For help or to subscribe/unsubscribe, email [email-masked]
> |with just the appropriate command message(s) in the body:
> |
> |  help
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- -- 
Fred Balistreri
[email-masked]

http://www.apsimtech.com
|------------------------------------------------------------------
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------------------------------

Date: Wed, 27 Nov 2002 10:19:11 -0800
From: "Angulo, John" <[email-masked]>
Subject: [IBIS-Users] Generic PCI or PCI-X IBIS model research.

The following is posted on behalf of Benoit Bouchard at Kontron Canada.  Please send any private replies to [email-masked] only.

- -----------------------------------

I'm looking for Generic IBIS model to do some simulation on a PCI/PCIX
backplane which will have PCI I/O devices on.
Any idea if their is any Generic model for PCI or PCIX devices?

Thank you for your time.
> Benoit Bouchard ing. / eng. 
> Concepteur materiel / Hardware designer 
> Produit Standard / Standard Product 
> Kontron Canada Inc 
> 
> Tel/fax: (450) 437-5682/8053 
> (1-800-387-4222); ext. 2249 
> <http://www.kontron.com> 
> <mailto:[email-masked]> 
> 
> 
|------------------------------------------------------------------
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------------------------------

Date: Fri, 29 Nov 2002 16:35:20 +0100
From: "Henrik G. Madsen" <[email-masked]>
Subject: [IBIS-Users] LVDS driver VT curves selection

This is a multi-part message in MIME format.

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Hey all

I have read most of the latest presentations on making IBIS models for =
LVDS drivers with interest, but....

How many VT curves to include in the initial model?

For very short tracks (I.e. the 100 ohm diff termination very close to =
the driver, no transmission line),  two waveforms should be enough

[Rising waveform]  50 Vcm(typ) Vcm(min) Vcm(max) NA NA NA NA NA
[Falling waveform]  50 Vcm(typ) Vcm(min) Vcm(max) NA NA NA NA NA

where Vcm(???) is the out common mode voltage

To include the cases where the driver is connected to a transmission =
line with a diff impedance of 100 ohm, the following waveforms should be =
made too

[Rising waveform]  50 Vol(typ) Vol(min) Vol(max) NA NA NA NA NA
[Falling waveform]  50 Voh(typ) Voh(min) Voh(max) NA NA NA NA NA

(The driver sees a 100 ohm transmission line, but since both pads change =
opposite, the real voltage swing is the double. To include that in the =
above I have halfed the impedance)

Is more waveforms needed?

_____________________________________
Henrik G Madsen
Sr. HW Engineer=20
Vitesse Semiconductor Corporation A/S
Ethernet Products Division
Hoerkaer 16,  DK-2730 Herlev, DENMARK
Direct: +45 4485 5920
Phone: +45 4485 5900, Fax: +45 4485 5901
mail: [email-masked]
web: http://www.vitesse.com
_____________________________________

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charset=3Diso-8859-1">
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<TITLE>LVDS driver VT curves selection</TITLE>
</HEAD>
<BODY>
<!-- Converted from text/rtf format -->

<P><FONT SIZE=3D2 FACE=3D"Arial">Hey all</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">I have read most of the latest =
presentations on making IBIS models for LVDS drivers with interest, =
but....</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">How many VT curves to include in the =
initial model?</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">For very short tracks (I.e. the 100 ohm =
diff termination very close to the driver, no transmission line),&nbsp; =
two waveforms should be enough</FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Arial">[Rising waveform]&nbsp; 50 Vcm(typ) =
Vcm(min) Vcm(max) NA NA NA NA NA</FONT>

<BR><FONT SIZE=3D2 FACE=3D"Arial">[Falling waveform]&nbsp; 50 Vcm(typ) =
Vcm(min) Vcm(max) NA NA NA NA NA</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">where Vcm(???) is the out common mode =
voltage</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">To include the cases where the driver =
is connected to a transmission line with a diff impedance of 100 ohm, =
the following waveforms should be made too</FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Arial">[Rising waveform]&nbsp; 50 Vol(typ) =
Vol(min) Vol(max) NA NA NA NA NA</FONT>

<BR><FONT SIZE=3D2 FACE=3D"Arial">[Falling waveform]&nbsp; 50 Voh(typ) =
Voh(min) Voh(max) NA NA NA NA NA</FONT>
</P>

<P><FONT SIZE=3D2 FACE=3D"Arial">(The driver sees a 100 ohm transmission =
line, but since both pads change opposite, the real voltage swing is the =
double. To include that in the above I have halfed the =
impedance)</FONT></P>

<P><FONT SIZE=3D2 FACE=3D"Arial">Is more waveforms needed?</FONT>
</P>

<P><FONT SIZE=3D2 =
FACE=3D"Arial">_____________________________________</FONT>

<BR><FONT SIZE=3D2 FACE=3D"Arial">Henrik G Madsen</FONT>

<BR><SPAN LANG=3D"da"><FONT SIZE=3D2 =
FACE=3D"Arial">Sr.</FONT></SPAN><SPAN LANG=3D"en-us"></SPAN><SPAN =
LANG=3D"en-us"> <FONT SIZE=3D2 FACE=3D"Arial">HW Engineer </FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">Vitesse =
Semiconductor Corporation A/S</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">Ethernet Products =
Division</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">Hoerkaer =
16,&nbsp; DK-2730 Herlev, DENMARK</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">Direct: +45 4485 =
5920</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">Phone: +45 4485 =
5900, Fax: +45 4485 5901</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">mail: =
[email-masked]</FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 FACE=3D"Arial">web: <A =
HREF=3D"http://www.vitesse.com">http://www.vitesse.com</A></FONT></SPAN>

<BR><SPAN LANG=3D"en-us"><FONT SIZE=3D2 =
FACE=3D"Arial">_____________________________________</FONT></SPAN>
</P>
<BR>

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------------------------------

Date: Tue, 3 Dec 2002 19:58:18 -0800
From: "Eric Hsu" <[email-masked]>
Subject: [IBIS-Users] [model selector] issue

Hi All,

In ver3.2 ibis model, if using [model selector] to specify model, is there
any option we can use to define default model in the [model selector]?

Best Regard,

~eric

|------------------------------------------------------------------
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|with just the appropriate command message(s) in the body:
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------------------------------

Date: Tue, 3 Dec 2002 22:18:01 -0800 (PST)
From: Syed Huq <[email-masked]>
Subject: Re: [IBIS-Users] [model selector] issue

I believe the first buffer under the [Model selector] will be the default 
one.

Syed

>From: "Eric Hsu" <[email-masked]>
>To: <[email-masked]>
>Subject: [IBIS-Users] [model selector] issue
>Date: Tue, 3 Dec 2002 19:58:18 -0800
>MIME-Version: 1.0
>Content-Transfer-Encoding: 7bit
>X-Priority: 3 (Normal)
>X-MSMail-Priority: Normal
>X-MimeOLE: Produced By Microsoft MimeOLE V5.50.4920.2300
>Importance: Normal
>
>Hi All,
>
>In ver3.2 ibis model, if using [model selector] to specify model, is there
>any option we can use to define default model in the [model selector]?
>
>Best Regard,
>
>~eric
>
>|------------------------------------------------------------------
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>|with just the appropriate command message(s) in the body:
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------------------------------

Date: Wed, 4 Dec 2002 18:59:58 -0800 
From: Shee Kian Wong <[email-masked]>
Subject: [IBIS-Users] Rsing/Falling/Ramp

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C29C0A.65459460
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Hi all,

Normally there are 2 sets of rising/falling (1 set for 50W to gnd and 1 set
for 50W to vcc) plus 1 ramp data in an IBIS file. 
Which one does a simulator use? The ramp or the rising/falling data? If
rising/ falling data is used, which set (there are normally >1 set of data)
would be chosen? 
Rgds, 
  
Shee Kian 

- ------_=_NextPart_001_01C29C0A.65459460
Content-Type: text/html
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2653.12">
<TITLE>Rsing/Falling/Ramp</TITLE>
</HEAD>
<BODY>

<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">Hi all,</FONT></P>

<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">Normally there are 2 sets =
of rising/fallin</FONT><FONT SIZE=3D2 FACE=3D"Arial">g</FONT><FONT =
SIZE=3D2 FACE=3D"Arial"></FONT> <FONT SIZE=3D2 FACE=3D"Arial">(1 set =
for 50</FONT><FONT FACE=3D"Symbol" SIZE=3D2>W</FONT><FONT SIZE=3D2 =
FACE=3D"Arial"> to gnd and 1 set for 50</FONT><FONT FACE=3D"Symbol" =
SIZE=3D2>W</FONT><FONT SIZE=3D2 FACE=3D"Arial"> to vcc)</FONT> <FONT =
SIZE=3D2 FACE=3D"Arial">plus 1 ramp data in an IBIS file.</FONT><FONT =
SIZE=3D2 FACE=3D"Arial"></FONT> </P>

<P ALIGN=3DLEFT><FONT SIZE=3D2 FACE=3D"Arial">Which one does a =
simulator use?</FONT><FONT SIZE=3D2 FACE=3D"Arial"> The ramp or the =
rising/falling data? If rising/ falling data is used, which</FONT> =
<FONT SIZE=3D2 FACE=3D"Arial">set (there are normally &gt;1 set of =
data) would be chosen?</FONT> </P>

<P ALIGN=3DLEFT><A NAME=3D"_MailAutoSig"><FONT COLOR=3D"#0000FF" =
SIZE=3D2 FACE=3D"Arial">Rgds,</FONT></A><BR>
<FONT SIZE=3D2 FACE=3D"Arial">&nbsp;</FONT><BR>
<B><I></I></B><B><I><FONT COLOR=3D"#0000FF" SIZE=3D2 =
FACE=3D"Arial">Shee Kian</FONT></I></B> </P>

</BODY>
</HTML>
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------------------------------

Date: Thu, 5 Dec 2002 07:53:51 -0500
From: "Ingraham, Andrew" <[email-masked]>
Subject: [IBIS-Users] RE: [IBIS] Rsing/Falling/Ramp

> Normally there are 2 sets of rising/falling (1 set for 50W to gnd and 1 set for 50W to vcc) plus 1 ramp data in an IBIS file. 
> 
> Which one does a simulator use? The ramp or the rising/falling data? If rising/ falling data is used, which set (there are normally >1 set of data) would be chosen? 
 
That depends entirely on the simulator.

I would expect most simulators to use the Waveform data,
if they are capable of using it.  Some simulators might even
use both.

The first implementation of IBIS models integrated into Hspice,
used only the Ramp data.

In general, a simulator needs to employ some "magic" (a
complicated algorithm) to get from the Waveform data to
actual driven waveforms, because the real load rarely if ever
is a perfect 50 ohm resistor to VCC or to GND.  A good
algorithm might use all available Waveform tables, appropriately
weighted, depending on actual load conditions.  Again, I expect
this to be simulator dependent.  (I believe that Hspice now can
use either one, or two, Waveform tables, but not more than the
first two tables it finds in the IBIS data sheet.  You get to tell it
whether to use one or two.)

Regards,
Andy

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------------------------------

Date: Fri, 6 Dec 2002 07:59:10 -0500
From: "Timothy Coyle" <[email-masked]>
Subject: [IBIS-Users] Vinh for Differential Part

Hello,
I have a differential device in an IBIS file.  I define a Vdiff of 100mV
for my differential signal thresholds. However, I also have to define a
Vinh and Vinl
for the single-ended positive and negative differential Input model types
in IBIS. The IBIS spec (3.2) states that:

If a pin is a differential input pin, the differential input
| threshold (vdiff) overrides and supersedes the need for Vinh
| and Vinl.

However, if I do not define a Vinh and Vinl for my differential inputs,
then the IBIS parser gives me a warning.  It also seems that some
simulators use this
Vinh and Vinl for the single-ended differential signals. If this is an LVDS
input, switching from 1 to 1.4 V, then I could put thresholds of 1.1 and
1.3?

I'm curious as to what other people do and why the parser gives me this
warning?

Regards,
Tim

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------------------------------

Date: Fri, 6 Dec 2002 08:40:01 -0800 
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] Agenda, IBIS Open Forum Teleconference 12/13

		     IBIS Open Forum Meeting Agenda
			      for 12/13/02

		Bridge Number    Reservation #   Passcode
                1-916-356-2663      3            5013842

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Stephen Peters and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Peters

     - Intros of New IBIS Participants, Meeting Quorum       Peters
     - Call for Patents                                      Peters
     - Membership Update and Treasurers Report               Peters
     - Review of Previous Meeting's Minutes (and ARs)        Peters
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Leventhal, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters

     DesignCon2003 IBIS Summit Meeting Planning              Peters

     IBIS Version 4.0 Parser Funding                         Peters

     IBIS Quality Committee                                  Katz

     IBIS Model Review Committee                             Green

     New Administrative Issues                               All

8:45 Technical Discussion

     IBIS Connector and Futures Group Report                 Peters/Green
     - ICM Specification Proposal

     BIRD75.7 - Multi-Lingual IBIS Model Support             Ross/Muranyi
     BIRD77.2 - Differential Subparameter Additions          Ross

     BIRD80 - Add External Reference Column to Pin           Mirmak
              Mapping Keyword

     BIRD78.1 - Comment Line Length Limit                    Green

     BIRD79 - Non-linear Buffer Impedance
Muranyi/Giacotto

     BIRD74.2 - EMI Parameters                               de Burgh

     ibischk3 Status                                         Ross
     - BUG71 - Monotonic Checking for Combined I-V Tables    Haller
     - BUG74 - Missing Timing Test Load Warning Messages     Haller
     - BUG77 - Test for Series* Models in [Pin] Error        Ross
     - BUG78 - Clamp Current Double Counting Test            Leventhal/Ross

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Peters

9:55 Sign Off
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------------------------------

Date: Fri, 06 Dec 2002 09:29:49 -0800
From: Vinu Arumugham <[email-masked]>
Subject: Re: [IBIS-Users] Vinh for Differential Part

Since these threshold voltages are used for timing measurements and since
datasheets specify timing at the zero crossing or Vddq/2 level, would it not
be better to set Vdiff=0, Vinl=Vinh=1.2V?

Thanks,
Vinu

Timothy Coyle wrote:

> Hello,
> I have a differential device in an IBIS file.  I define a Vdiff of 100mV
> for my differential signal thresholds. However, I also have to define a
> Vinh and Vinl
> for the single-ended positive and negative differential Input model types
> in IBIS. The IBIS spec (3.2) states that:
>
> If a pin is a differential input pin, the differential input
> | threshold (vdiff) overrides and supersedes the need for Vinh
> | and Vinl.
>
> However, if I do not define a Vinh and Vinl for my differential inputs,
> then the IBIS parser gives me a warning.  It also seems that some
> simulators use this
> Vinh and Vinl for the single-ended differential signals. If this is an LVDS
> input, switching from 1 to 1.4 V, then I could put thresholds of 1.1 and
> 1.3?
>
> I'm curious as to what other people do and why the parser gives me this
> warning?
>
> Regards,
> Tim
>
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------------------------------

Date: Fri, 6 Dec 2002 09:46:09 -0800
From: "Tom Dagostino" <[email-masked]>
Subject: RE: [IBIS-Users] Vinh for Differential Part

The switching point for a differential input happens when the difference in
the input voltage reaches the Vdiff value.  In this case the common mode
voltage is 1.2 Volts and the inputs need to be at least 100 mV different to
cause the input to recognize state.  Thus 1.15 and 1.25 volts would be the
appropriate Vinl/Vinh values.

Tom Dagostino
Device Modeling Division
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 430-1065
[email-masked]
http://www.teraspeed.com

- -----Original Message-----
From: [email-masked]
[mailto:[email-masked]]On Behalf Of Vinu Arumugham
Sent: Friday, December 06, 2002 9:30 AM
To: Timothy Coyle
Cc: [email-masked]
Subject: Re: [IBIS-Users] Vinh for Differential Part

Since these threshold voltages are used for timing measurements and since
datasheets specify timing at the zero crossing or Vddq/2 level, would it not
be better to set Vdiff=0, Vinl=Vinh=1.2V?

Thanks,
Vinu

Timothy Coyle wrote:

> Hello,
> I have a differential device in an IBIS file.  I define a Vdiff of 100mV
> for my differential signal thresholds. However, I also have to define a
> Vinh and Vinl
> for the single-ended positive and negative differential Input model types
> in IBIS. The IBIS spec (3.2) states that:
>
> If a pin is a differential input pin, the differential input
> | threshold (vdiff) overrides and supersedes the need for Vinh
> | and Vinl.
>
> However, if I do not define a Vinh and Vinl for my differential inputs,
> then the IBIS parser gives me a warning.  It also seems that some
> simulators use this
> Vinh and Vinl for the single-ended differential signals. If this is an
LVDS
> input, switching from 1 to 1.4 V, then I could put thresholds of 1.1 and
> 1.3?
>
> I'm curious as to what other people do and why the parser gives me this
> warning?
>
> Regards,
> Tim
>
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------------------------------

Date: Fri, 6 Dec 2002 13:12:42 -0500
From: "Timothy Coyle" <[email-masked]>
Subject: RE: [IBIS-Users] Vinh for Differential Part

 I think the problem is that the Vth and Vtl defined for the differential
input is being applied to the single-ended signal, and
not the differential signal. A vdiff of +/- 100mV of the common mode input
voltage only applies to the differential signal.  For the single-ended
signal,
I believe the threshold should be  +/-100mV from what ever voltage the
other pin is tied too.  For example, VA  VTH is = VB + 0.1V, VTL = VB -
0.1V.
But if I have Vdiff defined, these values shouldn't be used at all. And if
I don't have Vdiff defined, I do not think that these threshold values are
going
to be used for the differential signal. It might also be irreverent because
is there any situations when one would want to do  any timing measurements
on the single-ended signal rather than the differential signal? If not,
then the parser and EDA tools need to be informed to correct this.

Regards,
Tim

|---------+---------------------------->
|         |           [email-masked] |
|         |                            |
|         |           12/06/2002 12:27 |
|         |           PM               |
|         |                            |
|---------+---------------------------->
  >------------------------------------------------------------------------------------------------------------------------------|
  |                                                                                                                              |
  |       To:       Timothy Coyle/Americas/NSC@NSC                                                                               |
  |       cc:       [email-masked]@Internet                                                                           |
  |       Subject:  RE: [IBIS-Users] Vinh for Differential Part                                                                  |
  >------------------------------------------------------------------------------------------------------------------------------|

Well, your observation is right; the parser will not allow not putting
Vinh and Vinl for an input buffer even if the existence of Vdiff will
override the Vinh/Vinl thresholds.
For levels 1.0 ~1.4 with Vdiff=0.1V, the buffer will switch if you apply
differential voltage of at least 100mV around the common mode input
voltage and not 1.1V and 1.3V
I hope it helps,

BR,

Hazem Hegazy, M.Sc.
IBIS Modeling Engineer
QualiM
http://www.qualim.com/
Phone: (+20) 106052154
E-mail: [email-masked]

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------------------------------

Date: Fri, 6 Dec 2002 13:14:55 -0500
From: "Timothy Coyle" <[email-masked]>
Subject: Re: [IBIS-Users] Vinh for Differential Part

I think that most IBIS simulators use Vdiff as +/- of 0 V, assuming the
differential timing reference point is at 0V.

Regards,
Tim

|---------+---------------------------->
|         |           [email-masked]   |
|         |                            |
|         |           12/06/2002 12:29 |
|         |           PM               |
|         |                            |
|---------+---------------------------->
  >------------------------------------------------------------------------------------------------------------------------------|
  |                                                                                                                              |
  |       To:       Timothy Coyle/Americas/NSC@NSC                                                                               |
  |       cc:       [email-masked]@Internet                                                                                  |
  |       Subject:  Re: [IBIS-Users] Vinh for Differential Part                                                                  |
  >------------------------------------------------------------------------------------------------------------------------------|

Since these threshold voltages are used for timing measurements and since
datasheets specify timing at the zero crossing or Vddq/2 level, would it not
be better to set Vdiff=0, Vinl=Vinh=1.2V?

Thanks,
Vinu

Timothy Coyle wrote:

> Hello,
> I have a differential device in an IBIS file.  I define a Vdiff of 100mV
> for my differential signal thresholds. However, I also have to define a
> Vinh and Vinl
> for the single-ended positive and negative differential Input model types
> in IBIS. The IBIS spec (3.2) states that:
>
> If a pin is a differential input pin, the differential input
> | threshold (vdiff) overrides and supersedes the need for Vinh
> | and Vinl.
>
> However, if I do not define a Vinh and Vinl for my differential inputs,
> then the IBIS parser gives me a warning.  It also seems that some
> simulators use this
> Vinh and Vinl for the single-ended differential signals. If this is an LVDS
> input, switching from 1 to 1.4 V, then I could put thresholds of 1.1 and
> 1.3?
>
> I'm curious as to what other people do and why the parser gives me this
> warning?
>
> Regards,
> Tim
>
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------------------------------

Date: Fri, 6 Dec 2002 11:44:18 -0800 (PST)
From: "Eric Hsu" <[email-masked]>
Subject: [IBIS-Users] Date: Fri, 6 Dec 2002 11:44:28 -0800

Hi all and Arpad,

Could you please share your experience about verification spice and ibis
performance correlation? I found on page 8 of the article "I/O-buffer
modeling spec simplifies simulation for high-speed systems"
(http://www.eigroup.org/ibis/intel.htm), there is a figure mention about
spice and ibis waveform comparison. Do you think it was simulated by the
same tool? If it was, what's tool you used here? Or is anyone know what's
the tool I can use? How about like Hyperlynx, Quad Design, or
Interconnectix?

Best Regard,

Eric Hsu

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------------------------------

Date: Fri, 6 Dec 2002 15:35:07 -0500 
From: "ruston, matt" <[email-masked]>
Subject: [IBIS-Users] Multiple package models

All:

 Hi. What is the best way to embed several different package models into the
same IBIS file? Say I have an FPGA with 3 different possible packages. I
have min, typ, max RLC values for each. Is there a way to select packages on
the fly (like a [Model_selector] keyword)?

 I see the syntax for several different parameters dealing with packages in
the Ibis 3.2 spec, but it is unclear as to what they are actually USED for
or how to use them.

I appreciate the help.

Regards,

Matt
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------------------------------

Date: Fri, 06 Dec 2002 12:39:34 -0800
From: Vinu Arumugham <[email-masked]>
Subject: Re: [IBIS-Users] Vinh for Differential Part

The device might switch when the differential inputs are 100mV apart. However,
if the datasheet timing reference point is the zero crossing, Vdiff should be
set to 0 in the IBIS model and the simulator should use this Vdiff value to
report timing. Setting a different Vdiff value like 100mV in the IBIS model
will result in a timing inaccuracy due to double counting. Likewise for
Vinh/Vinl.

Thanks,
Vinu

Tom Dagostino wrote:

> The switching point for a differential input happens when the difference in
> the input voltage reaches the Vdiff value.  In this case the common mode
> voltage is 1.2 Volts and the inputs need to be at least 100 mV different to
> cause the input to recognize state.  Thus 1.15 and 1.25 volts would be the
> appropriate Vinl/Vinh values.
>
> Tom Dagostino
> Device Modeling Division
> Teraspeed Consulting Group LLC
> 2926 SE Yamhill St.
> Portland, OR 97214
> (503) 430-1065
> [email-masked]
> http://www.teraspeed.com
>
> -----Original Message-----
> From: [email-masked]
> [mailto:[email-masked]]On Behalf Of Vinu Arumugham
> Sent: Friday, December 06, 2002 9:30 AM
> To: Timothy Coyle
> Cc: [email-masked]
> Subject: Re: [IBIS-Users] Vinh for Differential Part
>
> Since these threshold voltages are used for timing measurements and since
> datasheets specify timing at the zero crossing or Vddq/2 level, would it not
> be better to set Vdiff=0, Vinl=Vinh=1.2V?
>
> Thanks,
> Vinu
>
> Timothy Coyle wrote:
>
> > Hello,
> > I have a differential device in an IBIS file.  I define a Vdiff of 100mV
> > for my differential signal thresholds. However, I also have to define a
> > Vinh and Vinl
> > for the single-ended positive and negative differential Input model types
> > in IBIS. The IBIS spec (3.2) states that:
> >
> > If a pin is a differential input pin, the differential input
> > | threshold (vdiff) overrides and supersedes the need for Vinh
> > | and Vinl.
> >
> > However, if I do not define a Vinh and Vinl for my differential inputs,
> > then the IBIS parser gives me a warning.  It also seems that some
> > simulators use this
> > Vinh and Vinl for the single-ended differential signals. If this is an
> LVDS
> > input, switching from 1 to 1.4 V, then I could put thresholds of 1.1 and
> > 1.3?
> >
> > I'm curious as to what other people do and why the parser gives me this
> > warning?
> >
> > Regards,
> > Tim
> >
> > |------------------------------------------------------------------
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------------------------------

Date: Fri, 6 Dec 2002 13:39:51 -0800
From: "Eric Hsu" <[email-masked]>
Subject: [IBIS-Users] FW: 

Hi All,

Is there anyone ever take IBIS mode and spice netlist and use hspice to
simulate on the same environment? I wonder maybe it is the best way to cross
verify correlation between IBIS model and spice netlist. If it is possible,
how can I handle R_pin, L_pin, C_pin, and C_comp those parameter  in the
ibis model? I mean should I add them into my test bench or not?

Best Regard,

Eric Hsu

Senior Design Engineer of Interface Technology
NetLogic Microsystems, Inc.
[email-masked]
650-961-6676 X198

 -----Original Message-----
From: 	Eric Hsu [mailto:[email-masked]]
Sent:	Friday, December 06, 2002 11:44 AM
To:	[email-masked]'; Arpad Muranyi (E-mail)
Subject:

Hi all and Arpad,

Could you please share your experience about verification spice and ibis
performance correlation? I found on page 8 of the article "I/O-buffer
modeling spec simplifies simulation for high-speed systems"
(http://www.eigroup.org/ibis/intel.htm), there is a figure mention about
spice and ibis waveform comparison. Do you think it was simulated by the
same tool? If it was, what's tool you used here? Or is anyone know what's
the tool I can use? How about like Hyperlynx, Quad Design, or
Interconnectix?

Best Regard,

Eric Hsu

|------------------------------------------------------------------
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------------------------------

Date: Fri, 6 Dec 2002 13:40:02 -0800
From: "Tom Dagostino" <[email-masked]>
Subject: RE: [IBIS-Users] Vinh for Differential Part

The problem with setting Vdiff to 0 is slow slew rates or poor transitions
will not give accurate timing.  All of the datasheets that I checked had a
limitation on the maximum transition time (between 1 and 5 nsec) for the
Vdiff = 0 timing.

Tom Dagostino
Device Modeling Division
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 430-1065
[email-masked]
http://www.teraspeed.com

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]
Sent: Friday, December 06, 2002 12:40 PM
To: [email-masked]
Cc: 'Timothy Coyle'; [email-masked]
Subject: Re: [IBIS-Users] Vinh for Differential Part

The device might switch when the differential inputs are 100mV apart.
However,
if the datasheet timing reference point is the zero crossing, Vdiff should
be
set to 0 in the IBIS model and the simulator should use this Vdiff value to
report timing. Setting a different Vdiff value like 100mV in the IBIS model
will result in a timing inaccuracy due to double counting. Likewise for
Vinh/Vinl.

Thanks,
Vinu

Tom Dagostino wrote:

> The switching point for a differential input happens when the difference
in
> the input voltage reaches the Vdiff value.  In this case the common mode
> voltage is 1.2 Volts and the inputs need to be at least 100 mV different
to
> cause the input to recognize state.  Thus 1.15 and 1.25 volts would be the
> appropriate Vinl/Vinh values.
>
> Tom Dagostino
> Device Modeling Division
> Teraspeed Consulting Group LLC
> 2926 SE Yamhill St.
> Portland, OR 97214
> (503) 430-1065
> [email-masked]
> http://www.teraspeed.com
>
> -----Original Message-----
> From: [email-masked]
> [mailto:[email-masked]]On Behalf Of Vinu Arumugham
> Sent: Friday, December 06, 2002 9:30 AM
> To: Timothy Coyle
> Cc: [email-masked]
> Subject: Re: [IBIS-Users] Vinh for Differential Part
>
> Since these threshold voltages are used for timing measurements and since
> datasheets specify timing at the zero crossing or Vddq/2 level, would it
not
> be better to set Vdiff=0, Vinl=Vinh=1.2V?
>
> Thanks,
> Vinu
>
> Timothy Coyle wrote:
>
> > Hello,
> > I have a differential device in an IBIS file.  I define a Vdiff of 100mV
> > for my differential signal thresholds. However, I also have to define a
> > Vinh and Vinl
> > for the single-ended positive and negative differential Input model
types
> > in IBIS. The IBIS spec (3.2) states that:
> >
> > If a pin is a differential input pin, the differential input
> > | threshold (vdiff) overrides and supersedes the need for Vinh
> > | and Vinl.
> >
> > However, if I do not define a Vinh and Vinl for my differential inputs,
> > then the IBIS parser gives me a warning.  It also seems that some
> > simulators use this
> > Vinh and Vinl for the single-ended differential signals. If this is an
> LVDS
> > input, switching from 1 to 1.4 V, then I could put thresholds of 1.1 and
> > 1.3?
> >
> > I'm curious as to what other people do and why the parser gives me this
> > warning?
> >
> > Regards,
> > Tim
> >
> > |------------------------------------------------------------------
> > |For help or to subscribe/unsubscribe, email [email-masked]
> > |with just the appropriate command message(s) in the body:
> > |
> > |  help
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> > |
> > |or email a written request to [email-masked].
> > |
> > |IBIS reflector archives exist under:
> > |
> > |  http://www.eda.org/pub/ibis/email_archive/  Recent
> > |  http://www.eda.org/pub/ibis/users_archive/  Recent
> > |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
>
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> |
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> |
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------------------------------

Date: Fri, 6 Dec 2002 13:43:32 -0800
From: "Tom Dagostino" <[email-masked]>
Subject: RE: [IBIS-Users] Multiple package models

Since each different package style will have a unique component name use
three different components with 3 different pin tables.  Each model
referenced in the 3 pin tables should reference the common model statements.

Tom Dagostino
Device Modeling Division
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 430-1065
[email-masked]
http://www.teraspeed.com

- -----Original Message-----
From: [email-masked]
[mailto:[email-masked]]On Behalf Of ruston, matt
Sent: Friday, December 06, 2002 12:35 PM
To: [email-masked]
Subject: [IBIS-Users] Multiple package models

All:

 Hi. What is the best way to embed several different package models into the
same IBIS file? Say I have an FPGA with 3 different possible packages. I
have min, typ, max RLC values for each. Is there a way to select packages on
the fly (like a [Model_selector] keyword)?

 I see the syntax for several different parameters dealing with packages in
the Ibis 3.2 spec, but it is unclear as to what they are actually USED for
or how to use them.

I appreciate the help.

Regards,

Matt
|------------------------------------------------------------------
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------------------------------

Date: Fri, 06 Dec 2002 13:46:53 -0800
From: Fred Balistreri <[email-masked]>
Subject: Re: [IBIS-Users] Vinh for Differential Part

Why not use Vmeas or Vinh, Vinl which would be more accurate. I think
Tom is right on this one.

Best Regards,

Tom Dagostino wrote:
> 
> The problem with setting Vdiff to 0 is slow slew rates or poor transitions
> will not give accurate timing.  All of the datasheets that I checked had a
> limitation on the maximum transition time (between 1 and 5 nsec) for the
> Vdiff = 0 timing.
> 
> Tom Dagostino
> Device Modeling Division
> Teraspeed Consulting Group LLC
> 2926 SE Yamhill St.
> Portland, OR 97214
> (503) 430-1065
> [email-masked]
> http://www.teraspeed.com
> 
> -----Original Message-----
> From: [email-masked] [mailto:[email-masked]]
> Sent: Friday, December 06, 2002 12:40 PM
> To: [email-masked]
> Cc: 'Timothy Coyle'; [email-masked]
> Subject: Re: [IBIS-Users] Vinh for Differential Part
> 
> The device might switch when the differential inputs are 100mV apart.
> However,
> if the datasheet timing reference point is the zero crossing, Vdiff should
> be
> set to 0 in the IBIS model and the simulator should use this Vdiff value to
> report timing. Setting a different Vdiff value like 100mV in the IBIS model
> will result in a timing inaccuracy due to double counting. Likewise for
> Vinh/Vinl.
> 
> Thanks,
> Vinu
> 
> Tom Dagostino wrote:
> 
> > The switching point for a differential input happens when the difference
> in
> > the input voltage reaches the Vdiff value.  In this case the common mode
> > voltage is 1.2 Volts and the inputs need to be at least 100 mV different
> to
> > cause the input to recognize state.  Thus 1.15 and 1.25 volts would be the
> > appropriate Vinl/Vinh values.
> >
> > Tom Dagostino
> > Device Modeling Division
> > Teraspeed Consulting Group LLC
> > 2926 SE Yamhill St.
> > Portland, OR 97214
> > (503) 430-1065
> > [email-masked]
> > http://www.teraspeed.com
> >
> > -----Original Message-----
> > From: [email-masked]
> > [mailto:[email-masked]]On Behalf Of Vinu Arumugham
> > Sent: Friday, December 06, 2002 9:30 AM
> > To: Timothy Coyle
> > Cc: [email-masked]
> > Subject: Re: [IBIS-Users] Vinh for Differential Part
> >
> > Since these threshold voltages are used for timing measurements and since
> > datasheets specify timing at the zero crossing or Vddq/2 level, would it
> not
> > be better to set Vdiff=0, Vinl=Vinh=1.2V?
> >
> > Thanks,
> > Vinu
> >
> > Timothy Coyle wrote:
> >
> > > Hello,
> > > I have a differential device in an IBIS file.  I define a Vdiff of 100mV
> > > for my differential signal thresholds. However, I also have to define a
> > > Vinh and Vinl
> > > for the single-ended positive and negative differential Input model
> types
> > > in IBIS. The IBIS spec (3.2) states that:
> > >
> > > If a pin is a differential input pin, the differential input
> > > | threshold (vdiff) overrides and supersedes the need for Vinh
> > > | and Vinl.
> > >
> > > However, if I do not define a Vinh and Vinl for my differential inputs,
> > > then the IBIS parser gives me a warning.  It also seems that some
> > > simulators use this
> > > Vinh and Vinl for the single-ended differential signals. If this is an
> > LVDS
> > > input, switching from 1 to 1.4 V, then I could put thresholds of 1.1 and
> > > 1.3?
> > >
> > > I'm curious as to what other people do and why the parser gives me this
> > > warning?
> > >
> > > Regards,
> > > Tim
> > >
> > > |------------------------------------------------------------------
> > > |For help or to subscribe/unsubscribe, email [email-masked]
> > > |with just the appropriate command message(s) in the body:
> > > |
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> > > |
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> > > |
> > > |  http://www.eda.org/pub/ibis/email_archive/  Recent
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> > > |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
> >
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> 
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- -- 
Fred Balistreri
[email-masked]

http://www.apsimtech.com
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------------------------------

Date: Fri, 6 Dec 2002 14:19:53 -0800
From: "Muranyi, Arpad" <[email-masked]>
Subject: RE: [IBIS-Users] FW: 

Eric,

Answers to your questions:

1) We do it all the time.
2) The HSPICE B-element includes the C_comp, so you don't need to
add that to your circuit.  The rest are not included in the B-element,
so you will need to add those around it.

Arpad
=====================================================================

- -----Original Message-----
From: Eric Hsu [mailto:[email-masked]]
Sent: Friday, December 06, 2002 1:40 PM
To: [email-masked]
Subject: [IBIS-Users] FW: 

Hi All,

Is there anyone ever take IBIS mode and spice netlist and use hspice to
simulate on the same environment? I wonder maybe it is the best way to cross
verify correlation between IBIS model and spice netlist. If it is possible,
how can I handle R_pin, L_pin, C_pin, and C_comp those parameter  in the
ibis model? I mean should I add them into my test bench or not?

Best Regard,

Eric Hsu

Senior Design Engineer of Interface Technology
NetLogic Microsystems, Inc.
[email-masked]
650-961-6676 X198

 -----Original Message-----
From: 	Eric Hsu [mailto:[email-masked]]
Sent:	Friday, December 06, 2002 11:44 AM
To:	[email-masked]'; Arpad Muranyi (E-mail)
Subject:

Hi all and Arpad,

Could you please share your experience about verification spice and ibis
performance correlation? I found on page 8 of the article "I/O-buffer
modeling spec simplifies simulation for high-speed systems"
(http://www.eigroup.org/ibis/intel.htm), there is a figure mention about
spice and ibis waveform comparison. Do you think it was simulated by the
same tool? If it was, what's tool you used here? Or is anyone know what's
the tool I can use? How about like Hyperlynx, Quad Design, or
Interconnectix?

Best Regard,

Eric Hsu

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------------------------------

Date: Fri, 6 Dec 2002 13:16:48 -0800
From: "Muranyi, Arpad" <[email-masked]>
Subject: [IBIS-Users] RE: IBIS correlation to SPICE

Eric,

To be honest with you, I do not remember which tools were used
to generate the figure in the article you are referencing in the
link in your message.  (That article was written quite a long time
ago, in 1994).

There are many ways of correlating your IBIS models with the
original SPICE.  Most tools have features to save their waveforms
in ASCII format, and you can import these ASCII files into the
other tool's waveform viewer, or if nothing else, a spreadsheet
program, such as EXCEL.  Some tools can even import other tool's
formats.

However, if you have HSPICE, you can do the correlation from within
HSPICE, because it has direct IBIS model support with its B-element.
You can get a taste for this if you go to:

http://www.eda.org/pub/ibis/training/

and download the IBIS_class_JEDEC.zip file in which I have a
"compare.sp" file that does just this.

Have fun,

Arpad
=================================================================

- -----Original Message-----
From: Eric Hsu [mailto:[email-masked]]
Sent: Friday, December 06, 2002 11:44 AM
To: [email-masked]; Muranyi, Arpad
Subject: [IBIS-Users] Date: Fri, 6 Dec 2002 11:44:28 -0800

Hi all and Arpad,

Could you please share your experience about verification spice and ibis
performance correlation? I found on page 8 of the article "I/O-buffer
modeling spec simplifies simulation for high-speed systems"
(http://www.eigroup.org/ibis/intel.htm), there is a figure mention about
spice and ibis waveform comparison. Do you think it was simulated by the
same tool? If it was, what's tool you used here? Or is anyone know what's
the tool I can use? How about like Hyperlynx, Quad Design, or
Interconnectix?

Best Regard,

Eric Hsu

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------------------------------

Date: Fri, 06 Dec 2002 15:19:26 -0800
From: Vinu Arumugham <[email-masked]>
Subject: Re: [IBIS-Users] Vinh for Differential Part

Tom is correct that datasheets that spec. Vdiff=0 timing reference also specify a
transition rate. If the simulation shows slow slew rates or poor transitions that
violate the datasheet requirement, then the datasheet receiver input timings are
no longer valid. The receiver manufacturer has to provide timing derating
information.

So, it is not clear to me how setting Vdiff to non-zero value or using Vinh not
equal to Vinl will help in this situation.

Thanks,
Vinu

Fred Balistreri wrote:

> Why not use Vmeas or Vinh, Vinl which would be more accurate. I think
> Tom is right on this one.
>
> Best Regards,
>
> Tom Dagostino wrote:
> >
> > The problem with setting Vdiff to 0 is slow slew rates or poor transitions
> > will not give accurate timing.  All of the datasheets that I checked had a
> > limitation on the maximum transition time (between 1 and 5 nsec) for the
> > Vdiff = 0 timing.
> >
> > Tom Dagostino
> > Device Modeling Division
> > Teraspeed Consulting Group LLC
> > 2926 SE Yamhill St.
> > Portland, OR 97214
> > (503) 430-1065
> > [email-masked]
> > http://www.teraspeed.com
> >
> > -----Original Message-----
> > From: [email-masked] [mailto:[email-masked]]
> > Sent: Friday, December 06, 2002 12:40 PM
> > To: [email-masked]
> > Cc: 'Timothy Coyle'; [email-masked]
> > Subject: Re: [IBIS-Users] Vinh for Differential Part
> >
> > The device might switch when the differential inputs are 100mV apart.
> > However,
> > if the datasheet timing reference point is the zero crossing, Vdiff should
> > be
> > set to 0 in the IBIS model and the simulator should use this Vdiff value to
> > report timing. Setting a different Vdiff value like 100mV in the IBIS model
> > will result in a timing inaccuracy due to double counting. Likewise for
> > Vinh/Vinl.
> >
> > Thanks,
> > Vinu
> >
> > Tom Dagostino wrote:
> >
> > > The switching point for a differential input happens when the difference
> > in
> > > the input voltage reaches the Vdiff value.  In this case the common mode
> > > voltage is 1.2 Volts and the inputs need to be at least 100 mV different
> > to
> > > cause the input to recognize state.  Thus 1.15 and 1.25 volts would be the
> > > appropriate Vinl/Vinh values.
> > >
> > > Tom Dagostino
> > > Device Modeling Division
> > > Teraspeed Consulting Group LLC
> > > 2926 SE Yamhill St.
> > > Portland, OR 97214
> > > (503) 430-1065
> > > [email-masked]
> > > http://www.teraspeed.com
> > >
> > > -----Original Message-----
> > > From: [email-masked]
> > > [mailto:[email-masked]]On Behalf Of Vinu Arumugham
> > > Sent: Friday, December 06, 2002 9:30 AM
> > > To: Timothy Coyle
> > > Cc: [email-masked]
> > > Subject: Re: [IBIS-Users] Vinh for Differential Part
> > >
> > > Since these threshold voltages are used for timing measurements and since
> > > datasheets specify timing at the zero crossing or Vddq/2 level, would it
> > not
> > > be better to set Vdiff=0, Vinl=Vinh=1.2V?
> > >
> > > Thanks,
> > > Vinu
> > >
> > > Timothy Coyle wrote:
> > >
> > > > Hello,
> > > > I have a differential device in an IBIS file.  I define a Vdiff of 100mV
> > > > for my differential signal thresholds. However, I also have to define a
> > > > Vinh and Vinl
> > > > for the single-ended positive and negative differential Input model
> > types
> > > > in IBIS. The IBIS spec (3.2) states that:
> > > >
> > > > If a pin is a differential input pin, the differential input
> > > > | threshold (vdiff) overrides and supersedes the need for Vinh
> > > > | and Vinl.
> > > >
> > > > However, if I do not define a Vinh and Vinl for my differential inputs,
> > > > then the IBIS parser gives me a warning.  It also seems that some
> > > > simulators use this
> > > > Vinh and Vinl for the single-ended differential signals. If this is an
> > > LVDS
> > > > input, switching from 1 to 1.4 V, then I could put thresholds of 1.1 and
> > > > 1.3?
> > > >
> > > > I'm curious as to what other people do and why the parser gives me this
> > > > warning?
> > > >
> > > > Regards,
> > > > Tim
> > > >
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> >
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>
> --
> Fred Balistreri
> [email-masked]
>
> http://www.apsimtech.com

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------------------------------

Date: Fri, 6 Dec 2002 19:52:37 -0500
From: "Lynne Green" <[email-masked]>
Subject: [IBIS-Users] Second Call for Papers for IBIS DesignCon Summit

- -----------------------------------------------------------------------
		IBIS SUMMIT
		SECOND CALL FOR
	PARTICIPATION & PRESENTATIONS
- -----------------------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

              I B I S   S U M M I T   M E E T I N G

Time/Date:      Monday January 27, 2003,  8:00 AM to 5:00 PM

Location:   Magnolia Room 
                Santa Clara Convention Center
                Santa Clara, CA

Content:       Presentations and Discussions

Purpose:       Solicit and Exchange IBIS Model Related Information and
Ideas.

Sponsors:     DesignCon, National Semiconductor

DesignCon: January 27-30, 2003
		Santa Clara Convention Center
		Santa Clara, California
		See <http://www.designcon.com/2003/> for more
information.

BACKGROUND

DesignCon is the premier annual Silicon Valley event for the electronic
design automation (EDA) and semiconductor industry.  Topics of current
interest to the EIA IBIS Open Forum are addressed at DesignCon.

This meeting will be conducted as a formal IBIS Summit Meeting.
Presentation are expected to be available and archived in an electronic
format, and minutes of the meeting will be issued.  Any pending formal
decisions (votes) will be announced at least two weeks prior to the
meeting.

CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development, and
digital circuit design are invited to participate to the Summit meeting.
If you plan to participate, please register with the information below:

   Name:
   E-mail address:
   Company:
   Telephone:

Send to:

    Milt Swartz at National Semiconductor ([email-masked])

CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS experiences
or issues.

Format of Presentation:  Overhead Projections.
			LCD Projection may be available.  It is
recommended
			that those wishing to use LCD projection bring
their
			presentation on a CD or send it electronically.
Time:			15-30 Minutes
Electronic Archival:	We request electronic versions so that the
			presentations can be archived and also made
			available to non-attendees.  Formats used in
			the past have been text, Power Point, Word,
			Postscript, and Acrobat.  Electronic
presentations
			should be made available by January 22, 2003
			for uploading and copying.

If you plan a presentation, please supply

   Title:
   Presenter:
   E-mail address:
   Company:
   Telephone:

   Estimate Time:

Send this to:

  Lynne Green ([email-masked])

AGENDA

The agenda includes presentations, discussions, breaks, and a luncheon
(which will be provided).  This will be developed as presentation
proposals are received.

The following individuals have signed up to present at the summit
(presentation titles are tentative)
 - Stephen Peters, IBIS Report
 - Dima Smolysansky, TDA Systems, TBD
 - Barry Katz, Signal Integrity Software, Quality Committee Report

Other presentations are encouraged.

LIST OF NEARBY HOTELS

See <http://www.designcon.com/2003/hotel.html> for travel directions,
hotels and other information.
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------------------------------

Date: Sun, 8 Dec 2002 21:42:21 -0500 (EST)
From: "Robert Haller" <[email-masked]>
Subject: Re: [IBIS-Users] FW:

Eric,
   This can easily be done (as Arpad pointed out) utilizing the B-element
in Hspice. You can obtain excellent correlation (in the same
environment) betweem IBIS models and HSPICE native models. The 2 keys
are Accurate IBIS models and identical conditions.

 Hspice will read all the information in an IBIS model including
R,L,C_pin, C_comp (when you make a B-elemenet Call). Some vendors provide
extensions to the simple R L C models in IBIS  because todays high
performance packages are better modeled as transmission lines.

Bob Haller
www.sisoft.com

> Hi All,
>
> Is there anyone ever take IBIS mode and spice netlist and use hspice to
> simulate on the same environment? I wonder maybe it is the best way to
> cross verify correlation between IBIS model and spice netlist. If it is
> possible, how can I handle R_pin, L_pin, C_pin, and C_comp those
> parameter  in the ibis model? I mean should I add them into my test
> bench or not?
>
> Best Regard,
>
> Eric Hsu
>
> Senior Design Engineer of Interface Technology
> NetLogic Microsystems, Inc.
> [email-masked]
> 650-961-6676 X198
>
>
>
>  -----Original Message-----
> From: 	Eric Hsu [mailto:[email-masked]]
> Sent:	Friday, December 06, 2002 11:44 AM
> To:	[email-masked]'; Arpad Muranyi (E-mail)
> Subject:
>
> Hi all and Arpad,
>
> Could you please share your experience about verification spice and ibis
> performance correlation? I found on page 8 of the article "I/O-buffer
> modeling spec simplifies simulation for high-speed systems"
> (http://www.eigroup.org/ibis/intel.htm), there is a figure mention about
> spice and ibis waveform comparison. Do you think it was simulated by the
> same tool? If it was, what's tool you used here? Or is anyone know
> what's the tool I can use? How about like Hyperlynx, Quad Design, or
> Interconnectix?
>
> Best Regard,
>
> Eric Hsu
>
>
>
>
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- -- 
Robert Haller ([email-masked])
Signal Integrity Software Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
Phone: (978) 461-0449, ext 15

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------------------------------

Date: Mon, 09 Dec 2002 08:33:01 -0800
From: bpanos <[email-masked]>
Subject: [IBIS-Users] ibis models

This is a multi-part message in MIME format.
- --------------9013FCB38F97C9E75D07EA29
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Maybe I'm missing something, but an ibis model cannot act like a spice
equivalent in so far as setting multiple inputs and outputs and seeing
how the device operates, is this correct? As An example, I have a model
for a PLL device and I wanted introduce a clock in and look the clock
out, as a function of the feedback (frequency lock) circuit, which is
critical in getting the PLL to operate correctly
Is the ibis model of the device made where the PLL is already at some
range of operation with a feedback circuit in place?
Any feedback appreciated....

Thanks
Bill

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------------------------------

Date: Tue, 10 Dec 2002 18:50:34 +0200
From: Dan Aleksandrowicz <[email-masked]>
Subject: [IBIS-Users] Using s2ibis2 in 1.65V range

- --------------63AEACE4193CFA52CAFCC7B0
Content-Type: text/plain; charset=
Content-Transfer-Encoding: base64

Hi there.

I have a problem generating a an IBIS model while using 1.65V supply.

The problem is that I get different ranges from the [Pulldown] Vs.
[Pullup]
tables - 3.3->1.6 and 3.25->-1.65 receptively.

Does anyone have a solution ?

Thanks

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Hi there.
<p>I have a problem generating a an IBIS model while using 1.65V supply.
<p>The problem is that I get different ranges from the [Pulldown] Vs. [Pullup]
<br>tables - 3.3->1.6 and 3.25->-1.65 receptively.
<p>Does anyone have a solution ?
<p>Thanks
<pre>--&nbsp;
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------------------------------

Date: Tue, 10 Dec 2002 11:38:18 -0800
From: "Angulo, John" <[email-masked]>
Subject: [IBIS-Users] Repost: Using s2ibis2 in 1.65V range

The following is posted on behalf of Dan Aleksandrowicz at Galileo Technology.  Please send any private replies to [email-masked] only.

John Angulo
IBIS Open Forum Postmaster

- --------------------------------------

Hi there.

I have a problem generating a an IBIS model while using 1.65V supply.

The problem is that I get different ranges from the [Pulldown] Vs.
[Pullup]
tables - 3.3->1.6 and 3.25->-1.65 receptively.

Does anyone have a solution ?

Thanks

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------------------------------

Date: Tue, 10 Dec 2002 12:02:00 -0800
From: "Angulo, John" <[email-masked]>
Subject: [IBIS-Users] Re: Using s2ibis2 in 1.65V range

The following is posted on behalf of Hazem Hegazy at QualiM.  Please send any private replies to [email-masked] only.

- -------------------------------------

Hi,

For a 1.65 supply buffer:

- -          Pulldown range will be -1.65 to 3.3 V.

- -          Pullup range from -1.65 to 3.3 also in case of the typical corner.

 

Both ranges will be swept with 0.05 V step if you want to get the maximum number of point allowed (Maximum accuracy).

So, I think the 3.25 V in the pull up that you are talking about came from ignoring the last step in the pull up sweep.

BR,

Hazem Hegazy, M.Sc.

IBIS Modeling Engineer

QualiM

http://www.qualim.com/

Phone: (+20) 106052154

E-mail: [email-masked]
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------------------------------

Date: Tue, 10 Dec 2002 15:37:01 -0500
From: "Mike LaBonte" <[email-masked]>
Subject: RE: [IBIS-Users] Using s2ibis2 in 1.65V range

This is a multi-part message in MIME format.

- ------=_NextPart_000_0019_01C2A061.FB8D5290
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Unfortunately s2ibis2 doesn't work at that voltage range due to some bugs. A
terrible hack is
to reduce the value of DIODE_DROP_DEFAULT in s2idflt.h to something like
0.3V, then recompile.
The right solution is to replace the offending function, sortVIData in
s2ianlyz.c.

Mike
  -----Original Message-----
  From: [email-masked] [mailto:[email-masked]]On Behalf
Of Dan Aleksandrowicz
  Sent: Tuesday, December 10, 2002 11:51 AM
  To: [email-masked]
  Subject: [IBIS-Users] Using s2ibis2 in 1.65V range

  Hi there.
  I have a problem generating a an IBIS model while using 1.65V supply.

  The problem is that I get different ranges from the [Pulldown] Vs.
[Pullup]
  tables - 3.3->1.6 and 3.25->-1.65 receptively.

  Does anyone have a solution ?

  Thanks

- --
"This message may contain confidential, proprietary or legally privileged
 information. The information is intended only for the use of the individual
 or entity named above. If the reader of this message is not the intended
 recipient, you are hereby notified that any dissemination, distribution
 or copying of this communication is strictly prohibited. If you have
 received this communication in error, please notify us immediately by
 telephone, or by e-mail and delete the message from your computer.".

- ------=_NextPart_000_0019_01C2A061.FB8D5290
Content-Type: text/html;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2800.1106" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D081172720-10122002><FONT face=3DArial color=3D#0000ff =

size=3D2>Unfortunately s2ibis2 doesn't work at that voltage range due to =
some=20
bugs. A terrible hack is</FONT></SPAN></DIV>
<DIV><SPAN class=3D081172720-10122002><FONT face=3DArial color=3D#0000ff =
size=3D2>to=20
reduce the value of DIODE_DROP_DEFAULT in s2idflt.h to something like =
0.3V, then=20
recompile.</FONT></SPAN></DIV>
<DIV><SPAN class=3D081172720-10122002><FONT face=3DArial color=3D#0000ff =
size=3D2>The=20
right solution is to&nbsp;replace the offending function, sortVIData in=20
s2ianlyz.c.</FONT></SPAN></DIV>
<DIV><SPAN class=3D081172720-10122002><FONT face=3DArial color=3D#0000ff =

size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D081172720-10122002><FONT face=3DArial color=3D#0000ff =

size=3D2>Mike</FONT></SPAN></DIV>
<BLOCKQUOTE>
  <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B> =
[email-masked]=20
  [mailto:[email-masked]]<B>On Behalf Of </B>Dan=20
  Aleksandrowicz<BR><B>Sent:</B> Tuesday, December 10, 2002 11:51=20
  AM<BR><B>To:</B> [email-masked]<BR><B>Subject:</B> [IBIS-Users] =
Using=20
  s2ibis2 in 1.65V range<BR><BR></FONT></DIV>Hi there.=20
  <P>I have a problem generating a an IBIS model while using 1.65V =
supply.=20
  <P>The problem is that I get different ranges from the [Pulldown] Vs. =
[Pullup]=20
  <BR>tables - 3.3-&gt;1.6 and 3.25-&gt;-1.65 receptively.=20
  <P>Does anyone have a solution ?=20
  <P>Thanks <PRE>--&nbsp;
"This message may contain confidential, proprietary or legally =
privileged&nbsp;
&nbsp;information. The information is intended only for the use of the =
individual&nbsp;
&nbsp;or entity named above. If the reader of this message is not the =
intended&nbsp;
&nbsp;recipient, you are hereby notified that any dissemination, =
distribution&nbsp;
&nbsp;or copying of this communication is strictly prohibited. If you =
have&nbsp;
&nbsp;received this communication in error, please notify us immediately =
by&nbsp;
&nbsp;telephone, or by e-mail and delete the message from your =
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</BLOCKQUOTE></BODY></HTML>

- ------=_NextPart_000_0019_01C2A061.FB8D5290--

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------------------------------

Date: Tue, 10 Dec 2002 18:12:18 -0800 (PST)
From: Syed Huq <[email-masked]>
Subject: RE: [IBIS-Users] Using s2ibis2 in 1.65V range

How about this:

For the Pullup:
3.3
.
.
1.6
1.65  <-- add this line and extrapolate from 1.6 to 1.65

For the Pulldown:
3.3   <--  add this line and extrapolate from 3.25 to 3.3
3.25
.
.
.
1.65

and now you have the full range..
Syed

>  -----Original Message-----
>  From: [email-masked] [mailto:[email-masked]]On 
Behalf
>Of Dan Aleksandrowicz
>  Sent: Tuesday, December 10, 2002 11:51 AM
>  To: [email-masked]
>  Subject: [IBIS-Users] Using s2ibis2 in 1.65V range
>
>
>  Hi there.
>  I have a problem generating a an IBIS model while using 1.65V supply.
>
>  The problem is that I get different ranges from the [Pulldown] Vs.
>[Pullup]
>  tables - 3.3->1.6 and 3.25->-1.65 receptively.
>
>  Does anyone have a solution ?
>
>  Thanks
>
>--
>"This message may contain confidential, proprietary or legally privileged
> information. The information is intended only for the use of the 
individual
> or entity named above. If the reader of this message is not the intended
> recipient, you are hereby notified that any dissemination, distribution
> or copying of this communication is strictly prohibited. If you have
> received this communication in error, please notify us immediately by
> telephone, or by e-mail and delete the message from your computer.".

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------------------------------

Date: Thu, 19 Dec 2002 21:15:08 +0100
From: "Hans Klos" <[email-masked]>
Subject: [IBIS-Users] IBIS Development studio

Hello ibis users,

We recently developed a tool called IBIS development studio.

With IBIS development studio it is possible to :
- - check ibis models
- - modify IBIS waveforms graphically
- - create you own model with a whizard
- - import buffer models from other ibis models
- - write out the model in a xml format.

Possible add-ons are now developed.
If you have any questions, feel free to send it to us.

On our web page, you can find more information regarding IBIS development studio.

Best Regards,

Edality BV, EDA software development and distribution
The Netherlands
http://www.Edality.com
mailto:[email-masked]
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------------------------------

Date: Thu, 19 Dec 2002 14:01:48 -0800
From: "Angulo, John" <[email-masked]>
Subject: RE: [IBIS-Users] IBIS Development studio

Is this tool available for free?  If so, great!  If not, remember that EIA rules require no commercial product discussion on the IBIS mailing lists.

Best regards,

John Angulo
IBIS Open Forum Postmaster

- -----Original Message-----
From: Hans Klos [mailto:[email-masked]]
Sent: Thursday, December 19, 2002 12:15 PM
To: ibis-users
Subject: [IBIS-Users] IBIS Development studio

Hello ibis users,

We recently developed a tool called IBIS development studio.

With IBIS development studio it is possible to :
- - check ibis models
- - modify IBIS waveforms graphically
- - create you own model with a whizard
- - import buffer models from other ibis models
- - write out the model in a xml format.

Possible add-ons are now developed.
If you have any questions, feel free to send it to us.

On our web page, you can find more information regarding IBIS development studio.

Best Regards,

Edality BV, EDA software development and distribution
The Netherlands
http://www.Edality.com
mailto:[email-masked]
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------------------------------

Date: Thu, 19 Dec 2002 17:19:55 -0800
From: [email-masked]
Subject: [IBIS-Users] s2ibis2.solaris

Question 1 (VT curves)
Can anyone tell me how to configure the .s2i file to automatically add pwl
stimulus for rising and falling waveforms?
The example shows:
[Rising waveform] 500 0 NA NA NA NA NA NA NA
[Falling waveform] 500 3.3 NA NA NA NA NA NA NA
My results have Rising Waveform voltages of all 0.000V and Falling Waveform
voltages of all 3.30V.

Question 2  (VI curves)
Again in the .s2i file under [model file]  the example shows:
[Model file] spectre.mod spectre.mod spectre.mod
This file contains Nominal, Slow and Fast parameters.  But my .ibs data
only shows I(typ).    It shows  NA for I(min) and I(max).
How do I get it to show the I min and max data?

Thanks for any help
Garry Felker

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------------------------------

Date: Thu, 19 Dec 2002 18:36:07 -0800 (PST)
From: Syed Huq <[email-masked]>
Subject: Re: [IBIS-Users] s2ibis2.solaris

For Ques#1:

You should have:
[Rising waveform] 500 0.0 0.0 0.0 NA NA NA NA NA
[Falling waveform] 500 3.3 3.0 3.6 NA NA NA NA NA

by looking at the a*.spi, b*.spi, c*.spi, you should see the PULSE
statement. Looks like your buffer did not switch. So there are other
problems.

For Ques#2:
[Model file] typ.mod slow.mod fast.mod

Each of the above contains the respective process files. Then you
should each all the columms. That is if the simulation ran correctly.

You can always look at, for example pdn*.out (pulldown min)and look
at the SPICE generat

Syed

>From: [email-masked]
>Subject: [IBIS-Users] s2ibis2.solaris
>To: [email-masked]
>Date: Thu, 19 Dec 2002 17:19:55 -0800
>X-MIMETrack: Serialize by Router on NPBSMTP1/Server/Conexant(Release 5.0.11  
|July 24, 2002) at 12/19/2002 05:19:57 PM
>MIME-Version: 1.0
>
>Question 1 (VT curves)
>Can anyone tell me how to configure the .s2i file to automatically add pwl
>stimulus for rising and falling waveforms?
>The example shows:
>[Rising waveform] 500 0 NA NA NA NA NA NA NA
>[Falling waveform] 500 3.3 NA NA NA NA NA NA NA
>My results have Rising Waveform voltages of all 0.000V and Falling Waveform
>voltages of all 3.30V.
>
>Question 2  (VI curves)
>Again in the .s2i file under [model file]  the example shows:
>[Model file] spectre.mod spectre.mod spectre.mod
>This file contains Nominal, Slow and Fast parameters.  But my .ibs data
>only shows I(typ).    It shows  NA for I(min) and I(max).
>How do I get it to show the I min and max data?
>
>Thanks for any help
>Garry Felker
>
>
>
>
>
>
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------------------------------

Date: Fri, 20 Dec 2002 10:43:16 +0530 (IST)
From: Suresh C <[email-masked]>
Subject: [IBIS-Users] IBIS Models for bidi I/O

Hi,

This is Suresh here. I'm new to IBIS modeling. I would
apprecitate if anyone could guide me for generating models for
bidirectional IO's with pullup.

Any documents/links would be helpful.

Thanks and Regards,
Suresh

===================================================================
Suresh C				Ph: 91-80-5099437
MSP India Tactical Cells Team
Texas Instruments, India
- --------------------------------------------------------------------
"All experience is an arch wherethrough gleams that untraveled world,
whose margin fades for ever and for ever when I move"
===================================================================

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------------------------------

End of ibis-users V1 #13
************************