Subject: ibis-users V1 #29
From: owner-ibis-users@ (ibis-users)
To: [email-masked]

ibis-users           Monday, August 25 2003           Volume 01 : Number 029

----------------------------------------------------------------------

Date: Mon, 18 Aug 2003 09:55:41 +0200
From: [email-masked]
Subject: [IBIS-Users] time shifted edges

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- --=_alternative 002BC524C1256D86_=
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Dear IBIS colleagues,

I am trying to model a differential LVDS output buffer.
I have generated waveform tables from Spectre simulations. The falling and 
rising waveforms look fine at first glance.
In Spectre the falling and rising waveforms (of both outputs, which are 
equal) have a crossing point about in the middle of the DC level (high and 
low state).
When I simulate my model with Hyperlynx I see that the crossing point is 
at a very low level, because of a time shift of the edges. I simulate with 
an Rfix (50 Ohm) to a Vfix which is 
in the middle of the DC levels.

So my question is:
How does a simulator determine where the edges start? Do different 
simulators use the same algorithm for this?
What can I do to get crossing point in the right place? (or: how do I 
control the place (in time) of the edges?).

Can anyone help me? Thanks in advance.

With kind regards,

Ir. Erik van der Ven
Room DB1032
Business Line Networking Infrastructure
Philips Semiconductors BV
Gerstweg 2
6534 AE Nijmegen
The Netherlands
Phone: +31-24-3534334
- --=_alternative 002BC524C1256D86_=
Content-Type: text/html; charset="us-ascii"

<br><font size=2 face="sans-serif">Dear IBIS colleagues,</font>
<br>
<br><font size=2 face="sans-serif">I am trying to model a differential LVDS output buffer.</font>
<br><font size=2 face="sans-serif">I have generated waveform tables from Spectre simulations. The falling and rising waveforms look fine at first glance.</font>
<br><font size=2 face="sans-serif">In Spectre the falling and rising waveforms (of both outputs, which are equal) have a crossing point about in the middle of the DC level (high and low state).</font>
<br><font size=2 face="sans-serif">When I simulate my model with Hyperlynx I see that the crossing point is at a very low level, because of a time shift of the edges. I simulate with an Rfix (50 Ohm) to a Vfix which is </font>
<br><font size=2 face="sans-serif">in the middle of the DC levels.</font>
<br>
<br><font size=2 face="sans-serif">So my question is:</font>
<br><font size=2 face="sans-serif">How does a simulator determine where the edges start? Do different simulators use the same algorithm for this?</font>
<br><font size=2 face="sans-serif">What can I do to get crossing point in the right place? (or: how do I control the place (in time) of the edges?).</font>
<br>
<br><font size=2 face="sans-serif">Can anyone help me? Thanks in advance.</font>
<br>
<br><font size=2 face="sans-serif">With kind regards,</font>
<br><font size=2 face="sans-serif"><br>
Ir. Erik van der Ven<br>
Room DB1032<br>
Business Line Networking Infrastructure<br>
Philips Semiconductors BV<br>
Gerstweg 2<br>
6534 AE Nijmegen<br>
The Netherlands<br>
Phone: +31-24-3534334</font>
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------------------------------

Date: Mon, 18 Aug 2003 14:19:12 +0100 (BST)
From: =?iso-8859-1?q?SUDHEER?= <[email-masked]>
Subject: [IBIS-Users] ECL LVDS   model 

Hi All 
I  am simulating ECL LVDS  signals , i am finding it
difficult to understand  the ibis convention on LVDS

Which  parameter in differential  pair signals will
define the swing ? 
I have  seen some 5v device buffers  are paired
together (inv and noninv ) and Vdiff defined at 300 mv
I have not seen the volt swing definition in ibis file
!!

Can anybody suggest me the device  where in I can get
ECL(100k) LVDS   buffer Driver (IBIS)

Thanks In advance
SUDHEER

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------------------------------

Date: Mon, 18 Aug 2003 11:03:52 -0400
From: "Allen Chao" <[email-masked]>
Subject: RE: [IBIS-Users]DC Sweep for the pullup IV curve

Hi Arpad,
Thanks for your fast reply... I just consulted further with the buffer
designer here. He said that this output is a high-speed data output and
instead of using Vcc (power-supply voltage) for the power clamp diode and
the pull-up transistor, we use a current source to drive the output to 0.4v
for signal high and simply turn off the transistors between current source
and the output for the low signal. (since the output is also connected to
another resistor and ground, the output will be grounded for the low
signal). As I described, there are not really pullup/pulldown transistors
and clamping devices.
My question is, can we still create an IBIS model for this output?

Thanks in advance,

Allen Chao

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On
Behalf Of Muranyi, Arpad
Sent: Thursday, August 14, 2003 7:07 PM
To: [email-masked]
Subject: RE: [IBIS-Users]DC Sweep for the pullup IV curve

Allen,

Strictly speaking the spec says the following:

| The stated voltage ranges for I-V tables cover the most common, single
| supply cases.  When multiple supplies are specified, the voltages shall
| extend similarly to values that handle practical extremes in reflected
wave
| simulations.
|
...
| 2) Voltage Ranges:
|    Points for each table must span the voltages listed below:
|
|       Table                   Low Voltage             High Voltage
|       -----------             -----------             ------------
|       [Pulldown]              GND - POWER             POWER + POWER
|       [Pullup]                GND - POWER             POWER + POWER
|       [GND Clamp]             GND - POWER             GND + POWER
|       [POWER Clamp]           POWER                   POWER + POWER
|       [Series Current]        GND - POWER             GND + POWER
|       [Series MOSFET]         GND                     GND + POWER
|
|    As described in the [Pulldown Reference] keyword section, the I-V
tables
|    of the [Pullup] and the [POWER Clamp] structures are 'Vcc relative',
|    using the equation:  Vtable = Vcc - Voutput.
|
|    For example, a model with a 5 V power supply voltage should be
|    characterized between (0 - 5) = -5 V and (5 + 5) = 10 V; and a model
with
|    a 3.3 V power supply should be characterized between (0 - 3.3) = -3.3 V
|    and (3.3 + 3.3) = 6.6 V for the [Pulldown] table.
|
|    When tabulating output data for ECL type models, the voltage points
must
|    span the range of Vcc to Vcc - 2.2 V.  This range applies to both the
|    [Pullup] and [Pulldown] tables.  Note that this range applies ONLY when
|    characterizing an ECL output.
|
|    These voltage ranges must be spanned by the IBIS data.  Data derived
from
|    lab measurements may not be able to span these ranges as such and so
may
|    need to be extrapolated to cover the full range.  This data must not be
|    left for the simulator to provide.

So according to the spec you would need to do -3.3 to 6.6 V.  However,
this was written in the days when most buffers were switching rail to
rail, and most transmission lines were unterminated having a full
reflection.
The spec wanted to make sure that the IV curves would cover the voltage
range even if the waveforms double due to reflections.

Lately, the picture has changed, and we have more low voltage swing signals
and parallel terminated buses.  As a consequence buffers do not necessarily
switch rail to rail, and reflections are much smaller.  Even if we followed
the logic of full reflections, your model should be sufficient if it covered
- -0.4 to 0.8 V.  This would be officially not according to the spec, but
as far as I remember, the parser doesn't issue an error message, so you
should be OK.

I am dealing with similar situations in other cases too, and I am
actually considering writing a BIRD on this subject to clarify/change
the spec.

Arpad Muranyi
Intel Corporation
===========================================================================

- -----Original Message-----
From: Allen Chao [mailto:[email-masked]]
Sent: Thursday, August 14, 2003 12:51 PM
To: [email-masked]
Subject: [IBIS-Users]DC Sweep for the pullup IV curve

Hi IBIS experts,
I have a question concerning the sweep. I have a 3.3V power supply for my
device. However, the logic high voltage is 0.4V and logic low is 0V for my
one of my outputs. Do I do the DC Sweep at the output from -3.3V to 6.6V
or -0.4V to 0.8V?

Thanks a lot for the help,

Allen Chao

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------------------------------

Date: Mon, 18 Aug 2003 09:40:03 -0700
From: "Muranyi, Arpad" <[email-masked]>
Subject: RE: [IBIS-Users]DC Sweep for the pullup IV curve

Allen,

OK, there is no pulldown, because the external resistor pulls the
signal to aero volts.  But what is that "current source" made out
of?  The designs I have seen so far implement current sources with
transistors, except they are sized and biased in such a way that
their IV curve will look more like a current source.

What does a current source's IV curve look like?  By definition a
current source provides a constant current regardless of what the
voltage across its terminals is, i.e. the IV curve is a horizontal
line.  In theory this should extend to all voltages, however, in
real life (unless it is a specialized circuit design) it will be
polarized (i.e. work only for one voltage polarity, say positive).

So implementing a current source can be done by a huge transistor,
which has a very steep linear region (coming out of the origin),
and then using a fairly low bias voltage you can operate in its
saturation region, which looks like a constant current source.
Note, however, that this transistor is still connected to some
sort of a supply rail.

So regarding your buffer, I would guess that it has this kind of
a pullup transistor, and whether the designer wants to call it a
pullup or not is a different question.

Having said all this, you can make an IBIS model of this buffer
using the "open source" model type, which has a pullup, but no
pulldown IV curve.  Don't worry about it being a current source,
the shape of the IV curve will describe that very well.

Regarding clamps, I have a hard time to believe that the above
transistor doesn't have any parasitic diodes (unless it is not
MOSFET) and that there is absolutely no ESD protection in this
device.  It may be the case, but usually it is not.  So I would
expect that you would still see some currents outside the rails
when you 3-state the device for this reason.  These currents
will go into the IBIS clamp IV tables.

Arpad Muranyi
Intel Corporation
=================================================================

- -----Original Message-----
From: Allen Chao [mailto:[email-masked]]
Sent: Monday, August 18, 2003 8:04 AM
To: Muranyi, Arpad; [email-masked]
Subject: RE: [IBIS-Users]DC Sweep for the pullup IV curve

Hi Arpad,
Thanks for your fast reply... I just consulted further with the buffer
designer here. He said that this output is a high-speed data output and
instead of using Vcc (power-supply voltage) for the power clamp diode and
the pull-up transistor, we use a current source to drive the output to 0.4v
for signal high and simply turn off the transistors between current source
and the output for the low signal. (since the output is also connected to
another resistor and ground, the output will be grounded for the low
signal). As I described, there are not really pullup/pulldown transistors
and clamping devices.
My question is, can we still create an IBIS model for this output?

Thanks in advance,

Allen Chao
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------------------------------

Date: Mon, 18 Aug 2003 11:37:41 -0700
From: Jose G Corona <[email-masked]>
Subject: [IBIS-Users] Creating 3 sets of R/F Waveforms 

Hello IBIS-users,

I am trying to generate ibis model for SSTL, this IO has termination
resistor of 50 Ohm connected to VDD/2. While looking into many other
ibis models  from different providers, I have found that there are always
two termination voltages (0 and VDD or 0 and VDD/2).  I want to create
an ibis model with three termination voltages "0, vdd/2 and vdd". But
the tool (North Carolina Univ's tool) only generates the waveforms for
the first two but not the third.
Is it possible for UNC s2ibis2 to create 3 sets of R/F waveforms?
 Also, I am not sure whether it is ibis-complaint to have three 
termination voltage schemes?

In the s2i tech file , I have using following lines
- -----------------------------------------------------
rising_waveform1 = [Rising waveform] 50 0 NA NA NA NA NA NA NA
falling_waveform1 = [Falling waveform] 50 0 NA NA NA NA NA NA NA
rising_waveform2 = [Rising waveform] 50 1.25 NA NA NA NA NA NA NA
falling_waveform2 = [Falling waveform] 50 1.25 NA NA NA NA NA NA NA

rising_waveform3 = [Rising waveform] 50 2.5 NA NA NA NA NA NA NA
falling_waveform3 = [Falling waveform] 50 2.5 NA NA NA NA NA NA NA
- ----------------------------------------------------------

Thanks for your precious time and I will really appreciate your response.

- -Jose 

- -- 
Jose G. Corona
Analog/Mixed-Signal Business Unit
ARTISAN COMPONENTS, INC.
Tel:    (858) 731-3428
Fax:    (858) 457-5578

www.artisan.com

"Artisan: The IP Partner of Choice"
 
- --
This transmission is intended for the sole use of the individual and
entity to whom it is addressed, and may contain information that is
privileged, confidential and exempt from disclosure under applicable
law. You are hereby notified that any dissemination, distribution or
duplication of this transmission by someone other than the intended
addressee or its designated agent is strictly prohibited. If your
receipt of this transmission is in error, please notify this company
immediately by reply to this transmission and delete it from your
computer. Thank You. Artisan Components, Inc.

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------------------------------

Date: Mon, 18 Aug 2003 12:08:48 -0700
From: "Muranyi, Arpad" <[email-masked]>
Subject: RE: [IBIS-Users] Creating 3 sets of R/F Waveforms 

Jose,

You can make legal IBIS models with more than just two
V_fixture voltages.  IBIS allows you to put 100 waveform
tables in a [Model].

I do not know how to use s2ibis, but if it only takes the
first two values, than you can make two models so that 
the first model has value1 value2 and the second model
has value2 and value3.  Then you can just cut and paste
the table that was generated with value3 from the second
IBIS model into the first IBIS model and you are done.

Arpad
========================================================

- -----Original Message-----
From: Jose G Corona [mailto:[email-masked]]
Sent: Monday, August 18, 2003 11:38 AM
To: ibis-users
Subject: [IBIS-Users] Creating 3 sets of R/F Waveforms 

Hello IBIS-users,

I am trying to generate ibis model for SSTL, this IO has termination
resistor of 50 Ohm connected to VDD/2. While looking into many other
ibis models  from different providers, I have found that there are always
two termination voltages (0 and VDD or 0 and VDD/2).  I want to create
an ibis model with three termination voltages "0, vdd/2 and vdd". But
the tool (North Carolina Univ's tool) only generates the waveforms for
the first two but not the third.
Is it possible for UNC s2ibis2 to create 3 sets of R/F waveforms?
 Also, I am not sure whether it is ibis-complaint to have three 
termination voltage schemes?

In the s2i tech file , I have using following lines
- -----------------------------------------------------
rising_waveform1 = [Rising waveform] 50 0 NA NA NA NA NA NA NA
falling_waveform1 = [Falling waveform] 50 0 NA NA NA NA NA NA NA
rising_waveform2 = [Rising waveform] 50 1.25 NA NA NA NA NA NA NA
falling_waveform2 = [Falling waveform] 50 1.25 NA NA NA NA NA NA NA

rising_waveform3 = [Rising waveform] 50 2.5 NA NA NA NA NA NA NA
falling_waveform3 = [Falling waveform] 50 2.5 NA NA NA NA NA NA NA
- ----------------------------------------------------------

Thanks for your precious time and I will really appreciate your response.

- -Jose 

- -- 
Jose G. Corona
Analog/Mixed-Signal Business Unit
ARTISAN COMPONENTS, INC.
Tel:    (858) 731-3428
Fax:    (858) 457-5578

www.artisan.com

"Artisan: The IP Partner of Choice"
 
- --
This transmission is intended for the sole use of the individual and
entity to whom it is addressed, and may contain information that is
privileged, confidential and exempt from disclosure under applicable
law. You are hereby notified that any dissemination, distribution or
duplication of this transmission by someone other than the intended
addressee or its designated agent is strictly prohibited. If your
receipt of this transmission is in error, please notify this company
immediately by reply to this transmission and delete it from your
computer. Thank You. Artisan Components, Inc.

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------------------------------

Date: Mon, 18 Aug 2003 12:22:17 -0700 (PDT)
From: Syed Huq <[email-masked]>
Subject: Re: [IBIS-Users] Creating 3 sets of R/F Waveforms 

According to ../doc/s2ibis2.txt, it says, you can generate 100 Rising and 
100 Falling waveforms per model.

Do you get tables with no entries or what it simply does not generate a 
table..

Syed

>Date: Mon, 18 Aug 2003 11:37:41 -0700
>From: Jose G Corona <[email-masked]>
>User-Agent: Mozilla/5.0 (X11; U; SunOS sun4u; en-US; rv:0.9.4.1) 
Gecko/20020518 Netscape6/6.2.3
>X-Accept-Language: en-us
>MIME-Version: 1.0
>To: ibis-users <[email-masked]>
>Subject: [IBIS-Users] Creating 3 sets of R/F Waveforms 
>Content-Transfer-Encoding: 7bit
>
>Hello IBIS-users,
>
>I am trying to generate ibis model for SSTL, this IO has termination
>resistor of 50 Ohm connected to VDD/2. While looking into many other
>ibis models  from different providers, I have found that there are always
>two termination voltages (0 and VDD or 0 and VDD/2).  I want to create
>an ibis model with three termination voltages "0, vdd/2 and vdd". But
>the tool (North Carolina Univ's tool) only generates the waveforms for
>the first two but not the third.
>Is it possible for UNC s2ibis2 to create 3 sets of R/F waveforms?
> Also, I am not sure whether it is ibis-complaint to have three 
>termination voltage schemes?
>
>In the s2i tech file , I have using following lines
>-----------------------------------------------------
>rising_waveform1 = [Rising waveform] 50 0 NA NA NA NA NA NA NA
>falling_waveform1 = [Falling waveform] 50 0 NA NA NA NA NA NA NA
>rising_waveform2 = [Rising waveform] 50 1.25 NA NA NA NA NA NA NA
>falling_waveform2 = [Falling waveform] 50 1.25 NA NA NA NA NA NA NA
>
>rising_waveform3 = [Rising waveform] 50 2.5 NA NA NA NA NA NA NA
>falling_waveform3 = [Falling waveform] 50 2.5 NA NA NA NA NA NA NA
>----------------------------------------------------------
>
>Thanks for your precious time and I will really appreciate your response.
>
>-Jose 
>
>-- 
>Jose G. Corona
>Analog/Mixed-Signal Business Unit
>ARTISAN COMPONENTS, INC.
>Tel:    (858) 731-3428
>Fax:    (858) 457-5578
>
>www.artisan.com
>
>"Artisan: The IP Partner of Choice"
> 
>--
>This transmission is intended for the sole use of the individual and
>entity to whom it is addressed, and may contain information that is
>privileged, confidential and exempt from disclosure under applicable
>law. You are hereby notified that any dissemination, distribution or
>duplication of this transmission by someone other than the intended
>addressee or its designated agent is strictly prohibited. If your
>receipt of this transmission is in error, please notify this company
>immediately by reply to this transmission and delete it from your
>computer. Thank You. Artisan Components, Inc.
>
>
>
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>

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------------------------------

Date: Mon, 18 Aug 2003 16:26:05 -0400
From: "Ambrish Varma" <[email-masked]>
Subject: RE: [IBIS-Users] Creating 3 sets of R/F Waveforms 

Hi Jose,
My understanding is that you can generate 100 R/F waveforms. I have
tested the latest (s2ibis3 beta) to generate multiple R/F waveforms and
I am pretty sure that s2ibis2 will also do the same.

Would be glad to help you out if you gave me more specific details.
- -Ambrish.

Ambrish K Varma
[email-masked]
ph(919)513-2015
fax(919)515-2285

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]] On
Behalf Of Jose G Corona
Sent: Monday, August 18, 2003 2:38 PM
To: ibis-users
Subject: [IBIS-Users] Creating 3 sets of R/F Waveforms 

Hello IBIS-users,

I am trying to generate ibis model for SSTL, this IO has termination
resistor of 50 Ohm connected to VDD/2. While looking into many other
ibis models  from different providers, I have found that there are
always
two termination voltages (0 and VDD or 0 and VDD/2).  I want to create
an ibis model with three termination voltages "0, vdd/2 and vdd". But
the tool (North Carolina Univ's tool) only generates the waveforms for
the first two but not the third.
Is it possible for UNC s2ibis2 to create 3 sets of R/F waveforms?
 Also, I am not sure whether it is ibis-complaint to have three 
termination voltage schemes?

In the s2i tech file , I have using following lines
- -----------------------------------------------------
rising_waveform1 = [Rising waveform] 50 0 NA NA NA NA NA NA NA
falling_waveform1 = [Falling waveform] 50 0 NA NA NA NA NA NA NA
rising_waveform2 = [Rising waveform] 50 1.25 NA NA NA NA NA NA NA
falling_waveform2 = [Falling waveform] 50 1.25 NA NA NA NA NA NA NA

rising_waveform3 = [Rising waveform] 50 2.5 NA NA NA NA NA NA NA
falling_waveform3 = [Falling waveform] 50 2.5 NA NA NA NA NA NA NA
- ----------------------------------------------------------

Thanks for your precious time and I will really appreciate your
response.

- -Jose 

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------------------------------

Date: Mon, 18 Aug 2003 17:59:12 -0400
From: "Ambrish Varma" <[email-masked]>
Subject: FW: [IBIS-Users] Creating 3 sets of R/F Waveforms

Forwarding this to the group - for future reference.
- -Ambrish.

Ambrish K Varma
[email-masked]
North Carolina State University
ph(919)513-2015, fax(919)515-2285

- -----Original Message-----
From: Jose G Corona [mailto:[email-masked]] 
Sent: Monday, August 18, 2003 5:16 PM
To: Ambrish Varma
Cc: 'Anil Kumar'
Subject: Re: [IBIS-Users] Creating 3 sets of R/F Waveforms

Thanks Ambrish,

You are correct we had a syntax error in our .s2i file but after getting
the following lines in the .s2i file everything worked:

[Rising waveform] 50 3.3 NA NA NA NA NA NA NA
[Falling waveform] 50 3.3 NA NA NA NA NA NA NA
[Rising waveform] 50 0 NA NA NA NA NA NA NA
[Falling waveform] 50 0 NA NA NA NA NA NA NA
[Rising waveform] 50 2.5 NA NA NA NA NA NA NA
[Falling waveform] 50 2.5 NA NA NA NA NA NA NA

Thank you  for your quick response.

- -Jose & Anil

Ambrish Varma wrote:

>Hi Jose,
>My understanding is that you can generate 100 R/F waveforms. I have
>tested the latest (s2ibis3 beta) to generate multiple R/F waveforms and
>I am pretty sure that s2ibis2 will also do the same.
>
>Would be glad to help you out if you gave me more specific details.
>-Ambrish.
>
>Ambrish K Varma
>[email-masked]
>ph(919)513-2015
>fax(919)515-2285
>
>-----Original Message-----
>From: [email-masked] [mailto:[email-masked]] On
>Behalf Of Jose G Corona
>Sent: Monday, August 18, 2003 2:38 PM
>To: ibis-users
>Subject: [IBIS-Users] Creating 3 sets of R/F Waveforms 
>
>Hello IBIS-users,
>
>I am trying to generate ibis model for SSTL, this IO has termination
>resistor of 50 Ohm connected to VDD/2. While looking into many other
>ibis models  from different providers, I have found that there are
>always
>two termination voltages (0 and VDD or 0 and VDD/2).  I want to create
>an ibis model with three termination voltages "0, vdd/2 and vdd". But
>the tool (North Carolina Univ's tool) only generates the waveforms for
>the first two but not the third.
>Is it possible for UNC s2ibis2 to create 3 sets of R/F waveforms?
> Also, I am not sure whether it is ibis-complaint to have three 
>termination voltage schemes?
>
>In the s2i tech file , I have using following lines
>-----------------------------------------------------
>rising_waveform1 = [Rising waveform] 50 0 NA NA NA NA NA NA NA
>falling_waveform1 = [Falling waveform] 50 0 NA NA NA NA NA NA NA
>rising_waveform2 = [Rising waveform] 50 1.25 NA NA NA NA NA NA NA
>falling_waveform2 = [Falling waveform] 50 1.25 NA NA NA NA NA NA NA
>
>rising_waveform3 = [Rising waveform] 50 2.5 NA NA NA NA NA NA NA
>falling_waveform3 = [Falling waveform] 50 2.5 NA NA NA NA NA NA NA
>----------------------------------------------------------
>
>Thanks for your precious time and I will really appreciate your
>response.
>
>-Jose 
>
>
>

- -- 
Jose G. Corona
Analog/Mixed-Signal Business Unit
ARTISAN COMPONENTS, INC.
Tel:    (858) 731-3428
Fax:    (858) 457-5578

www.artisan.com

"Artisan: The IP Partner of Choice"
 
- --
This transmission is intended for the sole use of the individual and
entity to whom it is addressed, and may contain information that is
privileged, confidential and exempt from disclosure under applicable
law. You are hereby notified that any dissemination, distribution or
duplication of this transmission by someone other than the intended
addressee or its designated agent is strictly prohibited. If your
receipt of this transmission is in error, please notify this company
immediately by reply to this transmission and delete it from your
computer. Thank You. Artisan Components, Inc.

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------------------------------

Date: Mon, 18 Aug 2003 16:10:05 -0700
From: "Angulo, John" <[email-masked]>
Subject: RE: [IBIS-Users] time shifted edges

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C365DD.DC494D01
Content-Type: text/plain

Erik,
 
The model's V-T tables dictate to the simulator when to start the buffer's edges.  When you see a time shift in the simulated edges relative to your V-T tables, it probably means that the tool is clipping some of the lead-in time from the tables before simulation.  This is useful for those models that contain excessive lengths of dead time before the launch of the waveforms (we've seen ten nanoseconds in some cases), but it is undesirable in LVDS or other applications with carefully constructed V-T tables for precise duty cycle timing.  Hyperlynx lets you turn lead-in clipping off.  I'll contact you offline to point out the exact option.
 
Best regards,
John Angulo 
Hyperlynx Products 
Mentor Graphics Corp. 
[email-masked] 
425-869-2320 

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]
Sent: Monday, August 18, 2003 12:56 AM
To: [email-masked]
Subject: [IBIS-Users] time shifted edges

Dear IBIS colleagues, 

I am trying to model a differential LVDS output buffer. 
I have generated waveform tables from Spectre simulations. The falling and rising waveforms look fine at first glance. 
In Spectre the falling and rising waveforms (of both outputs, which are equal) have a crossing point about in the middle of the DC level (high and low state). 
When I simulate my model with Hyperlynx I see that the crossing point is at a very low level, because of a time shift of the edges. I simulate with an Rfix (50 Ohm) to a Vfix which is 
in the middle of the DC levels. 

So my question is: 
How does a simulator determine where the edges start? Do different simulators use the same algorithm for this? 
What can I do to get crossing point in the right place? (or: how do I control the place (in time) of the edges?). 

Can anyone help me? Thanks in advance. 

With kind regards, 

Ir. Erik van der Ven
Room DB1032
Business Line Networking Infrastructure
Philips Semiconductors BV
Gerstweg 2
6534 AE Nijmegen
The Netherlands
Phone: +31-24-3534334

- ------_=_NextPart_001_01C365DD.DC494D01
Content-Type: text/html

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=us-ascii">

<META content="MSHTML 5.50.4916.2300" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=251415618-18082003><FONT face=Arial color=#0000ff 
size=2>Erik,</FONT></SPAN></DIV>
<DIV><SPAN class=251415618-18082003><FONT face=Arial color=#0000ff 
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=251415618-18082003><FONT face=Arial color=#0000ff size=2>The 
model's V-T tables dictate to the&nbsp;simulator when&nbsp;to start the buffer's 
edges.&nbsp; When you see a time shift in the simulated edges relative to your 
V-T tables, it probably means that the tool is clipping some of the lead-in time 
from the tables before simulation.&nbsp; This is useful for those models that 
contain&nbsp;excessive&nbsp;lengths of&nbsp;dead time before the launch of the 
waveforms (we've seen ten nanoseconds in some cases), but it is undesirable in 
LVDS or other applications with carefully constructed V-T tables 
for&nbsp;precise duty cycle timing.&nbsp; Hyperlynx lets you turn lead-in 
clipping off.&nbsp; I'll contact you offline to point out the exact 
option.</FONT></SPAN></DIV>
<DIV><SPAN class=251415618-18082003><FONT face=Arial color=#0000ff 
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=251415618-18082003><FONT face=Arial color=#0000ff size=2>Best 
regards,</FONT></SPAN></DIV>
<DIV><SPAN class=251415618-18082003>
<P><FONT face=Arial size=2>John Angulo</FONT> <BR><FONT face=Arial 
size=2>Hyperlynx Products</FONT> <BR><FONT face=Arial size=2>Mentor Graphics 
Corp.</FONT> <BR><FONT face=Arial size=2>[email-masked]</FONT> <BR><FONT 
face=Arial size=2>425-869-2320</FONT> </P></SPAN></DIV>
<DIV><SPAN class=251415618-18082003><FONT face=Arial color=#0000ff 
size=2></FONT></SPAN>&nbsp;</DIV>
<BLOCKQUOTE>
  <DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma 
  size=2>-----Original Message-----<BR><B>From:</B> [email-masked] 
  [mailto:[email-masked]]<BR><B>Sent:</B> Monday, August 18, 2003 
  12:56 AM<BR><B>To:</B> [email-masked]<BR><B>Subject:</B> [IBIS-Users] time 
  shifted edges<BR><BR></FONT></DIV><BR><FONT face=sans-serif size=2>Dear IBIS 
  colleagues,</FONT> <BR><BR><FONT face=sans-serif size=2>I am trying to model a 
  differential LVDS output buffer.</FONT> <BR><FONT face=sans-serif size=2>I 
  have generated waveform tables from Spectre simulations. The falling and 
  rising waveforms look fine at first glance.</FONT> <BR><FONT face=sans-serif 
  size=2>In Spectre the falling and rising waveforms (of both outputs, which are 
  equal) have a crossing point about in the middle of the DC level (high and low 
  state).</FONT> <BR><FONT face=sans-serif size=2>When I simulate my model with 
  Hyperlynx I see that the crossing point is at a very low level, because of a 
  time shift of the edges. I simulate with an Rfix (50 Ohm) to a Vfix which is 
  </FONT><BR><FONT face=sans-serif size=2>in the middle of the DC levels.</FONT> 
  <BR><BR><FONT face=sans-serif size=2>So my question is:</FONT> <BR><FONT 
  face=sans-serif size=2>How does a simulator determine where the edges start? 
  Do different simulators use the same algorithm for this?</FONT> <BR><FONT 
  face=sans-serif size=2>What can I do to get crossing point in the right place? 
  (or: how do I control the place (in time) of the edges?).</FONT> <BR><BR><FONT 
  face=sans-serif size=2>Can anyone help me? Thanks in advance.</FONT> 
  <BR><BR><FONT face=sans-serif size=2>With kind regards,</FONT> <BR><FONT 
  face=sans-serif size=2><BR>Ir. Erik van der Ven<BR>Room DB1032<BR>Business 
  Line Networking Infrastructure<BR>Philips Semiconductors BV<BR>Gerstweg 
  2<BR>6534 AE Nijmegen<BR>The Netherlands<BR>Phone: 
+31-24-3534334</FONT></BLOCKQUOTE></BODY></HTML>

- ------_=_NextPart_001_01C365DD.DC494D01--
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|with just the appropriate command message(s) in the body:
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------------------------------

Date: Mon, 18 Aug 2003 18:59:54 -0400
From: "Allen Chao" <[email-masked]>
Subject: RE: [IBIS-Users]DC Sweep for the pullup IV curve

Hi Arpad,
You are right, the current source is composed by 2 pull-up transistors in
series.
Now, for the clamping IV curves, do we always sweep from -Vcc to Vcc (for
gnd clamp) and sweep from Vcc to 2Vcc(for power clamp) at the high-impedance
output? or there are other ways to do it? 'cause our output has 3 modes, low
speed, full speed and high speed, however there is only one mode (stand-by)
where the output is in high-impedance. In different modes(LS/FS/HS), there
are different circuitries connected to the output, using the above method,
we will get the same power clamp/gnd clamp IV curves for all 3 modes. I am
not sure if this is right. Also, I think you are right about the parasitic
diodes being the clamping devices. (Since we don't really have a specific
diode for clamping and there is still some clamping effect in high-impedance
state.)

Thanks,
Allen

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On
Behalf Of Muranyi, Arpad
Sent: Monday, August 18, 2003 12:40 PM
To: [email-masked]
Subject: RE: [IBIS-Users]DC Sweep for the pullup IV curve

Allen,

OK, there is no pulldown, because the external resistor pulls the
signal to aero volts.  But what is that "current source" made out
of?  The designs I have seen so far implement current sources with
transistors, except they are sized and biased in such a way that
their IV curve will look more like a current source.

What does a current source's IV curve look like?  By definition a
current source provides a constant current regardless of what the
voltage across its terminals is, i.e. the IV curve is a horizontal
line.  In theory this should extend to all voltages, however, in
real life (unless it is a specialized circuit design) it will be
polarized (i.e. work only for one voltage polarity, say positive).

So implementing a current source can be done by a huge transistor,
which has a very steep linear region (coming out of the origin),
and then using a fairly low bias voltage you can operate in its
saturation region, which looks like a constant current source.
Note, however, that this transistor is still connected to some
sort of a supply rail.

So regarding your buffer, I would guess that it has this kind of
a pullup transistor, and whether the designer wants to call it a
pullup or not is a different question.

Having said all this, you can make an IBIS model of this buffer
using the "open source" model type, which has a pullup, but no
pulldown IV curve.  Don't worry about it being a current source,
the shape of the IV curve will describe that very well.

Regarding clamps, I have a hard time to believe that the above
transistor doesn't have any parasitic diodes (unless it is not
MOSFET) and that there is absolutely no ESD protection in this
device.  It may be the case, but usually it is not.  So I would
expect that you would still see some currents outside the rails
when you 3-state the device for this reason.  These currents
will go into the IBIS clamp IV tables.

Arpad Muranyi
Intel Corporation
=================================================================

- -----Original Message-----
From: Allen Chao [mailto:[email-masked]]
Sent: Monday, August 18, 2003 8:04 AM
To: Muranyi, Arpad; [email-masked]
Subject: RE: [IBIS-Users]DC Sweep for the pullup IV curve

Hi Arpad,
Thanks for your fast reply... I just consulted further with the buffer
designer here. He said that this output is a high-speed data output and
instead of using Vcc (power-supply voltage) for the power clamp diode and
the pull-up transistor, we use a current source to drive the output to 0.4v
for signal high and simply turn off the transistors between current source
and the output for the low signal. (since the output is also connected to
another resistor and ground, the output will be grounded for the low
signal). As I described, there are not really pullup/pulldown transistors
and clamping devices.
My question is, can we still create an IBIS model for this output?

Thanks in advance,

Allen Chao
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|with just the appropriate command message(s) in the body:
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|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Wed, 20 Aug 2003 08:55:41 -0700
From: "Muranyi, Arpad" <[email-masked]>
Subject: RE: [IBIS-Users]DC Sweep for the pullup IV curve

Allen,

Even though the IBIS spec requires those ranges you mention,
it does not forbid to provide the entire -Vcc to 2Vcc range
for the clamps.  In my IBIS models I always give the whole
range, but I also make sure that I am not double counting for
some effects (on die terminations, etc).

Also, when you measure the data, you will have to sweep it
the full range anyway, because you have to provide a difference
curve for the pullup and pulldown tables.  In order be able to
subtract the clamp curve from the pullup or pulldown, you have
to have the whole range covered by both.  If you have the data,
you might as well put it in the IBIS model too.

Arpad
===============================================================

- -----Original Message-----
From: Allen Chao [mailto:[email-masked]]
Sent: Monday, August 18, 2003 4:00 PM
To: Muranyi, Arpad; [email-masked]
Subject: RE: [IBIS-Users]DC Sweep for the pullup IV curve

Hi Arpad,
You are right, the current source is composed by 2 pull-up transistors in
series.
Now, for the clamping IV curves, do we always sweep from -Vcc to Vcc (for
gnd clamp) and sweep from Vcc to 2Vcc(for power clamp) at the high-impedance
output? or there are other ways to do it? 'cause our output has 3 modes, low
speed, full speed and high speed, however there is only one mode (stand-by)
where the output is in high-impedance. In different modes(LS/FS/HS), there
are different circuitries connected to the output, using the above method,
we will get the same power clamp/gnd clamp IV curves for all 3 modes. I am
not sure if this is right. Also, I think you are right about the parasitic
diodes being the clamping devices. (Since we don't really have a specific
diode for clamping and there is still some clamping effect in high-impedance
state.)

Thanks,
Allen

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On
Behalf Of Muranyi, Arpad
Sent: Monday, August 18, 2003 12:40 PM
To: [email-masked]
Subject: RE: [IBIS-Users]DC Sweep for the pullup IV curve

Allen,

OK, there is no pulldown, because the external resistor pulls the
signal to aero volts.  But what is that "current source" made out
of?  The designs I have seen so far implement current sources with
transistors, except they are sized and biased in such a way that
their IV curve will look more like a current source.

What does a current source's IV curve look like?  By definition a
current source provides a constant current regardless of what the
voltage across its terminals is, i.e. the IV curve is a horizontal
line.  In theory this should extend to all voltages, however, in
real life (unless it is a specialized circuit design) it will be
polarized (i.e. work only for one voltage polarity, say positive).

So implementing a current source can be done by a huge transistor,
which has a very steep linear region (coming out of the origin),
and then using a fairly low bias voltage you can operate in its
saturation region, which looks like a constant current source.
Note, however, that this transistor is still connected to some
sort of a supply rail.

So regarding your buffer, I would guess that it has this kind of
a pullup transistor, and whether the designer wants to call it a
pullup or not is a different question.

Having said all this, you can make an IBIS model of this buffer
using the "open source" model type, which has a pullup, but no
pulldown IV curve.  Don't worry about it being a current source,
the shape of the IV curve will describe that very well.

Regarding clamps, I have a hard time to believe that the above
transistor doesn't have any parasitic diodes (unless it is not
MOSFET) and that there is absolutely no ESD protection in this
device.  It may be the case, but usually it is not.  So I would
expect that you would still see some currents outside the rails
when you 3-state the device for this reason.  These currents
will go into the IBIS clamp IV tables.

Arpad Muranyi
Intel Corporation
=================================================================

- -----Original Message-----
From: Allen Chao [mailto:[email-masked]]
Sent: Monday, August 18, 2003 8:04 AM
To: Muranyi, Arpad; [email-masked]
Subject: RE: [IBIS-Users]DC Sweep for the pullup IV curve

Hi Arpad,
Thanks for your fast reply... I just consulted further with the buffer
designer here. He said that this output is a high-speed data output and
instead of using Vcc (power-supply voltage) for the power clamp diode and
the pull-up transistor, we use a current source to drive the output to 0.4v
for signal high and simply turn off the transistors between current source
and the output for the low signal. (since the output is also connected to
another resistor and ground, the output will be grounded for the low
signal). As I described, there are not really pullup/pulldown transistors
and clamping devices.
My question is, can we still create an IBIS model for this output?

Thanks in advance,

Allen Chao
|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
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|  subscribe   ibis       <optional e-mail address, if different>
|  subscribe   ibis-users <optional e-mail address, if different>
|  unsubscribe ibis       <optional e-mail address, if different>
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|
|or email a written request to [email-masked].
|
|IBIS reflector archives exist under:
|
|  http://www.eda.org/pub/ibis/email_archive/  Recent
|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

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|with just the appropriate command message(s) in the body:
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|
|or email a written request to [email-masked].
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|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Wed, 20 Aug 2003 16:13:06 -0400
From: "Lynne Green" <[email-masked]>
Subject: [IBIS-Users] First Call for Papers for PCB East IBIS Summit

- ------------------------------------------------------------------------
- -------
                             IBIS SUMMIT
                          FIRST CALL FOR
               PARTICIPATION & PRESENTATIONS
- ------------------------------------------------------------------------
- -------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

              I B I S   S U M M I T   M E E T I N G

Time/Date:  Tuesday, October 21, 2003,  9:00 AM to 5:00 PM

Location:   North East Systems Associates
                5 Lan Drive
                Westford, MA 01886

Content:    Presentations and Discussions

Purpose:   Solicit and Exchange IBIS Model Related Information and
                Ideas.

Sponsors:   If your company would be interested in sponsoring this
            event, please contact Lynne Green <[email-masked]>.
            Sponsorship is available for the lunch and coffee breaks.
            Benefits to sponsors include formal recognition at the
            meeting and mention in the Calls for Papers and meeting
            minutes.

            Your financial support strengthens the organization by
            allowing IBIS to focus resources on industry activities
            rather than raising money, and you will receive generous
            thanks for your support.

PCB Design Conference East
            October 20 - 24, 2003
            Holiday Inn Boxborough 
            242 Adams Place 
            Boxborough, MA 01719 
            
            See <http://www.pcbeast.com/> for more information.

BACKGROUND

PCB East is the premier East Coast event dedicated exclusively
to PCB design and engineering professionals.  Topics of current
interest to the EIA IBIS Open Forum are addressed at PCB East.

This meeting will be conducted as a formal IBIS Summit Meeting.
Presentations are expected to be available and archived in an
electronic format, and minutes of the meeting will be issued.
Any pending formal decisions (votes) will be announced at least
two weeks prior to the meeting.

CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development,
and digital circuit design are invited to participate in the Summit
meeting. If you plan to participate, please register with the
information below:

   Name:
   E-mail address:
   Company:
   Telephone:

Send to:
    Kathy Breda ([email-masked]).

CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have experiences
of interest to the IBIS modeling community.  In the past, these
have included demonstrations of modeling techniques, explanations
of behavioral algorithms and descriptions of difficulties encountered
in specific applications.  Of particular interest are topics related to
model correlation, modeling building experiences and comparisons
to other modeling methods.  Presentations may be addressed to
any and all levels of IBIS experience, from beginning to advanced.

Format of Presentation:  LCD Projection with Windows laptop.
Time:          15-30 Minutes
Electronic Archival: We request electronic versions so that the
               presentations can be archived and also made
               available to non-attendees.  Formats used in
               the past have been text, Power Point, Word,
               Postscript, and Acrobat.  Electronic 
               presentations should be made available by
               October 14, 2003 for uploading and copying to
               the presentation laptop.

If you plan a presentation, please supply

   Title:
   Presenter:
   E-mail address:
   Company:
   Telephone:

   Estimated Time:

Send this to:

  Lynne Green ([email-masked])

AGENDA

The agenda includes presentations, discussions, breaks, and
a luncheon (which will be provided).  This will be developed
as presentation proposals are received.

LIST OF NEARBY HOTELS

See <http://www.pcbeast.com/travel_info/> for travel directions,
hotels and other information.
- -----------------------------------------------------------------
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|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
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------------------------------

Date: Wed, 20 Aug 2003 16:58:48 -0400
From: "Allen Chao" <[email-masked]>
Subject: RE: [IBIS-Users] IBIS model Error

Hi all,
Here is the simplified output buffer of my device... due to the internal
resistor, my falling/rising waveforms are not falling/rising like the sample
IBIS models I found on the internet.
For example, my falling waveform with the 50-ohm load terminated with
different VDD as following are falling from 3.3/2.97/3.63V to 1.5V instead
of 0V. My confusion is whether I should remove the internal resistor or
leave the way it is...

[Falling Waveform]
R_fixture = 50
V_fixture = 3.30
V_fixture_min = 2.97
V_fixture_max = 3.63

                 Vdd         Vdd
                 _____       ____
                      |     |
                      |     |
                     -      |
                 ___|       |
                    |      / \
                     -     ---
                      |     |      internal resistor
                      |-----|---------^v^v^v----------x
                      |     |         45 ohm        output(Bond pad)
                     -
                 ___|       |
                    |      / \
                     -     ---
                      |     |
                      |     |
                 -----------------  VSS

Thanks in advance,

Allen Chao

- -----Original Message-----
From: Tom Dagostino [mailto:[email-masked]]
Sent: Wednesday, August 13, 2003 5:55 PM
To: 'Allen Chao'
Subject: RE: [IBIS-Users] IBIS model Error

Allen

The load line is the straight negative sloping line.  Where it intersects
the pulldown curves is the calculated end point for that load.  This is the
voltage that the parser is predicting.  The parser will read the first point
in the rising waveform with a 50 Ohm load to 3.3V table and then compare
this to the load line applied to the pulldown curve.  Ideally the two points
should match.  The parser will go through all the VT tables and match their
end points (first point and last point in the table) with the predicted
voltages computed from the know load R, known load termination voltage and
the appropriate pullup and pulldown curves (which will include the power and
ground clamps).

A falling waveform in this example will be the falling waveform with 50 Ohms
to 3.3 (as opposed to 50 Ohms to Gnd).  The falling waveform will start at
3.3V (the first point in the table) and end at the predicted voltage (the
last point in the table).  If the two differ you get either a warning or an
error, depending on the magnitude of the difference.

For the cases where the falling waveform has its load tied to ground then
the fall will start at the level predicted by the load line applied to the
pullup table and end at ground.  For both of these examples I'm assuming a
simple CMOS driver with not special features, just a plane pullup and
pulldown with zero current in the clamps in the active region between Gnd
and Vcc.

Tom Dagostino

Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC

2926 SE Yamhill St.                Device Modeling Division

Portland, OR 97214                 13610 SW Harness Lane

                                   Beaverton, OR 97008

http://www.teraspeed.com           503-430-1065

[email-masked]
- -----Original Message-----
From: Allen Chao [mailto:[email-masked]]
Sent: Wednesday, August 13, 2003 2:40 PM
To: [email-masked]
Subject: RE: [IBIS-Users] IBIS model Error

Hi Tom,

Thanks for showing me this. But what does it mean? and what are the DC end
points that should match? Can you also tell me how the falling waveform
should behave in your example?

Allen
- -----Original Message-----
From: Tom Dagostino [mailto:[email-masked]]
Sent: Wednesday, August 13, 2003 4:52 PM
To: 'Allen Chao'
Subject: RE: [IBIS-Users] IBIS model Error

Allen

See the enclosed spreadsheet. I added a 50 Ohm load line terminated to 3.3V
to the pulldown curves in this example

Tom Dagostino

Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC

2926 SE Yamhill St.                Device Modeling Division

Portland, OR 97214                 13610 SW Harness Lane

                                   Beaverton, OR 97008

http://www.teraspeed.com           503-430-1065

[email-masked]
- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On Behalf Of
Allen Chao
Sent: Wednesday, August 13, 2003 1:38 PM
To: [email-masked]; [email-masked];
[email-masked]
Subject: RE: [IBIS-Users] IBIS model Error

Hi IBIS experts,
I have the same problem as Muthu Lakshmi. I don't really understand how the
parser calculated the DC end points from the IV table... If anyone can
kindly show me how it works or know where to find the information on the
internet, it will be greatly appreciated.

Thanks in advance,

Allen Chao

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On Behalf Of
[email-masked]
Sent: Monday, July 28, 2003 4:10 AM
To: [email-masked]; [email-masked]
Subject: Re: [IBIS-Users] IBIS model Error

Hello Muthu Lakshmi,

I think there is something wrong with your IBIS model. The DC end points
calculated from the I-V tables should match the V-T end points (logic
levels). If the error is within 2% you should get a warning, otherwise an
error. The difference you mention is very big.

The DC end points are calculated from the I-V tables (therefore you don't
see the end points of the V-T table). The I-V tables are derived by sweeping
a voltage at the output and measuring the resulting current. By applying a
certain load the voltages from the logic high and low level are calculated
from the pull-up and pull-down curve (and of course they should be near the
waveform end point voltages). The V-T data is used to describe the
transition between the logic levels calculated from the I-V data.

I would suggest that you contact Cypress to ask if this model is OK.

With kind regards,

Ir. Erik van der Ven
Room DB1032
Business Line Networking Infrastructure
Philips Semiconductors BV
Gerstweg 2
6534 AE Nijmegen
The Netherlands
Phone: +31-24-3534334

[email-masked]
Sent by:
[email-masked]

07/28/03 05:32 AM

        To:        [email-masked]
        cc:        (bcc: Erik van der Ven/NYM/SC/PHILIPS)
        Subject:        [IBIS-Users] IBIS model Error
        Classification:

Hi All,

I need IBIS expert's advice on the following.

I get the following warning when checking the IBIS model.

Warning - Model bp_usb_hs: The [Rising Waveform]
     with [R_fixture]=45 Ohms and [V_fixture]=0V
     has TYP column DC endpoints of  0.00V and  0.38v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 1.14V and  1.06V),
     a difference of 99.99% and 64.28%, respectively.

Warning - Model bp_usb_hs: The [Falling Waveform]
     with [R_fixture]=45 Ohms and [V_fixture]=0V
     has TYP column DC endpoints of  0.00V and  0.38v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 1.14V and  1.06V),
     a difference of 99.99% and 64.28%, respectively.

Warning - Model bp_usb_hs: The [Rising Waveform]
     with [R_fixture]=45 Ohms and [V_fixture_min]=0V
     has MIN column DC endpoints of  0.00V and  0.37v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 1.09V and  0.93V),
     a difference of 99.99% and 60.23%, respectively.

Warning - Model bp_usb_hs: The [Falling Waveform]
     with [R_fixture]=45 Ohms and [V_fixture_min]=0V
     has MIN column DC endpoints of  0.00V and  0.37v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 1.09V and  0.93V),
     a difference of 99.99% and 60.23%, respectively.

Warning - Model bp_usb_hs: The [Rising Waveform]
     with [R_fixture]=45 Ohms and [V_fixture_max]=0V
     has MAX column DC endpoints of  0.00V and  0.39v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 1.77V and  1.83V),
     a difference of 100.00% and 78.72%, respectively.

Warning - Model bp_usb_hs: The [Falling Waveform]
     with [R_fixture]=45 Ohms and [V_fixture_max]=0V
     has MAX column DC endpoints of  0.00V and  0.38v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 1.77V and  1.83V),
     a difference of 100.00% and 79.26%, respectively.

Please tell me the impact of this warning in simulation. I use XTK for the
simulation. Eventhough the rise and fall VT curve values range from 0V to
0.38V in the IBIS model, I get 1.04V to 1.14V wave form. How is this related
with this. I am using Cypress "CY7C65640" hub controller's IBIS model.

Awaiting your earliest reply.

Note: One IBIS parser gives the above warnings and another parser gives them
as Errors.
       I do not know whether files can be attached with this mail. If it is
OK, I can send  the IBIS model.

thanks & regards
K.Muthu Lakshmi (KML)

SCM Microsystems (India) Pvt. Ltd.
email: [email-masked]
Web: www.scmmicro.com

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
|
|  help
|  subscribe   ibis       <optional e-mail address, if different>
|  subscribe   ibis-users <optional e-mail address, if different>
|  unsubscribe ibis       <optional e-mail address, if different>
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|
|or email a written request to [email-masked].
|
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|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Wed, 20 Aug 2003 14:14:02 -0700
From: "Tom Dagostino" <[email-masked]>
Subject: RE: [IBIS-Users] IBIS model Error

This is quite normal operation for a buffer.  All outputs have a finite
output impedance.  The output impedance and the load form a voltage divider
so the output voltage will never make it to zero volts when there is a
pullup termination.  The output voltage will be

Vout = Vdd * (Rout/(Rout + Rload)

Tom Dagostino
Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
2926 SE Yamhill St.                Device Modeling Division
Portland, OR 97214                 13610 SW Harness Lane
                                   Beaverton, OR 97008
http://www.teraspeed.com           503-430-1065
[email-masked]

- -----Original Message-----
From: Allen Chao [mailto:[email-masked]]
Sent: Wednesday, August 20, 2003 1:59 PM
To: [email-masked]; [email-masked]
Subject: RE: [IBIS-Users] IBIS model Error

Hi all,
Here is the simplified output buffer of my device... due to the internal
resistor, my falling/rising waveforms are not falling/rising like the sample
IBIS models I found on the internet.
For example, my falling waveform with the 50-ohm load terminated with
different VDD as following are falling from 3.3/2.97/3.63V to 1.5V instead
of 0V. My confusion is whether I should remove the internal resistor or
leave the way it is...

[Falling Waveform]
R_fixture = 50
V_fixture = 3.30
V_fixture_min = 2.97
V_fixture_max = 3.63

                 Vdd         Vdd
                 _____       ____
                      |     |
                      |     |
                     -      |
                 ___|       |
                    |      / \
                     -     ---
                      |     |      internal resistor
                      |-----|---------^v^v^v----------x
                      |     |         45 ohm        output(Bond pad)
                     -
                 ___|       |
                    |      / \
                     -     ---
                      |     |
                      |     |
                 -----------------  VSS

Thanks in advance,

Allen Chao

- -----Original Message-----
From: Tom Dagostino [mailto:[email-masked]]
Sent: Wednesday, August 13, 2003 5:55 PM
To: 'Allen Chao'
Subject: RE: [IBIS-Users] IBIS model Error

Allen

The load line is the straight negative sloping line.  Where it intersects
the pulldown curves is the calculated end point for that load.  This is the
voltage that the parser is predicting.  The parser will read the first point
in the rising waveform with a 50 Ohm load to 3.3V table and then compare
this to the load line applied to the pulldown curve.  Ideally the two points
should match.  The parser will go through all the VT tables and match their
end points (first point and last point in the table) with the predicted
voltages computed from the know load R, known load termination voltage and
the appropriate pullup and pulldown curves (which will include the power and
ground clamps).

A falling waveform in this example will be the falling waveform with 50 Ohms
to 3.3 (as opposed to 50 Ohms to Gnd).  The falling waveform will start at
3.3V (the first point in the table) and end at the predicted voltage (the
last point in the table).  If the two differ you get either a warning or an
error, depending on the magnitude of the difference.

For the cases where the falling waveform has its load tied to ground then
the fall will start at the level predicted by the load line applied to the
pullup table and end at ground.  For both of these examples I'm assuming a
simple CMOS driver with not special features, just a plane pullup and
pulldown with zero current in the clamps in the active region between Gnd
and Vcc.

Tom Dagostino

Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC

2926 SE Yamhill St.                Device Modeling Division

Portland, OR 97214                 13610 SW Harness Lane

                                   Beaverton, OR 97008

http://www.teraspeed.com           503-430-1065

[email-masked]
- -----Original Message-----
From: Allen Chao [mailto:[email-masked]]
Sent: Wednesday, August 13, 2003 2:40 PM
To: [email-masked]
Subject: RE: [IBIS-Users] IBIS model Error

Hi Tom,

Thanks for showing me this. But what does it mean? and what are the DC end
points that should match? Can you also tell me how the falling waveform
should behave in your example?

Allen
- -----Original Message-----
From: Tom Dagostino [mailto:[email-masked]]
Sent: Wednesday, August 13, 2003 4:52 PM
To: 'Allen Chao'
Subject: RE: [IBIS-Users] IBIS model Error

Allen

See the enclosed spreadsheet. I added a 50 Ohm load line terminated to 3.3V
to the pulldown curves in this example

Tom Dagostino

Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC

2926 SE Yamhill St.                Device Modeling Division

Portland, OR 97214                 13610 SW Harness Lane

                                   Beaverton, OR 97008

http://www.teraspeed.com           503-430-1065

[email-masked]
- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On Behalf Of
Allen Chao
Sent: Wednesday, August 13, 2003 1:38 PM
To: [email-masked]; [email-masked];
[email-masked]
Subject: RE: [IBIS-Users] IBIS model Error

Hi IBIS experts,
I have the same problem as Muthu Lakshmi. I don't really understand how the
parser calculated the DC end points from the IV table... If anyone can
kindly show me how it works or know where to find the information on the
internet, it will be greatly appreciated.

Thanks in advance,

Allen Chao

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On Behalf Of
[email-masked]
Sent: Monday, July 28, 2003 4:10 AM
To: [email-masked]; [email-masked]
Subject: Re: [IBIS-Users] IBIS model Error

Hello Muthu Lakshmi,

I think there is something wrong with your IBIS model. The DC end points
calculated from the I-V tables should match the V-T end points (logic
levels). If the error is within 2% you should get a warning, otherwise an
error. The difference you mention is very big.

The DC end points are calculated from the I-V tables (therefore you don't
see the end points of the V-T table). The I-V tables are derived by sweeping
a voltage at the output and measuring the resulting current. By applying a
certain load the voltages from the logic high and low level are calculated
from the pull-up and pull-down curve (and of course they should be near the
waveform end point voltages). The V-T data is used to describe the
transition between the logic levels calculated from the I-V data.

I would suggest that you contact Cypress to ask if this model is OK.

With kind regards,

Ir. Erik van der Ven
Room DB1032
Business Line Networking Infrastructure
Philips Semiconductors BV
Gerstweg 2
6534 AE Nijmegen
The Netherlands
Phone: +31-24-3534334

[email-masked]
Sent by:
[email-masked]

07/28/03 05:32 AM

        To:        [email-masked]
        cc:        (bcc: Erik van der Ven/NYM/SC/PHILIPS)
        Subject:        [IBIS-Users] IBIS model Error
        Classification:

Hi All,

I need IBIS expert's advice on the following.

I get the following warning when checking the IBIS model.

Warning - Model bp_usb_hs: The [Rising Waveform]
     with [R_fixture]=45 Ohms and [V_fixture]=0V
     has TYP column DC endpoints of  0.00V and  0.38v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 1.14V and  1.06V),
     a difference of 99.99% and 64.28%, respectively.

Warning - Model bp_usb_hs: The [Falling Waveform]
     with [R_fixture]=45 Ohms and [V_fixture]=0V
     has TYP column DC endpoints of  0.00V and  0.38v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 1.14V and  1.06V),
     a difference of 99.99% and 64.28%, respectively.

Warning - Model bp_usb_hs: The [Rising Waveform]
     with [R_fixture]=45 Ohms and [V_fixture_min]=0V
     has MIN column DC endpoints of  0.00V and  0.37v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 1.09V and  0.93V),
     a difference of 99.99% and 60.23%, respectively.

Warning - Model bp_usb_hs: The [Falling Waveform]
     with [R_fixture]=45 Ohms and [V_fixture_min]=0V
     has MIN column DC endpoints of  0.00V and  0.37v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 1.09V and  0.93V),
     a difference of 99.99% and 60.23%, respectively.

Warning - Model bp_usb_hs: The [Rising Waveform]
     with [R_fixture]=45 Ohms and [V_fixture_max]=0V
     has MAX column DC endpoints of  0.00V and  0.39v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 1.77V and  1.83V),
     a difference of 100.00% and 78.72%, respectively.

Warning - Model bp_usb_hs: The [Falling Waveform]
     with [R_fixture]=45 Ohms and [V_fixture_max]=0V
     has MAX column DC endpoints of  0.00V and  0.38v, but
     an equivalent load applied to the model's I-V tables yields
     different voltages ( 1.77V and  1.83V),
     a difference of 100.00% and 79.26%, respectively.

Please tell me the impact of this warning in simulation. I use XTK for the
simulation. Eventhough the rise and fall VT curve values range from 0V to
0.38V in the IBIS model, I get 1.04V to 1.14V wave form. How is this related
with this. I am using Cypress "CY7C65640" hub controller's IBIS model.

Awaiting your earliest reply.

Note: One IBIS parser gives the above warnings and another parser gives them
as Errors.
       I do not know whether files can be attached with this mail. If it is
OK, I can send  the IBIS model.

thanks & regards
K.Muthu Lakshmi (KML)

SCM Microsystems (India) Pvt. Ltd.
email: [email-masked]
Web: www.scmmicro.com

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
|
|  help
|  subscribe   ibis       <optional e-mail address, if different>
|  subscribe   ibis-users <optional e-mail address, if different>
|  unsubscribe ibis       <optional e-mail address, if different>
|  unsubscribe ibis-users <optional e-mail address, if different>
|
|or email a written request to [email-masked].
|
|IBIS reflector archives exist under:
|
|  http://www.eda.org/pub/ibis/email_archive/  Recent
|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Sat, 23 Aug 2003 21:40:42 -0700
From: Bob Ross <[email-masked]>
Subject: [IBIS-Users] BIRD82.2 - Clarification of Clamp Table Use

Hello:

The text of BIRD82.2, approved at the August 22, 2003 meeting,
is shown below.

Bob

****************************************************************************
****************************************************************************
                        Buffer Issue Resolution Document  (BIRD)

BIRD ID#:       82.2
ISSUE TITLE:    Clarification of Clamp Table Use
REQUESTOR:      Lynne Green, Cadence, and Robert Haller, SiSoft
DATE SUBMITTED: June 27, 2003, August 7, 2003, August 22, 2003
DATE ACCEPTED BY IBIS OPEN FORUM:  August 22, 2003

****************************************************************************
****************************************************************************

STATEMENT OF THE ISSUE:

Double-counting of clamp currents is the result of confusion over how the
clamp currents are summed by the tools.  Model makers are often unsure if
clamps are always active, or whether the [Power Clamp] works only with the
[Pullup] and the [GND Clamp] only with the [Pulldown].  This is difficult,
if not impossible, to detect with a parser.

This issue can be resolved by clarification of the text under
|    Keywords:  [Pulldown], [Pullup], [GND Clamp], [POWER Clamp]

****************************************************************************

STATEMENT OF THE RESOLVED SPECIFICATIONS:

Old text:
|         It is assumed that the simulator sums the clamp tables
|         together with the appropriate [Pullup] or [Pulldown] table
|         when a buffer is driving high or low, respectively.  From this
|         assumption and the nature of 3-statable buffers, it follows
|         that the data in the clamping table sections are handled as
|         constantly present tables and the [Pullup] and [Pulldown]
|         tables are used only when needed in the simulation.
|

Proposed text:
|         It is intended that the [POWER Clamp] and [GND Clamp] tables are
|         summed together and then added to the appropriate [Pullup] or
|         [Pulldown] table when a buffer is driving high or low,
|         respectively.
|
|         From this assumption and the nature of 3-statable buffers, it
|         follows that the data in the clamping table sections are handled
|         as constantly present tables and the [Pullup] and [pulldown]
|         tables are used only when needed in the simulation.
|

****************************************************************************

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

Comments from members of the Quality committee, as well as others,
indicated that some models double-count clamp currents.

****************************************************************************

ANY OTHER BACKGROUND INFORMATION:

Initially, it was suggested that this be detected by the parser, but
it was decided that this was too difficult.  This led to further
discussion of why double-counting occurred, and how clarification of
the spec could help address the issue.

****************************************************************************

- -- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
2926 SE Yamhill St.                Device Modeling Division
Portland, OR 97214                 13610 SW Harness Lane
503-239-5536                       Beaverton, OR 97008
http://www.teraspeed.com           503-430-1065
[email-masked]                  503-246-8048 Direct

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------------------------------

Date: Mon, 25 Aug 2003 12:48:00 -0600
From: [email-masked]
Subject: [IBIS-Users] [IBIS] Open forum minutes (08/22/03)

DATE: 8/25/03

SUBJECT: August 22, 2003 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2003 PARTICIPANTS LIST:
Ansoft Corporation             (Eric Bracken)
Apple Computer                 Kim Helliwell
Applied Simulation Technology  Fred Balistreri
Cadence Design                 Lynne Green*, Lance Wang
Cisco Systems                  Syed Huq, Michael LaBonte,
                               Val Mandruson, Hung Pham,
                               Todd Westerhoff
Fairchild Semiconductor        (Graham Connolly)
Hitachi ULSI Systems           Kazuyoshi Shoji
Intel Corporation              Stephen Peters*, Michael Mirmak*,
                               Arpad Muranyi*, Eric Magnusson
LSI Logic                      Frank Gasparik
Matsushita (Panasonic)         Atsuji Ito
Mentor Graphics                [Bob Ross], Ian Dodd, Guy de Burgh,
                               John Angulo*, Mike Donnelly, Weston Beal 
Micron Technology              Randy Wolff*
Molex Incorporated             Gus Panella
Motorola                       (Rick Kingen)
National Semiconductor         [Milt Schwartz], [Tim Coyle]
NEC Electric Corporation       (Itsuki Yamada)
Philips Semiconductor          (D.C. Sessions), Stephanie Goedecke
Siemens (& Automotive) AG      Eckhard Lenski, Michael Kindij, 
                               Burkhard Muller, Katja Koller, 
                               Andre Goerisch, Manfred Maurer, 
                               Bernard Unger, Amir Motamedi, 
                               Hartmut Ibowski, Gerald Bannert
Signal Integrity Software      Bob Haller, Barry Katz, Doug Burns
Sigrity                        [Raj Raghuram]
Synopsys                       Warren Wong, Edmund Cheng
Texas Instruments              Thomas Fisher
Teraspeed                      Scott McMorrow, Tom Dagostino,
                               Kevin Simpson, Bob Ross*
Time Domain Analysis Systems   Dima Smolyansky, Steve Corey
Zuken (& Incases)              Michael Schaeder, Ralf Bruening

OTHER PARTICIPANTS IN 2003:
Agilent Technologies           Herbert Lage
Brocade                        Frank Yuan, Yongrue Yu
Conexant                       Gary Felker
EADS CCR                       Alix de la Villeguerin
EFM                            Ekkehard Miersch
EMC Corporation                Brian Arsenault, John Fernandez,
                               Simba Julian
Fraunhofer IZM                 Ege Engin
Fujitsu                        Tadashi Arai
GEIA                           (Chris Denham)
Huawei Technologies            (Jiang Xiang Zhong)
Independent                    Kelly Green, Luca Giacotto
Infineon Tech AG               Christian Sporrer
Marvell Semiconductor          Itzik Peleg
NetLogic Microsystems          Eric Hsu
North East Systems Associates  Edward Sayre 
North Carolina State Univ.     Ambrish Varma* 
Plexus                         Joseph Socha
Politechnico de Torino         Igor Stievano
Qlogic                         Larry Barnes
Sintecs BV                     Hans Klos, Bob te Nijenhuis
SiQual                         (Rob Hinz)
Sun Microsystems               Tim Coyle
Via Technologies               (Weber Chuang)
Xilinx                         Susan Wu

In the list above, attendees at the meeting are indicated by *.  Principal
members or other active members who have not attended are in parentheses. 
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are 
as follows:

       Date           Bridge Number    Reservation #    Passcode
 September 12, 2003   1-916-356-2663        2           890-1093

All meetings are 8:00 AM to 9:55 AM Pacific Time.  Meeting agendas are
typically distributed seven days before each Open Forum.  Minutes are 
typically distributed within seven days of the corresponding meeting.
When calling into the meeting, provide the reservation number and 
passcode at the automated prompts.  If asked by an operator, please
request to join the IBIS Open Forum hosted by Michael Mirmak.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES -----------------------------------
INTRODUCTIONS AND MEETING QUORUM
No new participants.

CALL FOR PATENTS
Michael Mirmak called for any patents or pending patents related to the
IBIS Version 4.0, 4.1 or ICM specifications. No patents were declared.

MEMBERSHIP UPDATE AND TREASURER'S REPORT
Michael Mirmak reported that membership remains at 25 organizations. 
One invoice for membership is still in processing. 

REVIEW OF MINUTES AND AR'S
The August 8, 2003 meeting minutes were approved without objection.

MISCELLANY/ANNOUNCEMENTS
No new announcements.

PRESS AND WEB PAGE UPDATES
Ambrish Varma expressed some concern regarding the posting of
S2IBIS3 executables as opposed to posting a link to them.  As
the code is still under development, executables on the IBIS
web site may rapidly become stale.  At present, only a link to 
the S2IBIS3 page at North Carolina State is planned for the
IBIS site.

NEW MODELS AVAILABLE, LIBRARY UPDATE
Bob Ross reported that he had received three new IBIS model links
which have been forwarded to Roy Leventhal for inclusion on the
IBIS web site model library.  Michael accepted the AR to confirm
with Roy his schedule for model page updates.

OPENS FOR NEW ISSUES
No new issues.

INTERNATIONAL/EXTERNAL PROGRESS
- - IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal
  (formerly, IEC 93/67/NP IBIS and EMC Simulation)
  No update.
- - JEDEC Activity Report
Lynne Green reported that she has been invited to present a one-day
short course on IBIS and IBIS modeling during the JEDEC spring meeting.
A presentation link will be posted on the IBIS Open Forum web site.

DATE/PCB EAST SUMMIT DISCUSSION
Lynne Green has distributed a first call for papers to the PCB East
IBIS Summit.  She noted that a few presentation titles and subjects have 
already been forwarded to her.  Michael Mirmak described his 
conversation with Kathy Breda of NESA.  NESA has confirmed that they
will host the IBIS Summit on Tuesday, October 21.  Kathy is the 
contact for summit registrations.  Lynne and Michael will meet
with Kathy via teleconference before the next Open Forum to finalize
room and refreshment/lunch arrangements.  Ambrish Varma indicated
that he may be able to present on S2IBIS3 development.

DESIGNCON SUMMIT DISCUSSION
Michael Mirmak reported that an updated draft contract with the IEC for
co-sponsorship of DesignCon 2004 has been received.  The summit date
of Monday, Feb. 2, 2004 has been confirmed, with a room and audiovisual
equipment.  However, separate refreshments continue to be a problem.
A teleconference is not anticipated.

In addition, sponsors are needed for lunches at both PCB East and 
DesignCon 2004.  Open Forum members and participants are encouraged to 
inquire at their organizations regarding co-sponsorship of the summit.  
Sponsors will be prominently mentioned in Summit presentations,
announcements, and the minutes.  

IBIS VERSION 4.0 PARSER FUNDING AND STATUS
Michael Mirmak reported that payment from one parser sponsor has not
yet been confirmed by the GEIA.  Only a few issues remain to be resolved
in the latest beta version of the parser (see the BUG discussion below).
Parser code from the current beta has been provided to all paid sponsors.

A beta version of IBISCHK4 is available for download:

http://www.vhdl.org/pub/ibis/ibischk4_beta

IBIS QUALITY COMMITTEE
Bob Ross reported that meetings continue every two weeks.

IBIS MODEL REVIEW COMMITTEE
Lynne Green reported that no new models have been received by the 
committee since the last Open Forum meeting.

NEW ADMINISTRATIVE ISSUES
No new issues.

S2IBIS3
Ambrish Varma reported that work continues on S2IBIS3 development.
NMOS code has been completed, with PMOS work underway.

S2IBIS3 beta executables can be downloaded from:

http://www.ece.ncsu.edu/erl/ibis/s2ibis3/s2ibis3.htm

Feedback on the current beta version is appreciated and encouraged.

WEB PAGE DISCUSSION
Discussion of potential domain and format changes for the IBIS web site
was deferred until the next Open Forum meeting.

BIRD82.1 - Clarification of Clamp Tables
Lynne Green reintroduced BIRD82.1 and mentioned a change requested by
Bob Haller to the BIRD text.  After discussion, the BIRD was amended
to change the opening sentence to read, "It is intended that both 
[Power Clamp] and [GND Clamp] tables..."

Lynne noted that the BIRD was intended to be incorporated into IBIS 4.1.
The BIRD was approved as amended unanimously.  The text will be posted 
with changes as BIRD82.2.

CLARIFICATION BIRD DISCUSSION
Michael Mirmak introduced two issues related to series elements discovered
during model validation at Intel Corp.  The 4.0 specification does not
clearly state whether the [Series MOSFET] keyword must be present for
each occurrence of the "Vds" subparameter and accompanying data table.
Using only one [Series MOSFET] keyword with multiple Vds subparameters
is seen as an error by the current parser.  Michael proposed that this 
parsing rule be made explicit in the specification.  Stephen Peters and
Bob Ross noted that other keywords force multiple occurrences of keywords
with data tables; for example, [Rising Waveform] must appear for each
rising data table under the [Model] keyword.  

In addition, Michael noted that the [Series Pin Mapping] keyword makes the
column function_table_groups optional, so that the operation of series
switch enables may be described.  However, the use of function_table_groups
for switches implies the need for [Series Switch Groups], which the 
specification describes as simply not required.  Michael proposed that 
[Series Switch Groups] be required if function_table_groups is used.  Again,
the current parser assumes that both must be present for correctly written
series switch models.  Bob Ross observed that any clarification BIRD written
to address these issues would likely be assigned as BIRD83, and should be 
made as unobtrusive as possible to prevent problems approving IBIS 4.1.

IBIS VERSION 4.1 DISCUSSION
John Angulo updated the Open Forum on his work in developing an expansion
of the [Ramp] keyword, for use with the 4.1 multilingual extensions.  The
task is complicated by the fact that [Ramp] carries several assumptions
regarding load termination (to what voltage is it connected) and type
(is the load single-ended, differential, etc.).  In addition, the [Ramp]
keyword is frequently misused in currently available models, often
expressing a slew rate instead of the actual 20-80% voltage and
transition time required by the specification.   Stephen Peters advocated
keeping the [Ramp] keyword as currently required in 4.0, but some
members noted that this would not accommodate differential technologies
properly.  Bob Ross and Michael Mirmak also noted that, even with
changes to address differentials, [Ramp] would still be inadequate for
any future technologies modeled using the multilingual extensions.
John Angulo accepted the AR to defer on writing specific keyword
language.  Instead, he will present the algorithmic requirements of 
tools which use the [Ramp] keyword for crosstalk and timestep
analysis.  These can be generalized for either a revised [Ramp] or
a new keyword by the Open Forum.

A draft version of IBIS version 4.1 is available on the web.  Both an 
ASCII text and an Adobe PDF version are available at:

  http://www.vhdl.org/pub/ibis/wip/

IBIS ICM SPECIFICATION REVIEW
Michael Mirmak announced the second "reading" of the ICM specification 
and called for comment.  No comments have been received since the last
IBIS Summit.  A vote on ICM approval is scheduled for Sept. 12.  

IBISCHK4 & BUG TRACKING STATUS
Michael Mirmak noted that only five BUGs remain unresolved in the latest
3.2 parser and inquired about their status in the beta 4.0 parser.  Of 
these five, BUG68 and BUG73 have been checked using 4.0 and do not yet 
appear to have been addressed.  BUG75 and BUG76 require inclusion of
new parser code and checking using special compilations of the parser.
Bob Ross observed that BUG71 may not have been properly addressed in 4.0, 
as the rule for non-monotonic checking which it created may not have been 
clearly expressed to the parser developer.  For IBIS 3.x models,
individual tables are checked for non-monotonicities.  The new rule for
IBIS 4.x models involves combining tables.  John Angulo noted that
there are still small, OS-dependent printing issues with the parser and
that some kinds of non-monotonic warnings appear twice in the beta.
Michael accepted the AR to communicate the state of the last five BUGs to
the parser developer and to request an update.

The beta version of IBISCHK4 is available at:

http://www.vhdl.org/pub/ibis/ibischk4_beta

BUG80 - [Model Selector] and [Diff Pin] Ordering
John Angulo introduced BUG80, which identifies that the parser observes
an implicit rule about the proper ordering of [Model Selector] with
respect to the placement of the [Pin] and [Diff Pin] keywords.  No rules
regarding the placement of these keywords is explicitly described in the
specification, although one is implied by the IBIS tree hierarchy.  As
the issue may be the result of a specification ambiguity, classification
of the BUG was deferred.  A discussion of the ordering issue will be
placed on the agenda for the next Open Forum.

NEXT MEETING:
The next teleconference has been scheduled for September 12 from 8:00 AM 
to 10:00 AM Pacific Daylight Time.  A vote on the ICM specification
is scheduled.

============================================================================
                               NOTES

IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-1046
            [email-masked]
            Senior Analog Engineer, Intel Corporation
            M/S FM6-45
            1900 Prairie City Rd.
            Folsom, CA  95630

VICE CHAIR: Lynne Green (425) 788-0412, Fax (425) 451-1871
            [email-masked]
            Senior Modeling Engineer, Cadence Design Systems
            320 120th Ave NE, Suite B-103, Bellevue, WA 98005-3016

SECRETARY:  Randy Wolff (208) 363-1764, Fax: (208) 368-3475
            [email-masked]
            Simulation Engineer, Micron Technology, Inc.
            8000 S. Federal Way
            Mail Stop: 1-711
            Boise, ID 83707-0006
        
LIBRARIAN:  Roy Leventhal (847) 590-9398
            [email-masked]
            Consultant, Leventhal Design and Communications
            1924 North Burke Drive
            Arlington Heights, Illinois 60004

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            [email-masked]
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 497-5077, Fax: (425) 881-1008
            [email-masked]
            Development Engineer, Mentor Graphics
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

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------------------------------

Date: Mon, 25 Aug 2003 16:21:49 -0400
From: "Allen Chao" <[email-masked]>
Subject: [none]

This is a multi-part message in MIME format.

- ------=_NextPart_000_0006_01C36B24.FC65A3A0
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: 7bit

Hi IBIS experts,
I have a 5V-short protection in my device and that causes my pull-up,
pull-down, and power clamp curves not acting monotonic.
I've attached the curves below.

Any suggestion for this kind of circuit? or it's ok to leave it like this?

Thanks in advance,
Allen Chao

- ------=_NextPart_000_0006_01C36B24.FC65A3A0
Content-Type: application/octet-stream;
	name="pull-down.jpg"
Content-Transfer-Encoding: base64
Content-Disposition: attachment;
	filename="pull-down.jpg"

- ------=_NextPart_000_0006_01C36B24.FC65A3A0
Content-Type: application/octet-stream;
	name="pull-up.jpg"
Content-Transfer-Encoding: base64
Content-Disposition: attachment;
	filename="pull-up.jpg"

- ------=_NextPart_000_0006_01C36B24.FC65A3A0
Content-Type: application/octet-stream;
	name="power_clamp.jpg"
Content-Transfer-Encoding: base64
Content-Disposition: attachment;
	filename="power_clamp.jpg"

- ------=_NextPart_000_0006_01C36B24.FC65A3A0
Content-Type: application/octet-stream;
	name="gnd_clamp.jpg"
Content-Transfer-Encoding: base64
Content-Disposition: attachment;
	filename="gnd_clamp.jpg"

- ------=_NextPart_000_0006_01C36B24.FC65A3A0--

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------------------------------

End of ibis-users V1 #29
************************