Subject: ibis-users V1 #5
From: owner-ibis-users@ (ibis-users)
To: [email-masked]

ibis-users           Wednesday, May 1 2002           Volume 01 : Number 005

----------------------------------------------------------------------

Date: Wed, 20 Mar 2002 01:36:29 -0800
From: [email-masked]
Subject: [IBIS-Users] Report to Recipient(s)

Incident Information:-

Originator:    [email-masked]
Recipients:    [email-masked]
Subject:  [IBIS-Users] Happy nice Lady Day

WARNING:  The file You can find technical info in this folder.pif you
received was infected with the W32/Klez.gen@MM virus.  The file attachment
was not successfully cleaned.

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------------------------------

Date: Wed, 20 Mar 2002 02:04:10 -0800
From: System Attendant <[email-masked]>
Subject: [IBIS-Users] ScanMail Message: To Recipient virus found and action taken.

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------------------------------

Date: Sat, 23 Mar 2002 14:26:59 -0800 (PST)
From: whiz kid <[email-masked]>
Subject: [IBIS-Users] IBIS Question.

Hi folks,
I have some dumb questions.
1) How can I identify the value of the pullup resistor
being modeled by looking at the Pullup and the
Powerclamp values.
2) Why do we need to use different fixture voltages
when specifing the Rising and Falling waveforms.

Any help is greatly appreciated.

Thanks,
Rahul. 

__________________________________________________
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------------------------------

Date: Sun, 24 Mar 2002 17:30:57 -0500
From: John Angulo <[email-masked]>
Subject: [IBIS-Users] List posting now closed to non-members

Hello,

Due to the recent surge in spam and virus related emails, posting to the
IBIS lists is now restricted to list members.  This has
already stopped some inappropriate mail to the lists.

Be aware that the following posts to the IBIS lists on 3/20/02 contained a
virus:

From: "nutwooduk" <[email-masked]>
To: <[email-masked]>
Subject: [IBIS] Have a excite Lady Day
Date: Wednesday, March 20, 2002 1:46 AM

From: "QA_Engr4" <[email-masked]>
To: <[email-masked]>
Subject: [IBIS-Users] Happy nice Lady Day
Date: Wednesday, March 20, 2002 1:46 AM

The other unwanted traffic on 3/20 consisted of automated warnings about
this threat from the service providers of several list
members.

Under the new restricted posting policy, if you send email to the list,
remember to use the exact address with which you subscribed.
Otherwise, the list administration software will not allow the post. It will
forward the email to me as a non-member attempt to
post.  In this event, I will send the email to the list myself and notify
you of the problem.  Domain reorganizations within a
company frequently lead to unexpected changes in email addresses, so I will
be monitoring this issue carefully.

In the future, if a list member becomes infected with a virus, and either of
the IBIS lists ever becomes overwhelmed by the
resulting traffic, we will temporarily moderate all postings until the
problem is resolved.

These policies should keep the lists clean.  Thanks for your patience with
yesterday's flurry of unwanted email.  Please respond to
me directly with any feedback.

John Angulo
IBIS Open Forum Postmaster

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------------------------------

Date: Mon, 25 Mar 2002 12:54:59 -0500
From: Jon Powell <[email-masked]>
Subject: RE: [IBIS-Users] IBIS Question.

You should NOT be using different fixture voltages for RISING and
FALLING in most model cases.

You should be using 2 voltages and making two rising and two
falling waveforms.

For standard 5 volts CMOS you use:
50 ohms to 5 volts and
50 ohms to 0 volts

it is actually very important to the simulation math that you
have the same voltages in both sets of waveforms.

have fun
Jon Powell

> -----Original Message-----
> From: whiz kid [mailto:[email-masked]]
> Sent: Saturday, March 23, 2002 2:27 PM
> To: [email-masked]
> Subject: [IBIS-Users] IBIS Question.
> 
> 
> Hi folks,
> I have some dumb questions.
> 1) How can I identify the value of the pullup resistor
> being modeled by looking at the Pullup and the
> Powerclamp values.
> 2) Why do we need to use different fixture voltages
> when specifing the Rising and Falling waveforms.
> 
> Any help is greatly appreciated.
> 
> Thanks,
> Rahul. 
> 
> __________________________________________________
> Do You Yahoo!?
> Yahoo! Movies - coverage of the 74th Academy Awards®
> http://movies.yahoo.com/
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------------------------------

Date: Mon, 25 Mar 2002 14:46:56 -0600
From: Gang Huo <[email-masked]>
Subject: [IBIS-Users] IBIS and HSPICE simulation result question

Hi All,

When I try to correlate a IBIS I/O model simulation with HSPICE model
using HSPICE version 2000.4,  the result is pretty good on the standard
load and open transmission line load. One thing concerns me is that in
the simulation of a load of transmission line to receiver simulation,
the overshoot level of the signal is much higher when using the IBIS
model than the HSPICE model, (the difference between two case is 0.5V
nominal and 0.7V in best case, this is a 3.3v I/O buffer).

I doubt this may be because of the clamp tables in the IBIS model. But
as the creator of the model, I am pretty confident that the clamp tables
in the IBIS model are correct, so can someone give me an idea what else
in the IBIS model may cause this? Will this cause a problem to the
users? And is there any good way to address this issue when creating the
models?

Thanks in advance,
Gang Huo

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------------------------------

Date: Tue, 26 Mar 2002 11:34:02 -0800
From: "Jeremy Plunkett" <[email-masked]>
Subject: RE: [IBIS-Users] IBIS and HSPICE simulation result question

Gang,
the IBIS model clamps will only affect the level of overshoot when the model
you created is the receiver.  If you are driving the model output into a
transmission line test load, the level of overshoot at the end of the line
will depend on the  edge rate and output impedance of your IBIS model, but
not on the clamps.

I do a correlation check into a test load that matches the termination
conditions that the driver will see in use, and correlate the waveform at
_the driver's own output pad_ before looking at anything else.  If the
driver will be used on a terminated bus like DDR or GTL, use a test load
that is a resistor equal to the transmission line impedance, connected to
the termination voltage level.  If the driver will be driving from the
middle of a terminated bus, divide the transmission line impedance by two
since the driver actually drives 2 transmission lines in parallel.  If the
driver will be used on unterminated lines, than the load should be a pullup
or pulldown resistor equal to the nominal trace impedance.

If your extraction was accurate, you should see near-perfect correlation of
the output waveform into these loads.  In particular, if you do a
correlation into the same loads that are used for the IBIS model VT curves
(usually 50 ohms pullup and pulldown), and you don't see 99% perfect
correlation, then there is definitely a problem with either the model or
your simulation setup.

Good luck, hope this helped!

Jeremy

|>--/\/\/--((((((((()--|>

Jeremy Plunkett
Signal Integrity Engineer
ServerWorks Corp
www.serverworks.com

|>--/\/\/--((((((((()--|>

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On Behalf Of
Gang Huo
Sent: Monday, March 25, 2002 12:47 PM
To: [email-masked]
Subject: [IBIS-Users] IBIS and HSPICE simulation result question

Hi All,

When I try to correlate a IBIS I/O model simulation with HSPICE model
using HSPICE version 2000.4,  the result is pretty good on the standard
load and open transmission line load. One thing concerns me is that in
the simulation of a load of transmission line to receiver simulation,
the overshoot level of the signal is much higher when using the IBIS
model than the HSPICE model, (the difference between two case is 0.5V
nominal and 0.7V in best case, this is a 3.3v I/O buffer).

I doubt this may be because of the clamp tables in the IBIS model. But
as the creator of the model, I am pretty confident that the clamp tables
in the IBIS model are correct, so can someone give me an idea what else
in the IBIS model may cause this? Will this cause a problem to the
users? And is there any good way to address this issue when creating the
models?

Thanks in advance,
Gang Huo

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------------------------------

Date: Tue, 26 Mar 2002 14:11:10 -0600
From: Gang Huo <[email-masked]>
Subject: Re: [IBIS-Users] IBIS and HSPICE simulation result question

Hi, All

Thank Jeremy for your response.

I should clear myself, the simulation with problem is a driver drive a
transmission then to the same I/O cell as the receiver. The simulation shows
good correlation when driving a open transmission line or a 50 Ohm load.

Well, I got a 'extreme currents present in GND clamp curve' warning when
running ibischk3 (around 30A). I know this is highly likely due to the
'perfect' diode with no intrinsic resistance in the HSPICE model per IBIS
cookbook. And the IBIS model may not correlate with the real buffer
performance, but I am surprised it did not correlate well with the HSPICE model
simulation in this case, since the IBIS model is derived from the same HSPICE
model I used.

Without further information on the diode information, is there a good way to
solve the problem? Will adding a small resistor with a fixed value (say 5-7
Ohm) do the trick?

Thanks in advance.
Huo,Gang

Jeremy Plunkett wrote:

> Gang,
> the IBIS model clamps will only affect the level of overshoot when the model
> you created is the receiver.  If you are driving the model output into a
> transmission line test load, the level of overshoot at the end of the line
> will depend on the  edge rate and output impedance of your IBIS model, but
> not on the clamps.
>
> I do a correlation check into a test load that matches the termination
> conditions that the driver will see in use, and correlate the waveform at
> _the driver's own output pad_ before looking at anything else.  If the
> driver will be used on a terminated bus like DDR or GTL, use a test load
> that is a resistor equal to the transmission line impedance, connected to
> the termination voltage level.  If the driver will be driving from the
> middle of a terminated bus, divide the transmission line impedance by two
> since the driver actually drives 2 transmission lines in parallel.  If the
> driver will be used on unterminated lines, than the load should be a pullup
> or pulldown resistor equal to the nominal trace impedance.
>
> If your extraction was accurate, you should see near-perfect correlation of
> the output waveform into these loads.  In particular, if you do a
> correlation into the same loads that are used for the IBIS model VT curves
> (usually 50 ohms pullup and pulldown), and you don't see 99% perfect
> correlation, then there is definitely a problem with either the model or
> your simulation setup.
>
> Good luck, hope this helped!
>
> Jeremy
>
> |>--/\/\/--((((((((()--|>
>
> Jeremy Plunkett
> Signal Integrity Engineer
> ServerWorks Corp
> www.serverworks.com
>
> |>--/\/\/--((((((((()--|>
>
> -----Original Message-----
> From: [email-masked] [mailto:[email-masked]]On Behalf Of
> Gang Huo
> Sent: Monday, March 25, 2002 12:47 PM
> To: [email-masked]
> Subject: [IBIS-Users] IBIS and HSPICE simulation result question
>
> Hi All,
>
> When I try to correlate a IBIS I/O model simulation with HSPICE model
> using HSPICE version 2000.4,  the result is pretty good on the standard
> load and open transmission line load. One thing concerns me is that in
> the simulation of a load of transmission line to receiver simulation,
> the overshoot level of the signal is much higher when using the IBIS
> model than the HSPICE model, (the difference between two case is 0.5V
> nominal and 0.7V in best case, this is a 3.3v I/O buffer).
>
> I doubt this may be because of the clamp tables in the IBIS model. But
> as the creator of the model, I am pretty confident that the clamp tables
> in the IBIS model are correct, so can someone give me an idea what else
> in the IBIS model may cause this? Will this cause a problem to the
> users? And is there any good way to address this issue when creating the
> models?
>
> Thanks in advance,
> Gang Huo
>
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------------------------------

Date: Tue, 26 Mar 2002 13:49:59 -0800
From: "Jeremy Plunkett" <[email-masked]>
Subject: RE: [IBIS-Users] IBIS and HSPICE simulation result question

hi,
not sure if I should address you by Huo or Gang...let me know?

sorry for the misunderstanding, if your model is both the source and
reciever then your input clamps are the determining factor.  I am surprised
that the IBIS model would should higher over/undershoot than the spice
model; typically if there is any error it is double-counting the clamp
current(clamps end up 2x as strong as the spice deck), not undercounting it.

When you are testing the model, do you have the hspice B element set up with
power=on or power=off?  It might be worth your while to try both settings
and compare the results.  Also, make sure that you have all necessary and
optional nodes and voltages defined for the model type you are using.  Don't
leave out the supply connections for the power clamp and ground clamp, not
all hspice versions include them as a default, no matter what the manual may
say.

Also, check that the buffer capacitance is the same between the ibis model
and spice deck at the process and temperature you are using.  Capacitance
can vary significantly between process corners and even as the pad voltage
varies from one supply rail to the other and especially beyond the rails;
the IBIS format is not flexible enough to represent this at the present
time.  If the capacitance of the spice model in the conditions at the pad
when the overshoot occurs is significantly higher than the capacitance
specified in the IBIS model, then you will see higher overshoot in the IBIS
model even though the diode IV curves were extracted correctly.

Regarding the diode resistance, if you have the physical part in hand or
even just similar parts made in the same process, you can measure the diode
clamp resistance(for one case of process, and at room temperature) fairly
easily.  Just connect the part to it's standard supplies (but preferably not
to any other valuable circuitry), and connect a variable voltage pulse
source to a tristated signal pin.  Set the pulse source to drive the signal
pad beyond the rail with a duty cycle of not more than 10%, and measure the
current flowing into the part by measuring the voltage at the pin with an
oscilloscope.  The pulse source has a 50ohm output, so the voltage you
measure at the pin will not be the voltage that you set up on the front
panel.  Measure the peak of that voltage (it should be a square/rectangular
waveform), and calculate the clamp current as Ic=(2xVf-VL)/50 where Ic=clamp
current, Vf=pulse voltage set at the front panel, and VL=peak voltage
measured at the pin.  Measure the clamp current for pin voltages of 1v and
2v past the rail, then calculate the clamp resistance as Rc=1/(I1-I2), where
I1 and I2 are the respective current readings.

regards,
Jeremy

|>--/\/\/--((((((((()--|>

Jeremy Plunkett
Signal Integrity Engineer
ServerWorks Corp
www.serverworks.com

|>--/\/\/--((((((((()--|>

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]
Sent: Tuesday, March 26, 2002 12:11 PM
To: Jeremy Plunkett
Cc: [email-masked]
Subject: Re: [IBIS-Users] IBIS and HSPICE simulation result question

Hi, All

Thank Jeremy for your response.

I should clear myself, the simulation with problem is a driver drive a
transmission then to the same I/O cell as the receiver. The simulation shows
good correlation when driving a open transmission line or a 50 Ohm load.

Well, I got a 'extreme currents present in GND clamp curve' warning when
running ibischk3 (around 30A). I know this is highly likely due to the
'perfect' diode with no intrinsic resistance in the HSPICE model per IBIS
cookbook. And the IBIS model may not correlate with the real buffer
performance, but I am surprised it did not correlate well with the HSPICE
model
simulation in this case, since the IBIS model is derived from the same
HSPICE
model I used.

Without further information on the diode information, is there a good way to
solve the problem? Will adding a small resistor with a fixed value (say 5-7
Ohm) do the trick?

Thanks in advance.
Huo,Gang

Jeremy Plunkett wrote:

> Gang,
> the IBIS model clamps will only affect the level of overshoot when the
model
> you created is the receiver.  If you are driving the model output into a
> transmission line test load, the level of overshoot at the end of the line
> will depend on the  edge rate and output impedance of your IBIS model, but
> not on the clamps.
>
> I do a correlation check into a test load that matches the termination
> conditions that the driver will see in use, and correlate the waveform at
> _the driver's own output pad_ before looking at anything else.  If the
> driver will be used on a terminated bus like DDR or GTL, use a test load
> that is a resistor equal to the transmission line impedance, connected to
> the termination voltage level.  If the driver will be driving from the
> middle of a terminated bus, divide the transmission line impedance by two
> since the driver actually drives 2 transmission lines in parallel.  If the
> driver will be used on unterminated lines, than the load should be a
pullup
> or pulldown resistor equal to the nominal trace impedance.
>
> If your extraction was accurate, you should see near-perfect correlation
of
> the output waveform into these loads.  In particular, if you do a
> correlation into the same loads that are used for the IBIS model VT curves
> (usually 50 ohms pullup and pulldown), and you don't see 99% perfect
> correlation, then there is definitely a problem with either the model or
> your simulation setup.
>
> Good luck, hope this helped!
>
> Jeremy
>
> |>--/\/\/--((((((((()--|>
>
> Jeremy Plunkett
> Signal Integrity Engineer
> ServerWorks Corp
> www.serverworks.com
>
> |>--/\/\/--((((((((()--|>
>
> -----Original Message-----
> From: [email-masked] [mailto:[email-masked]]On Behalf
Of
> Gang Huo
> Sent: Monday, March 25, 2002 12:47 PM
> To: [email-masked]
> Subject: [IBIS-Users] IBIS and HSPICE simulation result question
>
> Hi All,
>
> When I try to correlate a IBIS I/O model simulation with HSPICE model
> using HSPICE version 2000.4,  the result is pretty good on the standard
> load and open transmission line load. One thing concerns me is that in
> the simulation of a load of transmission line to receiver simulation,
> the overshoot level of the signal is much higher when using the IBIS
> model than the HSPICE model, (the difference between two case is 0.5V
> nominal and 0.7V in best case, this is a 3.3v I/O buffer).
>
> I doubt this may be because of the clamp tables in the IBIS model. But
> as the creator of the model, I am pretty confident that the clamp tables
> in the IBIS model are correct, so can someone give me an idea what else
> in the IBIS model may cause this? Will this cause a problem to the
> users? And is there any good way to address this issue when creating the
> models?
>
> Thanks in advance,
> Gang Huo
>
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------------------------------

Date: Wed, 27 Mar 2002 10:57:40 -0500
From: "Timothy Coyle" <[email-masked]>
Subject: [IBIS-Users] Positive Ground Clamp Curve

This is a multipart message in MIME format.
- --=_alternative 0058118085256B89_=
Content-Type: text/plain; 
 charset=us-ascii
Content-Transfer-Encoding: 7bit

I am trying to gain ground clamp curve data for an input buffer.  I do a 
DC sweep on the input pin and measure the current. However,
I get positive current. I am using HSPICE.  Is there a current convention 
thing going on in HSPICE or is something else wrong? 
Thanks in advance for any info.

Tim

- --=_alternative 0058118085256B89_=
Content-Type: text/html; 
 charset=us-ascii
Content-Transfer-Encoding: 7bit

<br><font size=2 face="sans-serif">I am trying to gain ground clamp curve data for an input buffer. &nbsp;I do a DC sweep on the input pin and measure the current. However,</font>
<br><font size=2 face="sans-serif">I get positive current. I am using HSPICE. &nbsp;Is there a current convention thing going on in HSPICE or is something else wrong? </font>
<br><font size=2 face="sans-serif">Thanks in advance for any info.</font>
<br>
<br><font size=2 face="sans-serif">Tim</font>
<br>
- --=_alternative 0058118085256B89_=--

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------------------------------

Date: Wed, 27 Mar 2002 09:07:56 -0800
From: "Muranyi, Arpad" <[email-masked]>
Subject: RE: [IBIS-Users] Positive Ground Clamp Curve

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C1D5B1.F09D1A80
Content-Type: text/plain;
	charset="iso-8859-1"

Tim,
 
Yes, there is.  I usually do it this way:
 
Arpad
======================================================================

 
3-state I-V plot generator
**********************************************************************
* This is a I-V curve generator for input or 3-stated buffers.
* It runs in transient mode and shows the I-V curve in the same
* orientation as it is seen on a curve tracer.
**********************************************************************
.OPTIONS POST=1 PROBE
.PROBE TRAN Voltage=V(Sweep) Pulldown=I(Vsweep)
.TRAN 0.1ms 198ms
**********************************************************************
.param Vcc_DC=3.3
**********************************************************************
Vpow   Vcc 0 DC=Vcc_DC
Vsweep 0 Sweep PWL 0ns 3.3V 198ms -6.6V
**********************************************************************
X1 0     Sweep  Vcc   0   0      BUFFER_SUBCKT_NAME
*  input output power GND enable
**********************************************************************
.END
**********************************************************************

- -----Original Message-----
From: Timothy Coyle [mailto:[email-masked]]
Sent: Wednesday, March 27, 2002 7:58 AM
To: [email-masked]
Subject: [IBIS-Users] Positive Ground Clamp Curve

I am trying to gain ground clamp curve data for an input buffer.  I do a DC
sweep on the input pin and measure the current. However, 
I get positive current. I am using HSPICE.  Is there a current convention
thing going on in HSPICE or is something else wrong? 
Thanks in advance for any info. 

Tim 

- ------_=_NextPart_001_01C1D5B1.F09D1A80
Content-Type: text/html;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">

<META content=3D"MSHTML 5.50.4725.2100" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D081040517-27032002>Tim,</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D081040517-27032002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D081040517-27032002>Yes, there=20
is.&nbsp; I usually do it this way:</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D081040517-27032002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D081040517-27032002>Arpad</DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D081040517-27032002>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D</SPAN></FONT></DIV></SPAN></FONT>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D081040517-27032002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D081040517-27032002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN=20
class=3D081040517-27032002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D081040517-27032002>3-state I-V=20
plot=20
generator<BR>***********************************************************=
***********<BR>*=20
This is a I-V curve generator for input or 3-stated buffers.<BR>* It =
runs in=20
transient mode and shows the I-V curve in the same<BR>* orientation as =
it is=20
seen on a curve=20
tracer.<BR>*************************************************************=
*********<BR>.OPTIONS=20
POST=3D1 PROBE<BR>.PROBE TRAN Voltage=3DV(Sweep) =
Pulldown=3DI(Vsweep)<BR>.TRAN 0.1ms=20
198ms<BR>***************************************************************=
*******<BR>.param=20
Vcc_DC=3D3.3<BR>********************************************************=
**************<BR>Vpow&nbsp;&nbsp;=20
Vcc 0 DC=3DVcc_DC<BR>Vsweep 0 Sweep PWL 0ns 3.3V 198ms=20
- -6.6V<BR>***************************************************************=
*******<BR>X1=20
0&nbsp;&nbsp;&nbsp;&nbsp; Sweep&nbsp; =
Vcc&nbsp;&nbsp;&nbsp;0&nbsp;&nbsp;=20
0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; BUFFER_SUBCKT_NAME</SPAN></FONT></DIV>
<DIV><FONT face=3D"Courier New" size=3D2><SPAN =
class=3D081040517-27032002>*&nbsp;=20
input output power GND=20
enable<BR>**************************************************************=
********<BR>.END<BR>****************************************************=
******************<BR></DIV></SPAN></FONT>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Timothy Coyle=20
[mailto:[email-masked]]<BR><B>Sent:</B> Wednesday, March 27, =
2002 7:58=20
AM<BR><B>To:</B> [email-masked]<BR><B>Subject:</B> =
[IBIS-Users]=20
Positive Ground Clamp Curve<BR><BR></FONT></DIV><BR><FONT =
face=3Dsans-serif=20
size=3D2>I am trying to gain ground clamp curve data for an input =
buffer. &nbsp;I=20
do a DC sweep on the input pin and measure the current. However,</FONT> =

<BR><FONT face=3Dsans-serif size=3D2>I get positive current. I am using =
HSPICE.=20
&nbsp;Is there a current convention thing going on in HSPICE or is =
something=20
else wrong? </FONT><BR><FONT face=3Dsans-serif size=3D2>Thanks in =
advance for any=20
info.</FONT> <BR><BR><FONT face=3Dsans-serif size=3D2>Tim</FONT> =
<BR></BODY></HTML>

- ------_=_NextPart_001_01C1D5B1.F09D1A80--
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------------------------------

Date: Wed, 27 Mar 2002 15:41:03 -0800
From: "Sanchez, Louis" <[email-masked]>
Subject: [IBIS-Users] Temperature Range:

Hello..............

I have a question regarding the proper format to use for the IBIS model
keyword:[Temperature Range]. According to version 3.2 of the EIA IBIS
Standard, the format is: typ, min, and max. The example given on page 29 of
the referenced standard is: typ: 27.0, min: -50, max: 130.0. Yet, I have
seen IBIS models from various sources that specify the min temperature as
high, in this case 130; and the max temperature as low, in this case -50.
Can someone comment on what the proper entry should be? I tend to believe
the standard, but I have seen so many IBIS files with the min and max
entries reversed that I just had to ask.

Thank You,
Louis A. Sanchez
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------------------------------

Date: Wed, 27 Mar 2002 16:02:56 -0800
From: "Mirmak, Michael" <[email-masked]>
Subject: RE: [IBIS-Users] Temperature Range:

Louis,

The {Temperature Range] keyword values are ordered depending on conditions,
not on numerical value (unlike C_comp).  In other words, your "min"
temperature value corresponds to the temperature used to get the "min" data,
not the smallest numerical temperature in your range.

Section 9 of the specification details Data Derivation methods and points
out that, for CMOS processes, "min" corner usually corresponds to high
temeratures, while the "max" corner corresponds to low temperatures.
Bipolar technologies, on the other hand, typically show association between
"min" corner and low temperature, etc.

While not so noted, I believe the spec example refers to a bipolar buffer.

I hope this helps!

- - Michael Mirmak, Intel Corp.

- -----Original Message-----
From: Sanchez, Louis [mailto:[email-masked]]
Sent: Wednesday, March 27, 2002 3:41 PM
To: [email-masked]'
Subject: [IBIS-Users] Temperature Range:

Hello..............

I have a question regarding the proper format to use for the IBIS model
keyword:[Temperature Range]. According to version 3.2 of the EIA IBIS
Standard, the format is: typ, min, and max. The example given on page 29 of
the referenced standard is: typ: 27.0, min: -50, max: 130.0. Yet, I have
seen IBIS models from various sources that specify the min temperature as
high, in this case 130; and the max temperature as low, in this case -50.
Can someone comment on what the proper entry should be? I tend to believe
the standard, but I have seen so many IBIS files with the min and max
entries reversed that I just had to ask.

Thank You,
Louis A. Sanchez
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|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Wed, 27 Mar 2002 19:12:16 -0500
From: "Lynne Green" <[email-masked]>
Subject: RE:  [IBIS-Users] Temperature Range:

Hello, Louis,

This is described in the IBIS 3.2 spec:
| The optional [Temperature Range] keyword will contain the temperature which
| causes or amplifies the slow, weak conditions in the "min" column and the
| temperature which causes or amplifies the fast, strong conditions in the
| "max" column.  Therefore, the "min" column for [Temperature Range] will
| contain the lowest value for bipolar models (TTL and ECL) and the highest
| value for CMOS models.

You are probably seeing some CMOS models and some bipolar models.

- - Lynne

- -----Original Message-----
From: Sanchez, Louis [mailto:[email-masked]]
Sent: Wednesday, March 27, 2002 3:41 PM
To: [email-masked]'
Subject: [IBIS-Users] Temperature Range:

Hello..............

I have a question regarding the proper format to use for the IBIS model
keyword:[Temperature Range]. According to version 3.2 of the EIA IBIS
Standard, the format is: typ, min, and max. The example given on page 29 of
the referenced standard is: typ: 27.0, min: -50, max: 130.0. Yet, I have
seen IBIS models from various sources that specify the min temperature as
high, in this case 130; and the max temperature as low, in this case -50.
Can someone comment on what the proper entry should be? I tend to believe
the standard, but I have seen so many IBIS files with the min and max
entries reversed that I just had to ask.

Thank You,
Louis A. Sanchez
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------------------------------

Date: Wed, 27 Mar 2002 16:14:38 -0800
From: "Sanchez, Louis" <[email-masked]>
Subject: RE: [IBIS-Users] Temperature Range:

Hi..............

I want to thank all who responded. These inputs cleared up my confusion.

Thanks,

Lou A. Sanchez

- -----Original Message-----
From: Mirmak, Michael 
Sent: Wednesday, March 27, 2002 4:03 PM
To: Sanchez, Louis; [email-masked]'
Subject: RE: [IBIS-Users] Temperature Range:

Louis,

The {Temperature Range] keyword values are ordered depending on conditions,
not on numerical value (unlike C_comp).  In other words, your "min"
temperature value corresponds to the temperature used to get the "min" data,
not the smallest numerical temperature in your range.

Section 9 of the specification details Data Derivation methods and points
out that, for CMOS processes, "min" corner usually corresponds to high
temeratures, while the "max" corner corresponds to low temperatures.
Bipolar technologies, on the other hand, typically show association between
"min" corner and low temperature, etc.

While not so noted, I believe the spec example refers to a bipolar buffer.

I hope this helps!

- - Michael Mirmak, Intel Corp.

- -----Original Message-----
From: Sanchez, Louis [mailto:[email-masked]]
Sent: Wednesday, March 27, 2002 3:41 PM
To: [email-masked]'
Subject: [IBIS-Users] Temperature Range:

Hello..............

I have a question regarding the proper format to use for the IBIS model
keyword:[Temperature Range]. According to version 3.2 of the EIA IBIS
Standard, the format is: typ, min, and max. The example given on page 29 of
the referenced standard is: typ: 27.0, min: -50, max: 130.0. Yet, I have
seen IBIS models from various sources that specify the min temperature as
high, in this case 130; and the max temperature as low, in this case -50.
Can someone comment on what the proper entry should be? I tend to believe
the standard, but I have seen so many IBIS files with the min and max
entries reversed that I just had to ask.

Thank You,
Louis A. Sanchez
|------------------------------------------------------------------
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|with just the appropriate command message(s) in the body:
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|
|or email a written request to [email-masked].
|
|IBIS reflector archives exist under:
|
|  http://www.eda.org/pub/ibis/email_archive/  Recent
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|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Wed, 27 Mar 2002 16:27:54 -0800
From: "Bill Hargin" <[email-masked]>
Subject: RE: [IBIS-Users] Temperature Range:

Hi Louis:

The spec and your initial example are correct.  Mistakes in IBIS models are
a dime a dozen, unfortunately.  As a recent thread discussed, many models do
not appear to be validated in simulators before they're released, and a lot
of models have obvious syntactical errors.

Best Regards,
Bill Hargin
Direct: 425-702-0744
Fax:    425-702-0305

Cognition Consulting
Electronic Design Software and Consulting
http://www.CognitionConsulting.com

> -----Original Message-----
> From: [email-masked] [mailto:[email-masked]]On
> Behalf Of Sanchez, Louis
> Sent: Wednesday, March 27, 2002 3:41 PM
> To: [email-masked]'
> Subject: [IBIS-Users] Temperature Range:
>
>
> Hello..............
>
> I have a question regarding the proper format to use for the IBIS model
> keyword:[Temperature Range]. According to version 3.2 of the EIA IBIS
> Standard, the format is: typ, min, and max. The example given on
> page 29 of
> the referenced standard is: typ: 27.0, min: -50, max: 130.0. Yet, I have
> seen IBIS models from various sources that specify the min temperature as
> high, in this case 130; and the max temperature as low, in this case -50.
> Can someone comment on what the proper entry should be? I tend to believe
> the standard, but I have seen so many IBIS files with the min and max
> entries reversed that I just had to ask.
>
> Thank You,
> Louis A. Sanchez
> |------------------------------------------------------------------
> |For help or to subscribe/unsubscribe, email [email-masked]
> |with just the appropriate command message(s) in the body:
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------------------------------

Date: Wed, 27 Mar 2002 16:43:07 -0800
From: "Peters, Stephen" <[email-masked]>
Subject: RE: [IBIS-Users] Temperature Range:

Hi Bill, Louis:

  Actually, IBIS models with a 'min' temperature higher than the 'max'
temperature are perfectly correct, assuming the part being modeled is CMOS.
As explained on pg. 57 of the IBIS spec, the 'min' value of [Temperature
Range] is the value that causes or amplifies the slow/weak condition, while
the 'max' value is the value that causes or amplifies the fastest/strongest
condition.   With CMOS, cold is fast & hot is slow.  TTL logic is just the
opposite. 

  Hope this helps.

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: Bill Hargin [mailto:[email-masked]]
Sent: Wednesday, March 27, 2002 4:28 PM
To: Sanchez, Louis; [email-masked]'
Subject: RE: [IBIS-Users] Temperature Range:

Hi Louis:

The spec and your initial example are correct.  Mistakes in IBIS models are
a dime a dozen, unfortunately.  As a recent thread discussed, many models do
not appear to be validated in simulators before they're released, and a lot
of models have obvious syntactical errors.

Best Regards,
Bill Hargin
Direct: 425-702-0744
Fax:    425-702-0305

Cognition Consulting
Electronic Design Software and Consulting
http://www.CognitionConsulting.com

> -----Original Message-----
> From: [email-masked] [mailto:[email-masked]]On
> Behalf Of Sanchez, Louis
> Sent: Wednesday, March 27, 2002 3:41 PM
> To: [email-masked]'
> Subject: [IBIS-Users] Temperature Range:
>
>
> Hello..............
>
> I have a question regarding the proper format to use for the IBIS model
> keyword:[Temperature Range]. According to version 3.2 of the EIA IBIS
> Standard, the format is: typ, min, and max. The example given on
> page 29 of
> the referenced standard is: typ: 27.0, min: -50, max: 130.0. Yet, I have
> seen IBIS models from various sources that specify the min temperature as
> high, in this case 130; and the max temperature as low, in this case -50.
> Can someone comment on what the proper entry should be? I tend to believe
> the standard, but I have seen so many IBIS files with the min and max
> entries reversed that I just had to ask.
>
> Thank You,
> Louis A. Sanchez
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------------------------------

Date: Wed, 27 Mar 2002 18:22:35 -0700
From: Al Davis <[email-masked]>
Subject: Re: [IBIS-Users] Temperature Range:

On Wednesday 27 March 2002 17:43, Peters, Stephen wrote:
>   Actually, IBIS models with a 'min' temperature higher than the
> 'max' temperature are perfectly correct, assuming the part being
> modeled is CMOS. As explained on pg. 57 of the IBIS spec, the 'min'
> value of [Temperature Range] is the value that causes or amplifies
> the slow/weak condition, while the 'max' value is the value that
> causes or amplifies the fastest/strongest condition.   With CMOS,
> cold is fast & hot is slow.  TTL logic is just the opposite.

That doesn't make sense.  The only place it is actually used in 
calculations in transit time, when [TTpower] or [TTgnd] keywords are 
used.  These define the nonlinear capacitance in parallel with the 
clamps.  High temperature is always low capacitance, therefore "fast".
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------------------------------

Date: Wed, 27 Mar 2002 23:50:24 -0500
From: "Todd Westerhoff" <[email-masked]>
Subject: RE: [IBIS-Users] Temperature Range:

Mistakes in IBIS models are now a dime a dozen?  When did the price go up?

Todd ;-)

Todd Westerhoff
Signal Integrity Engineer
Hammerhead Networks
5 Federal Street - Billerica, MA - 01821
email:[email-masked] - ph: 978-671-5084
============================================

"I’m starting With the man in the mirror
 I’m asking him to change his ways
 And no message could have been any clearer
 If you wanna make the world a better place
 Take a look at yourself, and then make a change"

- - "Man in the Mirror", Michael Jackson

- -----Original Message-----
From: [email-masked]
[mailto:[email-masked]]On Behalf Of Bill Hargin
Sent: Wednesday, March 27, 2002 7:28 PM
To: Sanchez, Louis; [email-masked]'
Subject: RE: [IBIS-Users] Temperature Range:

Hi Louis:

The spec and your initial example are correct.  Mistakes in IBIS models are
a dime a dozen, unfortunately.  As a recent thread discussed, many models do
not appear to be validated in simulators before they're released, and a lot
of models have obvious syntactical errors.

Best Regards,
Bill Hargin
Direct: 425-702-0744
Fax:    425-702-0305

Cognition Consulting
Electronic Design Software and Consulting
http://www.CognitionConsulting.com

> -----Original Message-----
> From: [email-masked] [mailto:[email-masked]]On
> Behalf Of Sanchez, Louis
> Sent: Wednesday, March 27, 2002 3:41 PM
> To: [email-masked]'
> Subject: [IBIS-Users] Temperature Range:
>
>
> Hello..............
>
> I have a question regarding the proper format to use for the IBIS model
> keyword:[Temperature Range]. According to version 3.2 of the EIA IBIS
> Standard, the format is: typ, min, and max. The example given on
> page 29 of
> the referenced standard is: typ: 27.0, min: -50, max: 130.0. Yet, I have
> seen IBIS models from various sources that specify the min temperature as
> high, in this case 130; and the max temperature as low, in this case -50.
> Can someone comment on what the proper entry should be? I tend to believe
> the standard, but I have seen so many IBIS files with the min and max
> entries reversed that I just had to ask.
>
> Thank You,
> Louis A. Sanchez
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------------------------------

Date: Thu, 28 Mar 2002 06:32:20 -0800
From: "Mellitz, Richard" <[email-masked]>
Subject: RE: [IBIS-Users] Temperature Range:

Al, 

Regarding the statement: "High temperature is always low capacitance,
therefore "fast"." 
Is only true of buffers whose slew rate is controlled by capacitance. There
are adaptive slew rate and driver strength schemes that can change the
dependence of slew rate and buffer strength on temperature. Just some food
for thought. :-)

Rich Mellitz,
Intel

- -----Original Message-----
From: Al Davis [mailto:[email-masked]]
Sent: Wednesday, March 27, 2002 8:23 PM
To: [email-masked]
Subject: Re: [IBIS-Users] Temperature Range:

On Wednesday 27 March 2002 17:43, Peters, Stephen wrote:
>   Actually, IBIS models with a 'min' temperature higher than the
> 'max' temperature are perfectly correct, assuming the part being
> modeled is CMOS. As explained on pg. 57 of the IBIS spec, the 'min'
> value of [Temperature Range] is the value that causes or amplifies
> the slow/weak condition, while the 'max' value is the value that
> causes or amplifies the fastest/strongest condition.   With CMOS,
> cold is fast & hot is slow.  TTL logic is just the opposite.

That doesn't make sense.  The only place it is actually used in 
calculations in transit time, when [TTpower] or [TTgnd] keywords are 
used.  These define the nonlinear capacitance in parallel with the 
clamps.  High temperature is always low capacitance, therefore "fast".
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------------------------------

Date: Thu, 28 Mar 2002 13:04:50 -0500
From: "Ingraham, Andrew" <[email-masked]>
Subject: RE: [IBIS-Users] Temperature Range:

> That doesn't make sense.  The only place it is actually used in 
> calculations in transit time, when [TTpower] or [TTgnd] keywords are 
> used.  These define the nonlinear capacitance in parallel with the 
> clamps.  High temperature is always low capacitance, therefore "fast".

But high temperature also means higher channel resistance, therefore "slow".

Whether or not an IBIS model actually makes use of the [Temperature Range] numbers themselves, is another matter, however.  (Aside from the [TTpower] or [TTgnd] cases you mentioned.)  There is plenty of data in an IBIS data sheet ("model") that may not be used by the simulator.  Most implementation details are left as an exercise for the simulator vendor.

It is conceivable, if not entirely practical, that a smart simulator might select the appropriate device strength/speed (or interpolate between them), based on the desired simulation temperature.  Or a simulator might give the user a message that the pairing he has selected (CMOS max strength devices simulated at max temperature) is impractical, so results would be overly conservative compared to the models.

Andy

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------------------------------

Date: Thu, 28 Mar 2002 13:19:28 -0500
From: "Ingraham, Andrew" <[email-masked]>
Subject: RE: [IBIS-Users] IBIS and HSPICE simulation result question

Are you comparing waveforms observed at the same electrical point, i.e., package pin vs. die pad?

If both were observed at the package pin, are you sure the IBIS model's package parameters are correct?  If there's a wide range of values, can you tell that the simulator selects the value within that range that you did in your HSPICE simulation?

What simulator did you use when checking the IBIS model?  If Star-HSPICE, did you add a package model (since HSPICE's IBIS implementation doesn't include one)?

If Star-HSPICE, did you include the "optional" nd_pc and nd_gc nodes?  If you don't, HSPICE turns off the clamps whenever the driver is not enabled!  If you over-drive the receiver by a few volts, with a moderate source resistance, does it clamp at all?

Andy

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------------------------------

Date: Thu, 28 Mar 2002 13:42:44 -0500
From: Mike LaBonte <[email-masked]>
Subject: RE: [IBIS-Users] Temperature Range:

At 01:04 PM 3/28/2002 -0500, Ingraham, Andrew wrote:
>It is conceivable, if not entirely practical, that a smart simulator might 
>select the appropriate device strength/speed (or interpolate between 
>them), based on the desired simulation temperature.

SPECCTRAQuest did at one time interpolate between I/V curves based on the 
design operating junction temperature of each part, as determined by 
thermal analysis. However, that was discontinued after doubts were raised 
about temperature being the primary factor. You would want to determine how 
much of the fast/slow variation is due to temperature before undertaking this.

Mike LaBonte

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------------------------------

Date: Tue, 2 Apr 2002 13:09:05 -0500
From: "Timothy Coyle" <[email-masked]>
Subject: [IBIS-Users] Using Differential IBIS Buffers in HSPICE

This is a multipart message in MIME format.
- --=_alternative 006419C685256B8F_=
Content-Type: text/plain; 
 charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi,
I am trying to use differential output IBIS buffers in HSPICE.  I set up 
independent voltage sources on each of the inverting and non-inverting 
output buffer. 
I put 100 ohms across the outputs since it is LVDS.  I'm getting some 
strange results.  Both buffers have non-inverting polarity and the voltage 
swing is way off
for LVDS.  Any help would be appreciated. 

Thanks in advance,
Tim

- --=_alternative 006419C685256B8F_=
Content-Type: text/html; 
 charset=us-ascii
Content-Transfer-Encoding: 7bit

<br><font size=2 face="sans-serif">Hi,</font>
<br><font size=2 face="sans-serif">I am trying to use differential output IBIS buffers in HSPICE. &nbsp;I set up independent voltage sources on each of the inverting and non-inverting output buffer. </font>
<br><font size=2 face="sans-serif">I put 100 ohms across the outputs since it is LVDS. &nbsp;I'm getting some strange results. &nbsp;Both buffers have non-inverting polarity and the voltage swing is way off</font>
<br><font size=2 face="sans-serif">for LVDS. &nbsp;Any help would be appreciated. </font>
<br>
<br><font size=2 face="sans-serif">Thanks in advance,</font>
<br><font size=2 face="sans-serif">Tim</font>
<br>
- --=_alternative 006419C685256B8F_=--

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------------------------------

Date: Tue, 2 Apr 2002 10:59:14 -0800
From: Kim Helliwell <[email-masked]>
Subject: [IBIS-Users] IBIS Imponderables

I'm sure I'm not the only person who has wondered
about these:

1. Why is a mismatch in the file name an error, rather than
     a warning? In fact, why does it matter at all?

2. Why are only lowercase letters allowed in an IBIS file name?

3. Why are AC mismatches warnings rather than errors?

4. Why does s2ibis2 appear to generate IBIS models
     with AC mismatches in the first place? (Judging
     from the number of IBIS models I've seen that
     used s2ibis2 and had such problems, it is
     apparently the norm.)

Feel free to provide answers or add your own imponderables.

Kim Helliwell
Apple Computer
[email-masked]
408 974 9936

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------------------------------

Date: Tue, 2 Apr 2002 15:48:23 -0500 
From: Matthew Flora <[email-masked]>
Subject: RE: [IBIS-Users] IBIS Imponderables

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C1DA87.BABAF7E0
Content-Type: text/plain;
	charset="iso-8859-1"

Dear Kim,

I'll stick my neck out ...

> 1. Why is a mismatch in the file name an error, rather than
>      a warning? In fact, why does it matter at all?

At this point, just backwards compatibility with IBIS 1.0?

> 2. Why are only lowercase letters allowed in an IBIS file name?

To make life easier for files accessed across multiple platforms.  Some
platforms are sensitive to the case of filenames, some are not.  Name
collisions can occur when filenames on a case sensitive platform differ only
in case and those files are then transferred to or accessed from a case-
insensitive platform.  Requiring all of one case gets around the problem.

> 3. Why are AC mismatches warnings rather than errors?

I have been told by a couple model builders who build models from
measurement
of actual parts that they have two different rigs for doing DC and AC
measurements.  This is an example where the two measurements may not be in
exact agreement.  The latest parser does generate an error when the
discrepancies become large.

> 4. Why does s2ibis2 appear to generate IBIS models
>      with AC mismatches in the first place? (Judging
>      from the number of IBIS models I've seen that
>      used s2ibis2 and had such problems, it is
>      apparently the norm.)

Sorry, I don't know.

Best regards,
Matthew Flora

- ------_=_NextPart_001_01C1DA87.BABAF7E0
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	charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2653.12">
<TITLE>RE: [IBIS-Users] IBIS Imponderables</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>Dear Kim,</FONT>
</P>

<P><FONT SIZE=3D2>I'll stick my neck out ...</FONT>
</P>

<P><FONT SIZE=3D2>&gt; 1. Why is a mismatch in the file name an error, =
rather than</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; a warning? In =
fact, why does it matter at all?</FONT>
</P>

<P><FONT SIZE=3D2>At this point, just backwards compatibility with IBIS =
1.0?</FONT>
</P>

<P><FONT SIZE=3D2>&gt; 2. Why are only lowercase letters allowed in an =
IBIS file name?</FONT>
</P>

<P><FONT SIZE=3D2>To make life easier for files accessed across =
multiple platforms.&nbsp; Some</FONT>
<BR><FONT SIZE=3D2>platforms are sensitive to the case of filenames, =
some are not.&nbsp; Name</FONT>
<BR><FONT SIZE=3D2>collisions can occur when filenames on a case =
sensitive platform differ only</FONT>
<BR><FONT SIZE=3D2>in case and those files are then transferred to or =
accessed from a case-</FONT>
<BR><FONT SIZE=3D2>insensitive platform.&nbsp; Requiring all of one =
case gets around the problem.</FONT>
</P>

<P><FONT SIZE=3D2>&gt; 3. Why are AC mismatches warnings rather than =
errors?</FONT>
</P>

<P><FONT SIZE=3D2>I have been told by a couple model builders who build =
models from measurement</FONT>
<BR><FONT SIZE=3D2>of actual parts that they have two different rigs =
for doing DC and AC</FONT>
<BR><FONT SIZE=3D2>measurements.&nbsp; This is an example where the two =
measurements may not be in exact agreement.&nbsp; The latest parser =
does generate an error when the discrepancies become large.</FONT></P>

<P><FONT SIZE=3D2>&gt; 4. Why does s2ibis2 appear to generate IBIS =
models</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; with AC =
mismatches in the first place? (Judging</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from the number =
of IBIS models I've seen that</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; used s2ibis2 and =
had such problems, it is</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; apparently the =
norm.)</FONT>
</P>

<P><FONT SIZE=3D2>Sorry, I don't know.</FONT>
</P>

<P><FONT SIZE=3D2>Best regards,</FONT>
<BR><FONT SIZE=3D2>Matthew Flora</FONT>
</P>

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------------------------------

Date: Tue, 2 Apr 2002 15:57:19 -0500
From: "Lynne Green" <[email-masked]>
Subject: RE: [IBIS-Users] IBIS Imponderables

Hi, Kim,

1) Ancient history that lingers with us.  I personally wouldn't mind
seeing this one reduced to a warning (or even eliminated) in IBIS 4.

2) This one is because some Windows Apps (such as copying a file
to a CD!) thoughtfully change case on files.  This rule makes life easier
when files have to go to both UNIX and Windows.

3) Since there is no agreement on where to draw the line between 
warnings and errors for mismatches, it is never an error.  At least
the size of the mismatch is reported by the parser.  (Sigh.)

4) Not sure about s2ibis2, but have seen this where there are not enough
table points in the transition region of a table.  Model makers need to
keep more points in tables where data is changing (steep slope), and 
fewer where is changing slowly or not at all, for both I-V and V-t tables.

Best regards,
Lynne

Dr. Lynne Green
Cadence Design Systems, Inc.
[email-masked]

- -----Original Message-----
From: Kim Helliwell [mailto:[email-masked]]
Sent: Tuesday, April 02, 2002 10:59 AM
To: [email-masked]'
Subject: [IBIS-Users] IBIS Imponderables

I'm sure I'm not the only person who has wondered
about these:

1. Why is a mismatch in the file name an error, rather than
     a warning? In fact, why does it matter at all?

2. Why are only lowercase letters allowed in an IBIS file name?

3. Why are AC mismatches warnings rather than errors?

4. Why does s2ibis2 appear to generate IBIS models
     with AC mismatches in the first place? (Judging
     from the number of IBIS models I've seen that
     used s2ibis2 and had such problems, it is
     apparently the norm.)

Feel free to provide answers or add your own imponderables.

Kim Helliwell
Apple Computer
[email-masked]
408 974 9936

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------------------------------

Date: Tue, 02 Apr 2002 16:36:58 -0500
From: Mike LaBonte <[email-masked]>
Subject: Re: [IBIS-Users] IBIS Imponderables

One would expect filename mismatches to be a rare problem.
It has been explained to me though, in some IC companies,
when an IBIS file is submitted by the model maker for publishing,
the first thing the web people do is change the filename.

Mike LaBonte

At 10:59 AM 4/2/2002 -0800, Kim Helliwell wrote:
>I'm sure I'm not the only person who has wondered
>about these:
>
>1. Why is a mismatch in the file name an error, rather than
>     a warning? In fact, why does it matter at all?
>
>2. Why are only lowercase letters allowed in an IBIS file name?
>
>3. Why are AC mismatches warnings rather than errors?
>
>4. Why does s2ibis2 appear to generate IBIS models
>     with AC mismatches in the first place? (Judging
>     from the number of IBIS models I've seen that
>     used s2ibis2 and had such problems, it is
>     apparently the norm.)
>
>Feel free to provide answers or add your own imponderables.
>
>
>Kim Helliwell
>Apple Computer
>[email-masked]
>408 974 9936
>
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------------------------------

Date: Tue, 2 Apr 2002 17:34:45 -0700
From: Al Davis <[email-masked]>
Subject: Re: [IBIS-Users] IBIS Imponderables

Here's one I have been wondering about ...

Why do people involved with IBIS refer to transient behavior as "AC"? 
 AC has always meant steady state frequency domain to me.
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------------------------------

Date: Tue, 2 Apr 2002 16:58:36 -0800
From: Kim Helliwell <[email-masked]>
Subject: Re: [IBIS-Users] IBIS Imponderables

That's a good one. I only used the term that way because
that's what the IBIS Golden Parser calls it. I assume that
everyone is familiar with the error message for "AC mismatch"
so it's a bit of shorthand.

You are right about it being a misnomer.

Kim

On Tuesday, April 2, 2002, at 04:34  PM, Al Davis wrote:

> Here's one I have been wondering about ...
>
> Why do people involved with IBIS refer to transient behavior as "AC"?
>  AC has always meant steady state frequency domain to me.
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Apple Computer
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------------------------------

Date: Tue, 2 Apr 2002 20:09:36 -0500 
From: Chris Rokusek <[email-masked]>
Subject: RE: [IBIS-Users] IBIS Imponderables

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Al,

My guess is that it is a carry over from databooks which often use the
term "AC characteristics" to describe switching behavior.

Chris

- -----Original Message-----
From: Al Davis [mailto:[email-masked]] 
Sent: Tuesday, April 02, 2002 4:35 PM
To: [email-masked]
Subject: Re: [IBIS-Users] IBIS Imponderables

Here's one I have been wondering about ...

Why do people involved with IBIS refer to transient behavior as "AC"? 
 AC has always meant steady state frequency domain to me.
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<P><FONT SIZE=3D2>Al,</FONT>
</P>

<P><FONT SIZE=3D2>My guess is that it is a carry over from databooks =
which often use the</FONT>
<BR><FONT SIZE=3D2>term &quot;AC characteristics&quot; to describe =
switching behavior.</FONT>
</P>

<P><FONT SIZE=3D2>Chris</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Al Davis [<A =
HREF=3D"mailto:[email-masked]">mailto:[email-masked]</A>] </FONT>
<BR><FONT SIZE=3D2>Sent: Tuesday, April 02, 2002 4:35 PM</FONT>
<BR><FONT SIZE=3D2>To: [email-masked]</FONT>
<BR><FONT SIZE=3D2>Subject: Re: [IBIS-Users] IBIS Imponderables</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Here's one I have been wondering about ...</FONT>
</P>

<P><FONT SIZE=3D2>Why do people involved with IBIS refer to transient =
behavior as &quot;AC&quot;? </FONT>
<BR><FONT SIZE=3D2>&nbsp;AC has always meant steady state frequency =
domain to me.</FONT>
<BR><FONT =
SIZE=3D2>|--------------------------------------------------------------=
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------------------------------

Date: Wed, 3 Apr 2002 00:31:40 -0800
From: "Jeremy Plunkett" <[email-masked]>
Subject: RE: [IBIS-Users] IBIS Imponderables

Hi Kim,
I have never been involved in the IBIS specification process, but I have built a lot of models, and here are my best-guess answers to your questions...

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]On
Behalf Of Kim Helliwell
Sent: Tuesday, April 02, 2002 10:59 AM
To: [email-masked]'
Subject: [IBIS-Users] IBIS Imponderables

I'm sure I'm not the only person who has wondered
about these:

1. Why is a mismatch in the file name an error, rather than
     a warning? In fact, why does it matter at all?

This was probably intended to prevent people from modifying the filename from the original (or make it more difficult, at least).  This is because an IBIS file is similar to a specification (more detailed, but less official) and semiconductor vendors do not want modified versions of their IBIS models floating around.  There should be one most current revision of an IBIS model for a given part, and if people are prevented from renaming the file then it is easier to confirm that they are all using the same file.  Of course if model users want to work around this they can (and do), but they have to go through the hassle of changing the name in 2 places.

2. Why are only lowercase letters allowed in an IBIS file name?

As others mentioned, this helps ease transfer between operating systems.

3. Why are AC mismatches warnings rather than errors?

The mismatch that this indicates is between the initial or final voltage of a VT curve and the predicted (steady-state)operating point based on the intersection of the IV curve with the load line for the VT curve load resistance.  There are 2 likely reasons why this mismatch occurs: 

1) the model maker trimmed off too much of the initial portion of the VT curve data before the edge, and either cut off the very beginning of the transition or set the start point of the VT curve data in the middle of a "pre-shoot" hump in the data (bounce on the signal that occurs prior to switching due to capacitive coupling between the gate and source/drain terminals of the output transistors).

2) the model maker set the end of the VT curves at a point where the signal had not yet completely settled at one or more of the PVT corners.  This is often unavoidable if the buffer will be used in a very fast switching environment, since some simulation programs (specifically Hspice, to my knowledge, and possibly others) will give erroneous waveforms if the VT curves are longer than the pulse width when the model is used in simulation.  This requires that a buffer which will be used at a frequency of 200MHz (2.5ns pulse width) must have VT curves less than 2.5ns in duration, maybe 10-15% less if the duty cycle or frequency will be varied in simulations.

Neither of these situations has a large effect on the accuracy of the simulation results with any simulators I've used, since in the 1st case any errors in the waveform occur prior to the portion of the edge which crosses the receiver thresholds and in the 2nd case the waveform errors would occur while the output voltage is at a steady-state high or low.  The sort of error that does occur depends on exactly what the simulator does in the face of the inconsistent VT data, but I am fairly sure that most if not all simulators either modify the curves with interpolated values or revert to some approximation of the IBIS 1.0 (no VT curves) algorithm at the discontinuities and just apply the VI curves to the load, which will result in a fairly smooth transition either way.

4. Why does s2ibis2 appear to generate IBIS models
     with AC mismatches in the first place? (Judging
     from the number of IBIS models I've seen that
     used s2ibis2 and had such problems, it is
     apparently the norm.)

The 2 situations above are very common, the 1st case happens more often with slow-speed logic and inexperienced model makers who determine the beginning of the transition in an arbitrary manner, the 2nd case is more common with very high speed logic and is often unavoidable.

Since avoiding the mismatch warning involves modifying the VT curves from the original data based on spice or measurement, whether to do so in a given case is a judgment call, and is probably not worth doing unless there is a significant chance that leaving the model with the mismatch will result in simulator errors.

Feel free to provide answers or add your own imponderables.

Kim Helliwell
Apple Computer
[email-masked]
408 974 9936

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------------------------------

Date: Wed, 3 Apr 2002 08:33:03 -0500
From: "Ingraham, Andrew" <[email-masked]>
Subject: RE: [IBIS-Users] IBIS Imponderables

Another possible reason for the error-vs-warning differentiation, on top of those already mentioned....

When a mistake is easily avoidable and/or correctable, and not the result of variations from one (simulator) implementation to another, they would be errors.

A file name error is easily and permanently fixed.

On the other hand, an "AC" mismatch depends to some degree on the interpolation algorithm used by the simulator.  Also, miniscule voltage errors can sometimes cause enormous percentage differences, but shouldn't prevent the model from being used (without an expert handy to tweak the tables).

Regards,
Andy

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------------------------------

Date: Thu, 4 Apr 2002 10:43:03 -0800 
From: "Mirmak, Michael" <[email-masked]>
Subject: RE: [IBIS-Users] Using Differential IBIS Buffers in HSPICE

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Tim,
 
There are known differences in how recent versions of HSPICE (2001.2 vs.
2001.4) treat differential IBIS models.  Try consulting the Avant! website
or your local rep. for the latest usage recommendations on 2001.4.  We've
had success by adding the following line to our B-element calls:
 
+hsp_ver=2001.2
 
This will force HSPICE to use the 2001.2 IBIS simulation engine.  Try it and
see if your results meet expectations.
 
Good luck!
 
- - Michael Mirmak, Intel Corp.
 
 -----Original Message-----
From: Timothy Coyle [mailto:[email-masked]]
Sent: Tuesday, April 02, 2002 10:09 AM
To: [email-masked]
Subject: [IBIS-Users] Using Differential IBIS Buffers in HSPICE

Hi, 
I am trying to use differential output IBIS buffers in HSPICE.  I set up
independent voltage sources on each of the inverting and non-inverting
output buffer. 
I put 100 ohms across the outputs since it is LVDS.  I'm getting some
strange results.  Both buffers have non-inverting polarity and the voltage
swing is way off 
for LVDS.  Any help would be appreciated. 

Thanks in advance, 
Tim 

- ------_=_NextPart_001_01C1DC08.8D995590
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	charset="iso-8859-1"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">

<META content="MSHTML 5.00.3502.4856" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT face="Courier New" size=2><SPAN 
class=640384316-03042002>Tim,</SPAN></FONT></DIV>
<DIV><SPAN class=640384316-03042002></SPAN>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=640384316-03042002>There are 
known differences in how recent versions of HSPICE (2001.2 vs. 2001.4) treat 
differential IBIS models.&nbsp; Try consulting the Avant! website or your local 
rep. for the latest&nbsp;usage recommendations on 2001.4.&nbsp; We've had 
success by adding the following line to our B-element calls:</SPAN></FONT></DIV>
<DIV><SPAN class=640384316-03042002></SPAN>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=640384316-03042002>+hsp_ver=2001.2</SPAN></FONT></DIV>
<DIV><SPAN class=640384316-03042002></SPAN>&nbsp;</DIV>
<DIV><FONT face="Courier New"><FONT size=2><SPAN class=640384316-03042002>This 
will force HSPICE to use the 2001.2 IBIS simulation engine</SPAN><SPAN 
class=640384316-03042002>.&nbsp; Try it and see if your results meet 
expectations.</SPAN></FONT></FONT></DIV>
<DIV><SPAN class=640384316-03042002></SPAN>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=640384316-03042002>Good 
luck!</SPAN></FONT></DIV>
<DIV><SPAN class=640384316-03042002></SPAN>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=640384316-03042002>- Michael 
Mirmak, Intel Corp.</SPAN></FONT></DIV>
<DIV><FONT face=Tahoma><FONT size=2><SPAN 
class=640384316-03042002></SPAN></FONT></FONT>&nbsp;</DIV>
<DIV><FONT face=Tahoma><FONT size=2><SPAN 
class=640384316-03042002>&nbsp;</SPAN>-----Original Message-----<BR><B>From:</B> 
Timothy Coyle [mailto:[email-masked]]<BR><B>Sent:</B> Tuesday, April 02, 
2002 10:09 AM<BR><B>To:</B> [email-masked]<BR><B>Subject:</B> 
[IBIS-Users] Using Differential IBIS Buffers in HSPICE<BR><BR></DIV></FONT>
<BLOCKQUOTE></FONT><BR><FONT face=sans-serif size=2>Hi,</FONT> <BR><FONT 
  face=sans-serif size=2>I am trying to use differential output IBIS buffers in 
  HSPICE. &nbsp;I set up independent voltage sources on each of the inverting 
  and non-inverting output buffer. </FONT><BR><FONT face=sans-serif size=2>I put 
  100 ohms across the outputs since it is LVDS. &nbsp;I'm getting some strange 
  results. &nbsp;Both buffers have non-inverting polarity and the voltage swing 
  is way off</FONT> <BR><FONT face=sans-serif size=2>for LVDS. &nbsp;Any help 
  would be appreciated. </FONT><BR><BR><FONT face=sans-serif size=2>Thanks in 
  advance,</FONT> <BR><FONT face=sans-serif size=2>Tim</FONT> 
<BR></BLOCKQUOTE></BODY></HTML>

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------------------------------

Date: Fri, 5 Apr 2002 16:32:15 -0500
From: "Timothy Coyle" <[email-masked]>
Subject: [IBIS-Users] Measuring Ccomp in HSPICE

This is a multipart message in MIME format.
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 charset=us-ascii
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Hello,
I'm looking for a way to obtain ccomp for inputs/outputs in HSPICE for 
IBIS.  I would like to be able to get ccomp min and max values from
simulation.

Thanks,
Tim

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 charset=us-ascii
Content-Transfer-Encoding: 7bit

<br><font size=2 face="sans-serif">Hello,</font>
<br><font size=2 face="sans-serif">I'm looking for a way to obtain ccomp for inputs/outputs in HSPICE for IBIS. &nbsp;I would like to be able to get ccomp min and max values from</font>
<br><font size=2 face="sans-serif">simulation.</font>
<br>
<br><font size=2 face="sans-serif">Thanks,</font>
<br><font size=2 face="sans-serif">Tim</font>
<br>
- --=_alternative 00768B0D85256B92_=--

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------------------------------

Date: Tue, 9 Apr 2002 14:39:47 -0400
From: "Michael Dotson" <[email-masked]>
Subject: [IBIS-Users] test..please ignore

Just a test msg

Regards,
Mike Dotson
Endicott Worldwide Field Design Center   607-752-5379 (tl 852)

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------------------------------

Date: Tue, 9 Apr 2002 15:36:48 -0400
From: "Michael Dotson" <[email-masked]>
Subject: [IBIS-Users] Using the '.ibis' (note the dot) in HSPICE

I have spent the last 2 days puzzling over how to use the ' .ibis ' call in
hspice.
Using the basic ibis buffer works ok, but this  other command was there to
try as well.

The ibis device I have is a basic  TS TTL buffering device that says it is
2.1 compatible.

When  hspice  runs I can see that it allocates a buffer to each input and
output pin.
However, the stim I put on the input pin does not get propagated to the
output pin.
I can see the input buffer switching a-ok, but the output buffer does not.
I have even tried different enable pin values to see if that had an effect.

What seem to be missing is the 'hook'  to drive the output buffers nd_in
port.
Actually, I do not even see a port named nd_in for the output buffers.  I
can
see the pc and pd and en pins OK though.

Can someone shed some light on my confusion?

thanks,
Mike Dotson
IBM Endicott Worldwide Field Design Center   607-752-5379 (tl 852)

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------------------------------

Date: Tue, 09 Apr 2002 17:12:48 -0400
From: Mark Bossard <[email-masked]>
Subject: Re: [IBIS-Users] Using the '.ibis' (note the dot) in HSPICE

I would suggest checking out the Hspice Device Models Manual.
It should be part of the normal Hspice electronic documentation package.
It has a fair description and examples of using .ibis .

The Device Models Manual tells you what the node names are (or should
be).

The names of the input and output nodes for the buffers are: 
INPUT and INPUT_ECL buffers signal name of pin ( in )  
bufn_<pin_number>  ( outofin ) 
Other types of buffers  bufn_<pin_number> ( in ) signal name of pin (
out )
n <pin_number> is 1 if this pin is the first pin defined in the [Pin]
keyword. 
n <pin_number> is 2 if this pin is the second pin. and so on. 
Note: If the buffer has an enable terminal, you must create a node named
buffer_name_en to enable the buffer.

Good Luck,

Mark Bossard

Michael Dotson wrote:
> 
> I have spent the last 2 days puzzling over how to use the ' .ibis ' call in
> hspice.
> Using the basic ibis buffer works ok, but this  other command was there to
> try as well.
> 
> The ibis device I have is a basic  TS TTL buffering device that says it is
> 2.1 compatible.
> 
> When  hspice  runs I can see that it allocates a buffer to each input and
> output pin.
> However, the stim I put on the input pin does not get propagated to the
> output pin.
> I can see the input buffer switching a-ok, but the output buffer does not.
> I have even tried different enable pin values to see if that had an effect.
> 
> What seem to be missing is the 'hook'  to drive the output buffers nd_in
> port.
> Actually, I do not even see a port named nd_in for the output buffers.  I
> can
> see the pc and pd and en pins OK though.
> 
> Can someone shed some light on my confusion?
> 
> thanks,
> Mike Dotson
> IBM Endicott Worldwide Field Design Center   607-752-5379 (tl 852)
> 
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- -- 

========================================================================
| Mark Bossard                     | Atmel Corporation                 |
| Direct Phone: (410) 423-4352     | Chesapeake Design Center          |
| Main Phone:   (410) 423-4300     | 8820 Columbia 100 Parkway         |
| Fax:          (410) 423-4302     | Suite 300                         |
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========================================================================
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------------------------------

Date: Tue, 09 Apr 2002 18:18:56 -0400
From: Mike LaBonte <[email-masked]>
Subject: Re: [IBIS-Users] Using the '.ibis' (note the dot) in HSPICE

The actual node names don't matter, do they? You can name
them anything you want as long as the terminal positions are
correct in the B element call. It wouldn't be SPICE if the actual
names mattered.

I was wondering if Mike is using the power=off parameter, which
causes the power and ground terminal to be used to supply current
to the buffer. This has never worked for me, and I have yet to find
an example of a circuit that works that way.

Mike

At 05:12 PM 4/9/2002 -0400, Mark Bossard wrote:
>I would suggest checking out the Hspice Device Models Manual.
>It should be part of the normal Hspice electronic documentation package.
>It has a fair description and examples of using .ibis .
>
>The Device Models Manual tells you what the node names are (or should
>be).
>
>The names of the input and output nodes for the buffers are:
>INPUT and INPUT_ECL buffers signal name of pin ( in )
>bufn_<pin_number>  ( outofin )
>Other types of buffers  bufn_<pin_number> ( in ) signal name of pin (
>out )
>n <pin_number> is 1 if this pin is the first pin defined in the [Pin]
>keyword.
>n <pin_number> is 2 if this pin is the second pin. and so on.
>Note: If the buffer has an enable terminal, you must create a node named
>buffer_name_en to enable the buffer.
>
>Good Luck,
>
>Mark Bossard
>
>
>
>Michael Dotson wrote:
> >
> > I have spent the last 2 days puzzling over how to use the ' .ibis ' call in
> > hspice.
> > Using the basic ibis buffer works ok, but this  other command was there to
> > try as well.
> >
> > The ibis device I have is a basic  TS TTL buffering device that says it is
> > 2.1 compatible.
> >
> > When  hspice  runs I can see that it allocates a buffer to each input and
> > output pin.
> > However, the stim I put on the input pin does not get propagated to the
> > output pin.
> > I can see the input buffer switching a-ok, but the output buffer does not.
> > I have even tried different enable pin values to see if that had an effect.
> >
> > What seem to be missing is the 'hook'  to drive the output buffers nd_in
> > port.
> > Actually, I do not even see a port named nd_in for the output buffers.  I
> > can
> > see the pc and pd and en pins OK though.
> >
> > Can someone shed some light on my confusion?
> >
> > thanks,
> > Mike Dotson
> > IBM Endicott Worldwide Field Design Center   607-752-5379 (tl 852)
> >

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------------------------------

Date: Wed, 10 Apr 2002 10:03:14 -0400
From: "Ingraham, Andrew" <[email-masked]>
Subject: RE: [IBIS-Users] Using the '.ibis' (note the dot) in HSPICE

I was going to comment on this too, but I'm confused exactly what he's doing.

There's no inherent connection between an input buffer and an output buffer.  IBIS doesn't model whole devices, such as a complete gate.  It models just the input alone, as seen from outside the chip; or just the output alone; but there is no connection from an input (of one model) to an output (of the same or a different model).  Signals do not propagate through IBIS models.

That being said, HSPICE's implementation does use buffer elements through which signals effectively propagate with zero delay; but one of those signals is pure binary.

For example, if you model an input buffer ("buffer=input"), the signal that the simulation applies to the "nd_in" node (which represents the device's input pad) does appear, in binary voltage form, at the "nd_out_of_in" node.  Merely as a convenience to you.  This signal has no physical meaning whatsoever.

For the output buffer ("buffer=output"), *you* need to drive the "nd_in" pin, with a binary voltage source.  Again, the signal has no physical meaning.  It is just a way to get the buffer element to do something.

As for the node names, the names given in the HSPICE manual to represent syntax, such as "nd_in", are just place-holders for the names you use.  "nd_in" itself has no special meaning to HSPICE.  Recall the syntax for resistors, which is:

Rxxx n1 n2 ...

Nodes "n1" and "n2" are place-holders.

Your IBIS model could look like:

BTTL 1 2 3 4 5 6 ...
or:
B_xyz VccPad GndPad SigPad BinSig ...

If you instantiate more than one IBIS device, make sure not to use the same node names on all of them, unless you really wanted them all shorted together!

Andy

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------------------------------

Date: Wed, 10 Apr 2002 11:18:12 -0400
From: "Michael Dotson" <[email-masked]>
Subject: RE: [IBIS-Users] Using the '.ibis' (note the dot) in HSPICE

The confusion was coming from the 'Device Models Ref' manual decription of
the Hspice implementation of the 'automagic'
buffer instantiation when the ' .ibis ' command is used.   From the
comments here, I understand that I need to stim whatever buffer I wanted to
look at.
Now that I realize that the 'bufn_#' is either an input or output node,
depending in the buffer type, I have been able to proceed forward.

Many thanks for the help,
Mike Dotson
IBM Endicott Worldwide Field Design Center   607-752-5379 (tl 852)

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------------------------------

Date: Wed, 10 Apr 2002 12:30:22 -0400
From: Mark Bossard <[email-masked]>
Subject: Re: [IBIS-Users] Using the '.ibis' (note the dot) in HSPICE

To clear up a little confusion....

 '.ibis'  is a new command in Hspice (2001.4.1 is the first appearance I
think) that serves this function...

>>The Avant! True-Hspice models implement buffers as a standard b element. But to support simulation of IBIS >>models using .ebd and .pkg, True-Hspice IBIS models include another component that creates buffers for an >>integrated circuit.

>>The .ibis command adds a buffer to the netlist for every pin, according to the signal_name and model_name >>defined in the [Pin] keyword in the .ibs file.

Oddly enough.... you don't need to use .ebd or .pkg to use .ibis, and I
don't believe you need to use .ibis to use .ebd and .pkg (as they
existed in Hspice before .ibis).

As it is a new command, there is little documentation on it (only about
6 spotty pages).
It's enough of a departure from the normal B model ibis buffer in Hspice
that it gets rather confusing to try to use it.
I looked at it, tried using it a few times, and then gave up and decided
it was a waste of my valuable time (without better documentation and/or
support from Avanti).

- -Mark Bossard

- -

- -- 

========================================================================
| Mark Bossard                     | Atmel Corporation                 |
| Direct Phone: (410) 423-4352     | Chesapeake Design Center          |
| Main Phone:   (410) 423-4300     | 8820 Columbia 100 Parkway         |
| Fax:          (410) 423-4302     | Suite 300                         |
| Email:        [email-masked] | Columbia, MD 21045                |
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------------------------------

Date: Wed, 10 Apr 2002 15:30:29 -0400
From: "Michael Dotson" <[email-masked]>
Subject: Re: [IBIS-Users] Using the '.ibis' (note the dot) in HSPICE

The final word is I discovered that the IV tables were bad (wrong sign) in
the ibis model I was using.
Everything looks OK after I fixed the tables.

Thanks,
Mike Dotson
IBM Endicott Worldwide Field Design Center   607-752-5379 (tl 852)

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------------------------------

Date: Thu, 11 Apr 2002 21:51:24 -0400
From: Guy deBurgh <[email-masked]>
Subject: [IBIS-Users] IBIS Summit meeting at Dac 2002

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this format, some or all of this message may not be legible.

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             D A C   2 0 0 2   I B I S   S U M M I T   M E E T I N G
                       F I R S T   A N N O U N C E M E N T

DATE:      Thursday, June 13, 2002
TIME:      8:30 AM - 5:00 PM

CITY:      New Orleans, Louisiana

LOCATION:  Hilton Hotel, New Orleans Riverside, next to Ernest N. Morial

           Convention Center where the Design Automation Conference
           (DAC) is being held.

ROOM:      To be announced.

LUNCH:     Free Refreshments and Lunch will be provided.

AGENDA:    The agenda is being planned.  Some possible items are:

             Election of Officers for 2002 - 2003

             Connector Specification

             Multi-Lingual Modeling

             EMI Modeling

             IBIS Version 4.0 Review

             IBIS Quality

             Modeling Problems and Solutions

           We welcome presentations and discussions on IBIS topics.

DAC 2002:  DAC is scheduled Monday - Friday, June 10 - 14, 2002.
           The exhibitor portion is open from Monday - Wednesday.
           For more information on DAC 2002 activities, housing, etc.,
           visit the DAC URL:

DAC URL:   http://www.dac.com/

CALL FOR PRESENTATIONS:

           We are also open to technical presentations (usually 30
minutes
           or less) related to any current IBIS activity and to future
IBIS
           needs.

           Contact Guy de Burgh regarding your presentation:

              Presenter:
              Title:
              Estimated Time:

           We are providing an LCD Projector and an Overhead Projector.
           Please plan to bring foils for backup, if needed.

           We would like you to provide handouts for the meeting (about
25)
           and also an electronic copy for archiving.

CALL FOR ATTENDEES:

           Please let Guy de Burgh know if you are planning to attend so

           we have an estimate on food requirements.

CONTACT:   Guy de Burgh
           IBIS Secretary
           [email-masked]
           (805) 988-8250 ext. 6823

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<TITLE>IBIS Summit meeting at Dac 2002</TITLE>
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<BODY>
<BR>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; D A C&nbsp;&nbsp; 2 0 0 2&nbsp;&nbsp; I B I S&nbsp;&nbsp; S U =
M M I T&nbsp;&nbsp; M E E T I N G</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; F =
I R S T&nbsp;&nbsp; A N N O U N C E M E N T</FONT>
</P>

<P><FONT SIZE=3D2>DATE:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Thursday, June =
13, 2002</FONT>
<BR><FONT SIZE=3D2>TIME:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 8:30 AM - 5:00 =
PM</FONT>
</P>

<P><FONT SIZE=3D2>CITY:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; New Orleans, =
Louisiana</FONT>
</P>

<P><FONT SIZE=3D2>LOCATION:&nbsp; Hilton Hotel, New Orleans Riverside, =
next to Ernest N. Morial</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Convention Center where the Design Automation Conference</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
(DAC) is being held.</FONT>
</P>

<P><FONT SIZE=3D2>ROOM:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; To be =
announced.</FONT>
</P>

<P><FONT SIZE=3D2>LUNCH:&nbsp;&nbsp;&nbsp;&nbsp; Free Refreshments and =
Lunch will be provided.</FONT>
</P>

<P><FONT SIZE=3D2>AGENDA:&nbsp;&nbsp;&nbsp; The agenda is being =
planned.&nbsp; Some possible items are:</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Election of Officers for 2002 - 2003</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Connector Specification</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Multi-Lingual Modeling</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; EMI Modeling</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; IBIS Version 4.0 Review</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; IBIS Quality</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Modeling Problems and Solutions</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
We welcome presentations and discussions on IBIS topics.</FONT>
</P>

<P><FONT SIZE=3D2>DAC 2002:&nbsp; DAC is scheduled Monday - Friday, =
June 10 - 14, 2002.</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
The exhibitor portion is open from Monday - Wednesday.</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
For more information on DAC 2002 activities, housing, etc.,</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
visit the DAC URL:</FONT>
</P>

<P><FONT SIZE=3D2>DAC URL:&nbsp;&nbsp; <A HREF=3D"http://www.dac.com/" =
TARGET=3D"_blank">http://www.dac.com/</A></FONT>
</P>

<P><FONT SIZE=3D2>CALL FOR PRESENTATIONS:</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
We are also open to technical presentations (usually 30</FONT>
<BR><FONT SIZE=3D2>minutes</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
or less) related to any current IBIS activity and to future</FONT>
<BR><FONT SIZE=3D2>IBIS</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
needs.</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Contact Guy de Burgh regarding your presentation:</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; Presenter:</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; Title:</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; Estimated Time:</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
We are providing an LCD Projector and an Overhead Projector.</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Please plan to bring foils for backup, if needed.</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
We would like you to provide handouts for the meeting (about</FONT>
<BR><FONT SIZE=3D2>25)</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
and also an electronic copy for archiving.</FONT>
</P>

<P><FONT SIZE=3D2>CALL FOR ATTENDEES:</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Please let Guy de Burgh know if you are planning to attend so</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
we have an estimate on food requirements.</FONT>
</P>

<P><FONT SIZE=3D2>CONTACT:&nbsp;&nbsp; Guy de Burgh</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
IBIS Secretary</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
[email-masked]</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
(805) 988-8250 ext. 6823</FONT>
</P>

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------------------------------

Date: Fri, 12 Apr 2002 08:25:34 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] Agenda, IBIS Teleconference Meeting 4/19

		     IBIS Open Forum Meeting Agenda
			      for 4/19/02

		 Bridge Number    Reservation #   Passcode
             1-888-316-5901   N/A             7095323
             (International Dial-In: 1-617-801-9781)

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Stephen Peters and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Peters

     - Intros of New IBIS Participants, Meeting Quorum       Peters
     - Membership Update and Treasurers Report               Fleming/Ross
     - Review of Previous Meeting's Minutes (and ARs)        Peters
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Leventhal, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters
     - JEDEC JC-16 Modeling and Testing                      Sessions
     - T10, Project 1414-DT - SCSI Signal Modeling           Barnes

     Design Automation Conference IBIS Summit Meeting        Ross

     IBIS Qualification Committee                            Katz

     IBIS Model Review Committee                             Ross

     Majordomo Update                                        Angulo

     New Administrative Issues                               All

8:45 Technical Discussion

     IBIS Version 4.0 Review                                 Peters

     Connector & Futures Group Report                        Peters

     BIRD 74 - EMI Parameters                                DeBurg

     BIRD 75 - Multi-Lingual IBIS Modeling Support           Ross

     ibischk3 Status                                         Ross
     - BUG68 - False Messages with Repeated Voltages         Mirmak

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Peters

9:55 Sign Off

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------------------------------

Date: Fri, 12 Apr 2002 10:46:51 -0700 (PDT)
From: Syed Huq <[email-masked]>
Subject: [IBIS-Users] ERROR in .pkg file

Hi,

The IBIS parser gives the following ERROR on a .pkg file:

ERROR (line 5100) -
    This Row Column Index defines an entry in the lower matrix triangle.
ERROR (line 5101) -
    This Row Column Index defines an entry in the lower matrix triangle.

<extracted from .pkg file>

  5098  [Row] AV35
  5099  AV35   1.60634E-08
  5100  AV34   8.46141E-09  <--Error on this line
  5101  AW35   1.00513E-08  <--Error on this line
  5102  [Row] F23
  
Can anyone give a bit more detailed explanation of what this ERROR
message from the parser means and how to debug this ?

I wish the parser output was more descriptive..What is a lower matrix 
triangle..

Syed  

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------------------------------

Date: Fri, 12 Apr 2002 14:20:28 -0500
From: "Dunbar, Tony" <[email-masked]>
Subject: RE: [IBIS-Users] ERROR in .pkg file

Syed,

A lower matrix triangle refers to the row/column section of a matrix below
the main diagonal. Only the upper-half matrix should be used. Symmetry in
the usual Maxwell matrix means this is sufficient.

The numbers in your example look like they are probably from the inductance
matrix, but I'm guessing just from the scale of the numbers.

What type of (inductance) matrix are you meant to be using, according to
what is specified in the .pkg file? Banded, Sparse or Full? The format of
your example looks like Sparse.

I'm guessing that the source of your problem is that the index AV34 is
alpanumerically before the current [Row] AV35 and this conflicts with the
ordering defined in the [Pin Numbers] section and the reconstruction of the
matrix attempts to place it in the lower-half.

Errr, unless there's a bug in the parser!?

Regards,
Tony

- -----Original Message-----
From: Syed Huq [mailto:[email-masked]]
Sent: Friday, April 12, 2002 12:47 PM
To: [email-masked]
Subject: [IBIS-Users] ERROR in .pkg file

Hi,

The IBIS parser gives the following ERROR on a .pkg file:

ERROR (line 5100) -
    This Row Column Index defines an entry in the lower matrix triangle.
ERROR (line 5101) -
    This Row Column Index defines an entry in the lower matrix triangle.

<extracted from .pkg file>

  5098  [Row] AV35
  5099  AV35   1.60634E-08
  5100  AV34   8.46141E-09  <--Error on this line
  5101  AW35   1.00513E-08  <--Error on this line
  5102  [Row] F23
  
Can anyone give a bit more detailed explanation of what this ERROR
message from the parser means and how to debug this ?

I wish the parser output was more descriptive..What is a lower matrix 
triangle..

Syed  

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------------------------------

Date: Mon, 15 Apr 2002 13:48:56 -0400
From: "Timothy Coyle" <[email-masked]>
Subject: [IBIS-Users] R fixture with Differential

This is a multipart message in MIME format.
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Hi,
I am trying to extract V-T data from a differential buffer. The outputs 
are terminated by 100 Ohms. (LVDS) In order to keep the outputs operating 
correctly, each output is tied to
R/2 to Vos.  What should I specify in IBIS for R_fixture? Is it 50 Ohms to 
1.2V, as the data is taken? Or is it 100 ohms to 1.2V? It seems when I 
specify R_fixture as 50 ohms,
I get a small 20 mV glitch on my edges when I run the IBIS file in HSPICE. 
(not sure if this is causing it or not) 

Any comments appreciated.

Tim

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Content-Transfer-Encoding: 7bit

<br><font size=2 face="sans-serif">Hi,</font>
<br><font size=2 face="sans-serif">I am trying to extract V-T data from a differential buffer. The outputs are terminated by 100 Ohms. (LVDS) In order to keep the outputs operating correctly, each output is tied to</font>
<br><font size=2 face="sans-serif">R/2 to Vos. &nbsp;What should I specify in IBIS for R_fixture? Is it 50 Ohms to 1.2V, as the data is taken? Or is it 100 ohms to 1.2V? It seems when I specify R_fixture as 50 ohms,</font>
<br><font size=2 face="sans-serif">I get a small 20 mV glitch on my edges when I run the IBIS file in HSPICE. (not sure if this is causing it or not) </font>
<br>
<br><font size=2 face="sans-serif">Any comments appreciated.</font>
<br>
<br><font size=2 face="sans-serif">Tim</font>
<br>
- --=_alternative 00629A5685256B9C_=--

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------------------------------

Date: Mon, 15 Apr 2002 13:07:29 -0500
From: "Yaping Zhou" <[email-masked]>
Subject: [IBIS-Users] SSO effect

Hi, all:

This is an excerption from IBIS Cookbook. I have one question about it, and
need your help.

"Inclusion of SSO Effects

Closely related to the discussion on model limits is the decision on how to
include Simultaneous Switching Output (SSO) effects.  SSO effects can be
included explicitly in a model by measuring the I/V and edge rate
characteristics under SSO conditions.  For example, a buffers I/V
characteristic can be measured with all the adjacent buffers turned on and
sinking current, or the buffers edge rate may be measured while adjacent
buffers are also switching.  Alternatively, a model that represents a single
buffer in isolation may be created, then several buffers may be connected to
a common power or ground rail via the [Pin Mapping] keyword.  The former
method (including SSO effects in the models' I/V and edge rate tables) has
the advantage that the resulting model is straight forward to verify and
less dependent on any particular simulators capability.  Note however, the
[Pin Mapping] keyword method does give the user the ability to perform
explicit ground bounce simulations and devise specific 'what if' scenarios.
"

When [Pin Mapping] is used, do we still need to measure V-I under SSO
condition? I think we should because we need to know how buffers respond
when voltage droop happens due to simultanuous switching.

Thanks in advance.

Yaping Zhou

Motorola Inc.

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------------------------------

Date: Wed, 17 Apr 2002 08:58:22 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: RE: [IBIS-Users] Measuring Ccomp in HSPICE

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

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Hello Tim:
 
  There are a number of methods, but whatever method is chosen recognize
that C_comp of an output buffer is a function of the pad voltage and
transistor bias.  I.e. just extracting the min and max pad capacitance from
a placed and routed buffer design will not be as accurate as doing an in
circuit test.  One method I've used for tri-stateable buffers and input
buffers is as follows:
 
1. In your simulation environment, apply power to the buffer and set the
controls so that the output is in a high impedance  state.
2. Thru a series resistor, connect a pulse source to the buffers input or
output node.
3. apply a very fast (<5ps rising edge) step to the resistor.  Amplitude of
the step should be close to VCC.  Observe the RC waveform at the output or
input node of the buffer, and calculate the C_comp value from the standard
RC time constant equation.
 
  Regards,
  Stephen

- -----Original Message-----
From: Timothy Coyle [mailto:[email-masked]]
Sent: Friday, April 05, 2002 1:32 PM
To: [email-masked]
Subject: [IBIS-Users] Measuring Ccomp in HSPICE

Hello, 
I'm looking for a way to obtain ccomp for inputs/outputs in HSPICE for IBIS.
I would like to be able to get ccomp min and max values from 
simulation. 

Thanks, 
Tim 

- ------_=_NextPart_001_01C1E628.B33F6080
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	charset="ISO-8859-1"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=ISO-8859-1">

<META content="MSHTML 5.00.3315.2870" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=628393415-17042002>Hello 
Tim:</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=628393415-17042002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=628393415-17042002>&nbsp; 
There are a number of methods, but whatever method is chosen recognize that 
C_comp of an output buffer is a function of the pad voltage and transistor 
bias.&nbsp; I.e. just extracting the min and max pad capacitance from a placed 
and routed buffer design will not be as accurate as doing an in circuit 
test.&nbsp;&nbsp;One method I've used for tri-stateable buffers and input 
buffers is as follows:</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=628393415-17042002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=628393415-17042002>1. In 
your simulation environment,&nbsp;apply power to the buffer and set the controls 
so that the output is in a high impedance&nbsp; state.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=628393415-17042002>2. 
Thru a series resistor, connect a pulse source to the buffers input or 
output&nbsp;node.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=628393415-17042002>3. 
apply a very fast (&lt;5ps rising edge) step to the resistor.&nbsp; Amplitude of 
the step should be close to VCC.&nbsp; Observe the RC waveform at the output or 
input node of the buffer, and calculate the C_comp value from the standard RC 
time constant equation.</SPAN></FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=628393415-17042002>&nbsp; 
Regards,</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=628393415-17042002>&nbsp; 
Stephen</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=628393415-17042002></SPAN></FONT>&nbsp;</DIV>
<BLOCKQUOTE>
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma 
  size=2>-----Original Message-----<BR><B>From:</B> Timothy Coyle 
  [mailto:[email-masked]]<BR><B>Sent:</B> Friday, April 05, 2002 1:32 
  PM<BR><B>To:</B> [email-masked]<BR><B>Subject:</B> [IBIS-Users] 
  Measuring Ccomp in HSPICE<BR><BR></DIV></FONT><BR><FONT face=sans-serif 
  size=2>Hello,</FONT> <BR><FONT face=sans-serif size=2>I'm looking for a way to 
  obtain ccomp for inputs/outputs in HSPICE for IBIS. &nbsp;I would like to be 
  able to get ccomp min and max values from</FONT> <BR><FONT face=sans-serif 
  size=2>simulation.</FONT> <BR><BR><FONT face=sans-serif size=2>Thanks,</FONT> 
  <BR><FONT face=sans-serif size=2>Tim</FONT> <BR></BLOCKQUOTE></BODY></HTML>

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Date: Fri, 19 Apr 2002 14:23:59 -0400
From: "Timothy Coyle" <[email-masked]>
Subject: [IBIS-Users] I-V vs V-T curves

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Hi,
I am trying to determine where my mismatch end points are coming  from in 
an IBIS file I am creating.  How do I get the end points from the pullup 
and pulldown I-V data
so I can compare them to the endpoints in my V-T curves? (load condition 
for V-T data is 50 ohms to 1.2V with endpoints 1.0V and 1.4V)

Thanks,
Tim

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<br><font size=2 face="sans-serif">Hi,</font>
<br><font size=2 face="sans-serif">I am trying to determine where my mismatch end points are coming &nbsp;from in an IBIS file I am creating. &nbsp;How do I get the end points from the pullup and pulldown I-V data</font>
<br><font size=2 face="sans-serif">so I can compare them to the endpoints in my V-T curves? (load condition for V-T data is 50 ohms to 1.2V with endpoints 1.0V and 1.4V)</font>
<br>
<br><font size=2 face="sans-serif">Thanks,</font>
<br><font size=2 face="sans-serif">Tim</font>
<br>
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Date: Mon, 22 Apr 2002 07:54:12 +0200
From: Lenski Eckhard <[email-masked]>
Subject: AW: [IBIS-Users] I-V vs V-T curves

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Hello Tim,
=20
I assume that you are modeling an LVDS-output.
=20
Normaly ( cmos ) you compare the crossing of the 50Ohmload curves with =
the pullup - pulldown curves=20
=20
- - 50 Ohm to Gnd  crossing with pullup curve
- - 50 Ohm to Vcc  crossing with pulldown curve
=20
and the  rising falling waveforms are measured with a 50 Ohm load to =
GND and to VCC.
=20
For LVDS you have to look for the crossing of your 50 Ohm to 1.2V  =
load-curve  with the pullup and pulldown curves=20
( so you havve to use the same loadcurve twice )=20
and then there should be no ( or no significant )  mismatch.
=20
By the way, I think the ibis-checker is always using 50 ohm to gnd and =
50 Ohm to vcc.
=20
=20
If you have further questions, please let me know.
=20
regards=20
Eckhard Lenski=20
=20

Eckhard Lenski=20
Siemens AG=20
ICN WN OP TDC TC3=20
81359 M=FCnchen=20
Tel:      0049 89 722 27776=20
Fax:     0049 89 722 44692=20
Email:  [email-masked]=20

- -----Urspr=FCngliche Nachricht-----
Von: Timothy Coyle [mailto:[email-masked]]
Gesendet: Freitag, 19. April 2002 20:24
An: [email-masked]
Betreff: [IBIS-Users] I-V vs V-T curves

Hi,=20
I am trying to determine where my mismatch end points are coming  from =
in an IBIS file I am creating.  How do I get the end points from the =
pullup and pulldown I-V data=20
so I can compare them to the endpoints in my V-T curves? (load =
condition for V-T data is 50 ohms to 1.2V with endpoints 1.0V and 1.4V) =

Thanks,=20
Tim=20

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3DISO-8859-1">

<META content=3D"MSHTML 5.50.4915.500" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D600504605-22042002>Hello=20
Tim,</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D600504605-22042002>I=20
assume that you are modeling an LVDS-output.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002>Normaly ( cmos ) you compare the crossing =
of&nbsp;the=20
50Ohmload curves with the pullup - pulldown curves </SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D600504605-22042002>- 50=20
Ohm to Gnd&nbsp; crossing with pullup curve</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D600504605-22042002>- 50=20
Ohm to Vcc&nbsp; crossing with pulldown curve</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D600504605-22042002>and=20
the&nbsp; rising falling waveforms are measured with a 50 Ohm load to =
GND and to=20
VCC.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D600504605-22042002>For=20
LVDS you have to look for the crossing of your 50 Ohm to 1.2V&nbsp;=20
load-curve&nbsp; with the pullup and pulldown curves =
</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D600504605-22042002>(=20
</SPAN></FONT><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002>so you havve to use the same loadcurve twice =

)&nbsp;</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D600504605-22042002>and=20
then there should be no ( or no significant )&nbsp;=20
mismatch.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D600504605-22042002>By the=20
way, I think the ibis-checker&nbsp;is always&nbsp;using 50 ohm to gnd =
and 50 Ohm=20
to vcc.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN =
class=3D600504605-22042002>If you=20
have further questions, please let me know.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002>regards&nbsp;</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D600504605-22042002>Eckhard Lenski&nbsp;</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2></FONT>&nbsp;</DIV>
<P><B><FONT face=3DArial size=3D2>Eckhard Lenski</FONT></B> =
<BR><B><FONT face=3DArial=20
size=3D2>Siemens AG</FONT></B> <BR><B><FONT face=3DArial size=3D2>ICN =
WN OP TDC=20
TC3</FONT></B> <BR><B><FONT face=3DArial size=3D2>81359 =
M=FCnchen</FONT></B>=20
<BR><B><FONT face=3DArial size=3D2>Tel:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
0049 89 722=20
27776</FONT></B> <BR><B><FONT face=3DArial =
size=3D2>Fax:&nbsp;&nbsp;&nbsp;&nbsp;=20
0049 89 722 44692</FONT></B> <BR><B><FONT face=3DArial =
size=3D2>Email:&nbsp;=20
[email-masked]</FONT></B> </P>
<BLOCKQUOTE>
  <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
  size=3D2>-----Urspr=FCngliche Nachricht-----<BR><B>Von:</B> Timothy =
Coyle=20
  [mailto:[email-masked]]<BR><B>Gesendet:</B> Freitag, 19. April =
2002=20
  20:24<BR><B>An:</B> [email-masked]<BR><B>Betreff:</B> =
[IBIS-Users] I-V vs=20
  V-T curves<BR><BR></FONT></DIV><BR><FONT face=3Dsans-serif =
size=3D2>Hi,</FONT>=20
  <BR><FONT face=3Dsans-serif size=3D2>I am trying to determine where =
my mismatch=20
  end points are coming &nbsp;from in an IBIS file I am creating. =
&nbsp;How do I=20
  get the end points from the pullup and pulldown I-V data</FONT> =
<BR><FONT=20
  face=3Dsans-serif size=3D2>so I can compare them to the endpoints in =
my V-T=20
  curves? (load condition for V-T data is 50 ohms to 1.2V with =
endpoints 1.0V=20
  and 1.4V)</FONT> <BR><BR><FONT face=3Dsans-serif =
size=3D2>Thanks,</FONT> <BR><FONT=20
  face=3Dsans-serif size=3D2>Tim</FONT> <BR></BLOCKQUOTE></BODY></HTML>

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------------------------------

Date: Mon, 22 Apr 2002 14:50:40 -0400
From: "Timothy Coyle" <[email-masked]>
Subject: [IBIS-Users] Input ESD Structures

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Hello,
When I get a SPICE netlist from the design team to do a spi2ibis 
translation, the ESD structures have ideal diodes (no resistance) which 
leads to kAmps in my
power and ground clamp curves.  So I put a series resistor of 1-3 Ohms on 
the input of the ESD pad (and sometimes the ground node of the ESD pad) to 
try to limit
the current.  While this approach works, my simulated data does not match 
up with data taken from the bench.  The lab data at one point is 4.3mA and 
the simulated
data at the same point is 160uA for a ground clamp curve.  Changing the 
resistor value doesn't give me the right current either.  Does anyone have 
any 
comments/suggestions on this approach? 

Also, I'm wondering what type of affect on my input model the magnitudes 
of my power and ground clamp curves have. Does it matter to a simulator if 
the ground clamp
current is 4.3mA or 160uA? It seems the most important parameter for an 
input model is Ccomp. Has anyone done any work on this they would like to 
share? 

Many thanks again to those who respond,

Tim

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<br><font size=2 face="sans-serif">Hello,</font>
<br><font size=2 face="sans-serif">When I get a SPICE netlist from the design team to do a spi2ibis translation, the ESD structures have ideal diodes (no resistance) which leads to kAmps in my</font>
<br><font size=2 face="sans-serif">power and ground clamp curves. &nbsp;So I put a series resistor of 1-3 Ohms on the input of the ESD pad (and sometimes the ground node of the ESD pad) to try to limit</font>
<br><font size=2 face="sans-serif">the current. &nbsp;While this approach works, my simulated data does not match up with data taken from the bench. &nbsp;The lab data at one point is 4.3mA and the simulated</font>
<br><font size=2 face="sans-serif">data at the same point is 160uA for a ground clamp curve. &nbsp;Changing the resistor value doesn't give me the right current either. &nbsp;Does anyone have any </font>
<br><font size=2 face="sans-serif">comments/suggestions on this approach? </font>
<br>
<br><font size=2 face="sans-serif">Also, I'm wondering what type of affect on my input model the magnitudes of my power and ground clamp curves have. Does it matter to a simulator if the ground clamp</font>
<br><font size=2 face="sans-serif">current is 4.3mA or 160uA? It seems the most important parameter for an input model is Ccomp. Has anyone done any work on this they would like to share? </font>
<br>
<br><font size=2 face="sans-serif">Many thanks again to those who respond,</font>
<br>
<br><font size=2 face="sans-serif">Tim</font>
<br>
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------------------------------

Date: Tue, 23 Apr 2002 11:28:33 -0400
From: "Lynne Green" <[email-masked]>
Subject: RE: [IBIS-Users] Input ESD Structures

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Hello, Tim,
=20
The 3 most significant DC parameters in the diode model:
IS: "reverse leakage" current, adjusted to give correct forward current
at low bias voltage (V<0.4V in silicon).  Ranges from around 1e-16
for signal diodes to >1e-9 for power diodes.
N: ideality factor, adjusted to give correct forward current at medium
bias (0.5V to 0.6V in silicon).  Usually 1<N<2.
RS: series resistance, adjusted to give correct forward current at=20
high bias (V>0.7V in silicon).  Typically 0.1 to 10 ohms.
=20
You need at least 3 I-V points to get these parameters.  More will
give a better least-squares fit.
=20
Model needs to be accurate over actual operating conditions,=20
including reflections.  This should cover from Vcc of reverse
voltage to about 1V of forward voltage.  Maximum current should not
exceed 100 mA, even outside this region.  SiQual has addressed
diode models in the reflector, with comparison to measurements.
=20
Best regards,
Lynne=20
=20
Dr. Lynne Green
PCB Systems Division
Cadence Design Systems, Inc.

- -----Original Message-----
From: Timothy Coyle [mailto:[email-masked]]
Sent: Monday, April 22, 2002 11:51 AM
To: [email-masked]
Subject: [IBIS-Users] Input ESD Structures

Hello,=20
When I get a SPICE netlist from the design team to do a spi2ibis =
translation, the ESD structures have ideal diodes (no resistance) which =
leads to kAmps in my=20
power and ground clamp curves.  So I put a series resistor of 1-3 Ohms =
on the input of the ESD pad (and sometimes the ground node of the ESD =
pad) to try to limit=20
the current.  While this approach works, my simulated data does not =
match up with data taken from the bench.  The lab data at one point is =
4.3mA and the simulated=20
data at the same point is 160uA for a ground clamp curve.  Changing the =
resistor value doesn't give me the right current either.  Does anyone =
have any=20
comments/suggestions on this approach?=20

Also, I'm wondering what type of affect on my input model the magnitudes =
of my power and ground clamp curves have. Does it matter to a simulator =
if the ground clamp=20
current is 4.3mA or 160uA? It seems the most important parameter for an =
input model is Ccomp. Has anyone done any work on this they would like =
to share?=20

Many thanks again to those who respond,=20

Tim=20

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<BODY>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2>Hello, =

Tim,</FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial=20
size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2>The 3 =
most=20
significant DC parameters in the diode model:</FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2>IS: =
"reverse=20
leakage" current, adjusted to give correct forward =
current</FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2>at low =
bias voltage=20
(V&lt;0.4V in silicon).&nbsp; Ranges from around =
1e-16</FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2>for =
signal diodes=20
</FONT></SPAN><SPAN class=3D965280815-23042002><FONT face=3DArial =
size=3D2>to &gt;1e-9=20
for power diodes.</FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2>N: =
ideality factor,=20
adjusted to give correct forward current at medium</FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2>bias =
(0.5V to 0.6V=20
in silicon).&nbsp; Usually 1&lt;N&lt;2.</FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2>RS: =
series=20
resistance, adjusted to give correct forward current at =
</FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2>high =
<SPAN=20
class=3D965280815-23042002><FONT face=3DArial size=3D2>bias (V&gt;0.7V =
in=20
silicon).&nbsp; Typically 0.1 to 10 =
ohms.</FONT></SPAN></FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002></SPAN></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>You need at least 3 I-V points to get these=20
parameters.&nbsp; More will</SPAN></FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>give </SPAN></FONT></SPAN><SPAN=20
class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>a better least-squares =
fit.</SPAN></FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002></SPAN></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>Model needs to be accurate over actual =
operating=20
conditions, </SPAN></FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>including reflections.&nbsp; This should =
cover from Vcc=20
of reverse</SPAN></FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>voltage to about 1V of forward voltage.&nbsp; =
Maximum=20
current should not</SPAN></FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>exceed 100 mA, even outside this =
region.&nbsp; SiQual=20
has addressed</SPAN></FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>diode models in the =
</SPAN></FONT></SPAN><SPAN=20
class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>reflector, with comparison to=20
measurements.</SPAN></FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002></SPAN></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>Best regards,</SPAN></FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>Lynne </SPAN></FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002></SPAN></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>Dr. Lynne Green</SPAN></FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>PCB Systems =
Division</SPAN></FONT></SPAN></DIV>
<DIV><SPAN class=3D965280815-23042002><FONT face=3DArial size=3D2><SPAN=20
class=3D965280815-23042002>Cadence Design Systems, =
Inc.</SPAN></DIV></FONT></SPAN>
<BLOCKQUOTE>
  <DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B> Timothy Coyle=20
  [mailto:[email-masked]]<BR><B>Sent:</B> Monday, April 22, 2002 =
11:51=20
  AM<BR><B>To:</B> [email-masked]<BR><B>Subject:</B> [IBIS-Users] =
Input ESD=20
  Structures<BR><BR></FONT></DIV><BR><FONT face=3Dsans-serif =
size=3D2>Hello,</FONT>=20
  <BR><FONT face=3Dsans-serif size=3D2>When I get a SPICE netlist from =
the design=20
  team to do a spi2ibis translation, the ESD structures have ideal =
diodes (no=20
  resistance) which leads to kAmps in my</FONT> <BR><FONT =
face=3Dsans-serif=20
  size=3D2>power and ground clamp curves. &nbsp;So I put a series =
resistor of 1-3=20
  Ohms on the input of the ESD pad (and sometimes the ground node of the =
ESD=20
  pad) to try to limit</FONT> <BR><FONT face=3Dsans-serif size=3D2>the =
current.=20
  &nbsp;While this approach works, my simulated data does not match up =
with data=20
  taken from the bench. &nbsp;The lab data at one point is 4.3mA and the =

  simulated</FONT> <BR><FONT face=3Dsans-serif size=3D2>data at the same =
point is=20
  160uA for a ground clamp curve. &nbsp;Changing the resistor value =
doesn't give=20
  me the right current either. &nbsp;Does anyone have any =
</FONT><BR><FONT=20
  face=3Dsans-serif size=3D2>comments/suggestions on this approach?=20
  </FONT><BR><BR><FONT face=3Dsans-serif size=3D2>Also, I'm wondering =
what type of=20
  affect on my input model the magnitudes of my power and ground clamp =
curves=20
  have. Does it matter to a simulator if the ground clamp</FONT> =
<BR><FONT=20
  face=3Dsans-serif size=3D2>current is 4.3mA or 160uA? It seems the =
most important=20
  parameter for an input model is Ccomp. Has anyone done any work on =
this they=20
  would like to share? </FONT><BR><BR><FONT face=3Dsans-serif =
size=3D2>Many thanks=20
  again to those who respond,</FONT> <BR><BR><FONT face=3Dsans-serif=20
  size=3D2>Tim</FONT> <BR></BLOCKQUOTE></BODY></HTML>

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------------------------------

Date: Tue, 23 Apr 2002 19:07:22 -0500
From: "Haque, Moshiul" <[email-masked]>
Subject: [IBIS-Users] Model Selector Keyword for Series Pin Mapping 

Hi All,
While creating an IBIS model for series switch, I have noticed that the
IBISCHK3.2 gives an error if the model selector keyword is used to define
two different models for the same model_name in series pin mapping.
IBISCHK3.2 gives an error saying that the model (that is defined in the
series pin mapping under model_name column) is not defined. Model selector
keyword works fine for other models (input, terminator or 3-state) Any idea
what did I do wrong? 

[Series Pin Mapping]   pin_2  model_name     function_table_group
|
3                      		2    Q3384A_IO_S          1

[Model Selector]       Q3384A_IO_S
|
Q3384A_IO_S_33         3.3 volt Vcc  
Q3384A_IO_S_25         2.5 volt Vcc  

If I use two different series pin mapping with separate model but with same
pin mapping will that be an incorrect approach?
 
Example: 
[Series Pin Mapping]   pin_2  model_name     function_table_group
|
3                      		2    Q3384A_IO_S_25          1
3                      		2    Q3384A_IO_S_33          1
 
Any suggestion would be greatly appreciated.

Regards
Moshiul Haque	             
Standard Linear and Logic Marketing
Texas Instruments Incorporated                
  	        
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------------------------------

Date: Wed, 24 Apr 2002 17:14:20 -0700
From: "Ross, Bob" <[email-masked]>
Subject: Re: [IBIS-Users] Model Selector Keyword for Series Pin Mapping

Hello Moshiul:

I believe [Model Selector] should work with Series or
Series_switch models that would be listed using 
{Series Pin Mapping].  So it looks like you have
uncovered an ibischk3 bug.

Could you send me directly a complete (but simplified) test
model that demonstrates the Error.  I want to check to see if there
are any other related issues.

Your second case is not correct for the purposes of connecting
one switch at a time.  Both are connected in parallel.  However,
if manually comment one line or the other, then it would work
for just those pins.

Best Regards,
Bob Ross
Mentor Graphics

"Haque, Moshiul" wrote:
> 
> Hi All,
> While creating an IBIS model for series switch, I have noticed that the
> IBISCHK3.2 gives an error if the model selector keyword is used to define
> two different models for the same model_name in series pin mapping.
> IBISCHK3.2 gives an error saying that the model (that is defined in the
> series pin mapping under model_name column) is not defined. Model selector
> keyword works fine for other models (input, terminator or 3-state) Any idea
> what did I do wrong?
> 
> [Series Pin Mapping]   pin_2  model_name     function_table_group
> |
> 3                               2    Q3384A_IO_S          1
> 
> [Model Selector]       Q3384A_IO_S
> |
> Q3384A_IO_S_33         3.3 volt Vcc
> Q3384A_IO_S_25         2.5 volt Vcc
> 
> If I use two different series pin mapping with separate model but with same
> pin mapping will that be an incorrect approach?
> 
> Example:
> [Series Pin Mapping]   pin_2  model_name     function_table_group
> |
> 3                               2    Q3384A_IO_S_25          1
> 3                               2    Q3384A_IO_S_33          1
> 
> Any suggestion would be greatly appreciated.
> 
> Regards
> Moshiul Haque
> Standard Linear and Logic Marketing
> Texas Instruments Incorporated
>
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------------------------------

Date: Wed, 24 Apr 2002 18:10:30 -0700
From: "Ross, Bob" <[email-masked]>
Subject: Re: AW: [IBIS-Users] I-V vs V-T curves

Hello Tim:

Actually, ibischk3 should work correctly for any set of
waveform endpoints based on R_fixture and V_fixture values.

The manual calculation of voltage can be done by iteration.
You assume a voltage, and then calculate the current needed
to supply R_fixture and V_fixture for either the high state
hen you add up the currents supplied by the [Pullup] table
(plus the [Gnd Clamp] and [Power Clamp] tables for the assumed
voltage.

If the currents are different, readjust the voltage in
the correct direction and repeat.  Eventually you should
converge on the solution.

Then you repeat this process for the low state using the
[Pulldown] table and clamps.

Bob Ross
Mentor Graphics

Lenski Eckhard wrote:
> 
> Hello Tim,
> 
> I assume that you are modeling an LVDS-output.
> 
> Normaly ( cmos ) you compare the crossing of the 50Ohmload curves with the
> pullup - pulldown curves
> 
> - 50 Ohm to Gnd  crossing with pullup curve
> - 50 Ohm to Vcc  crossing with pulldown curve
> 
> and the  rising falling waveforms are measured with a 50 Ohm load to GND and
> to VCC.
> 
> For LVDS you have to look for the crossing of your 50 Ohm to 1.2V  load-curve
> with the pullup and pulldown curves
> ( so you havve to use the same loadcurve twice )
> and then there should be no ( or no significant )  mismatch.
> 
> By the way, I think the ibis-checker is always using 50 ohm to gnd and 50 Ohm
> to vcc.
> 
> 
> If you have further questions, please let me know.
> 
> regards
> Eckhard Lenski
> 
> 
> Eckhard Lenski
> Siemens AG
> ICN WN OP TDC TC3
> 81359 München
> Tel:      0049 89 722 27776
> Fax:     0049 89 722 44692
> Email:  [email-masked]
> 
>      -----Ursprüngliche Nachricht-----
>      Von: Timothy Coyle [mailto:[email-masked]]
>      Gesendet: Freitag, 19. April 2002 20:24
>      An: [email-masked]
>      Betreff: [IBIS-Users] I-V vs V-T curves
> 
>      Hi,
>      I am trying to determine where my mismatch end points are coming
>       from in an IBIS file I am creating.  How do I get the end points
>      from the pullup and pulldown I-V data
>      so I can compare them to the endpoints in my V-T curves? (load
>      condition for V-T data is 50 ohms to 1.2V with endpoints 1.0V and
>      1.4V)
> 
>      Thanks,
>      Tim
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------------------------------

Date: Wed, 1 May 2002 11:51:06 -0400 
From: Guy deBurgh <[email-masked]>
Subject: [IBIS-Users] DAC 2002 IBIS Summit meeting

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C1F128.1D8F4900
Content-Type: text/plain;
	charset="iso-8859-1"

            D A C   2 0 0 2   I B I S   S U M M I T   M E E T I N G
                      S E C O N D   A N N O U N C E M E N T

DATE:      Thursday, June 13, 2002
TIME:      8:30 AM - 5:00 PM

CITY:      New Orleans, Louisiana

LOCATION:  Hilton Hotel, New Orleans Riverside, next to Ernest N. Morial

           Convention Center where the Design Automation Conference
(DAC)
           is being held.

ROOM:      To be Announced

LUNCH:     Free Refreshments and Lunch will be provided.

AGENDA:    The agenda is being planned.  Some possible items are:

             Presentation of Awards
             Election of Officers for 2002 - 2003

             Connector Specification
             EMI Modeling
             IBIS Version 4.0 Review
             Modeling Experiences, Problems and Solutions

           The following presentations are tentatively planned (titles
may
           change):

             "Use of IBIS in Digital Consumer Electronics", Atsuji Ito,
                Matsushita Electric Industrial Co. (Panasonic)
             "Semiconductor Modeling", Roy Leventhal, Independent
             "IBIS Quality Checklist", Barry Katz, SiSoft
             "Multi-Lingual Modeling Applications", Bob Ross, Mentor
Graphics
             "IBIS Report", Stephen Peters, Intel Corporation

           We welcome presentations and discussions on IBIS topics.

DAC 2001:  DAC is scheduled Monday - Friday, June 10 - 14, 2002.
           The exhibitor portion is open from Monday - Wednesday.
           For more information on DAC 2002 activities, housing, etc.,
           visit the DAC URL:

DAC URL:   http://www.dac.com/

CALL FOR PRESENTATIONS:

           We are also open to technical presentations (usually 30
minutes
           or less) related to any current IBIS activity and to future
IBIS
           needs.

           Contact Guy de Burgh regarding your presentation:

              Presenter:
              Title:
              Estimated Time:

           We are providing an LCD Projector and an Overhead Projector.
           Please plan to bring foils for backup, if needed.

           We would like you to provide handouts for the meeting (about
25)
           and also an electronic copy for archiving.

CALL FOR ATTENDEES:

           Please let Guy de Burgh know if you are planning to attend so

           we have an estimate on food requirements.

CONTACT:   Guy de Burgh
           IBIS Secretary
           [email-masked]
           (805) 988-8250 ext. 6823

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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2653.12">
<TITLE>DAC 2002 IBIS Summit meeting</TITLE>
</HEAD>
<BODY>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp; D A C&nbsp;&nbsp; 2 0 0 2&nbsp;&nbsp; I B I S&nbsp;&nbsp; S U M M I =
T&nbsp;&nbsp; M E E T I N G</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; S E C O =
N D&nbsp;&nbsp; A N N O U N C E M E N T</FONT>
</P>

<P><FONT SIZE=3D2>DATE:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Thursday, June =
13, 2002</FONT>
<BR><FONT SIZE=3D2>TIME:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 8:30 AM - 5:00 =
PM</FONT>
</P>

<P><FONT SIZE=3D2>CITY:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; New Orleans, =
Louisiana</FONT>
</P>

<P><FONT SIZE=3D2>LOCATION:&nbsp; Hilton Hotel, New Orleans Riverside, =
next to Ernest N. Morial</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Convention Center where the Design Automation Conference</FONT>
<BR><FONT SIZE=3D2>(DAC)</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
is being held.</FONT>
</P>

<P><FONT SIZE=3D2>ROOM:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; To be =
Announced</FONT>
</P>

<P><FONT SIZE=3D2>LUNCH:&nbsp;&nbsp;&nbsp;&nbsp; Free Refreshments and =
Lunch will be provided.</FONT>
</P>

<P><FONT SIZE=3D2>AGENDA:&nbsp;&nbsp;&nbsp; The agenda is being =
planned.&nbsp; Some possible items are:</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Presentation of Awards</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Election of Officers for 2002 - 2003</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Connector Specification</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; EMI Modeling</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; IBIS Version 4.0 Review</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; Modeling Experiences, Problems and Solutions</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
The following presentations are tentatively planned (titles</FONT>
<BR><FONT SIZE=3D2>may</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
change):</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; &quot;Use of IBIS in Digital Consumer Electronics&quot;, =
Atsuji Ito,</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; Matsushita Electric Industrial Co. =
(Panasonic)</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; &quot;Semiconductor Modeling&quot;, Roy Leventhal, =
Independent</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; &quot;IBIS Quality Checklist&quot;, Barry Katz, SiSoft</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; &quot;Multi-Lingual Modeling Applications&quot;, Bob Ross, =
Mentor</FONT>
<BR><FONT SIZE=3D2>Graphics</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; &quot;IBIS Report&quot;, Stephen Peters, Intel =
Corporation</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
We welcome presentations and discussions on IBIS topics.</FONT>
</P>

<P><FONT SIZE=3D2>DAC 2001:&nbsp; DAC is scheduled Monday - Friday, =
June 10 - 14, 2002.</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
The exhibitor portion is open from Monday - Wednesday.</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
For more information on DAC 2002 activities, housing, etc.,</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
visit the DAC URL:</FONT>
</P>

<P><FONT SIZE=3D2>DAC URL:&nbsp;&nbsp; <A HREF=3D"http://www.dac.com/" =
TARGET=3D"_blank">http://www.dac.com/</A></FONT>
</P>

<P><FONT SIZE=3D2>CALL FOR PRESENTATIONS:</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
We are also open to technical presentations (usually 30</FONT>
<BR><FONT SIZE=3D2>minutes</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
or less) related to any current IBIS activity and to future</FONT>
<BR><FONT SIZE=3D2>IBIS</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
needs.</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Contact Guy de Burgh regarding your presentation:</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; Presenter:</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; Title:</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; Estimated Time:</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
We are providing an LCD Projector and an Overhead Projector.</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Please plan to bring foils for backup, if needed.</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
We would like you to provide handouts for the meeting (about</FONT>
<BR><FONT SIZE=3D2>25)</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
and also an electronic copy for archiving.</FONT>
</P>

<P><FONT SIZE=3D2>CALL FOR ATTENDEES:</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Please let Guy de Burgh know if you are planning to attend so</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
we have an estimate on food requirements.</FONT>
</P>

<P><FONT SIZE=3D2>CONTACT:&nbsp;&nbsp; Guy de Burgh</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
IBIS Secretary</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
[email-masked]</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
(805) 988-8250 ext. 6823</FONT>
</P>

</BODY>
</HTML>
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------------------------------

End of ibis-users V1 #5
***********************