Subject: ibis-users V1 #6
From: owner-ibis-users@ (ibis-users)
To: [email-masked]

ibis-users            Friday, June 28 2002            Volume 01 : Number 006

----------------------------------------------------------------------

Date: Fri, 3 May 2002 13:55:18 -0700 
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] IBIS Open Forum Teleconference Agenda, 5/10

		     IBIS Open Forum Meeting Agenda
			      for 5/10/02

		 Bridge Number    Reservation #   Passcode
             1-888-316-5901   N/A             6874860
             (International Dial-In: 1-617-801-9781)

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Stephen Peters and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Peters

     - Intros of New IBIS Participants, Meeting Quorum       Peters
     - Membership Update and Treasurers Report               Peters
     - Review of Previous Meeting's Minutes (and ARs)        Peters
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Leventhal, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters
     - JEDEC JC-16 Modeling and Testing                      Sessions
     - T10, Project 1414-DT - SCSI Signal Modeling           Barnes

     Design Automation Conference IBIS Summit Meeting        Ross

     IBIS Qualification Committee                            Katz

     IBIS Model Review Committee                             Ross

     Majordomo Update                                        Angulo

     New Administrative Issues                               All

8:45 Technical Discussion

     IBIS Version 4.0 Discussion/BIRD75                      Peters

     IBIS Version 4.0 Review                                 Peters

     Connector & Futures Group Report                        Peters

     BIRD 74 - EMI Parameters                                de Burg

     BIRD 75 - Multi-Lingual IBIS Modeling Support           Ross

     ibischk3 Status                                         Ross
     - BUG68 - False Messages with Repeated Voltages         Mirmak
     - BUG69 - Error in EBD Path with Power Pin              Ross/Flora
     - BUG70 - [Model Selector] Fails for [Series Pin        Ross/Haque
               Mapping] models

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Peters

9:55 Sign Off
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------------------------------

Date: Mon, 6 May 2002 10:30:06 -0700 (PDT)
From: whiz kid <[email-masked]>
Subject: [IBIS-Users] Slew Rate Question.

 

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------------------------------

Date: Mon, 6 May 2002 10:40:19 -0700 (PDT)
From: whiz kid <[email-masked]>
Subject: [IBIS-Users] Slew Rate Question.

Hi Folks,
I have an IBIS model from a vendor. I am trying to
change the slew rate. How do I go about changing the
slew rate. Is it fine if I just change the dV_r/dt and
dV_f/dt values under the Ramp Keyword or do I need to
mess with the Rising and Falling wave forms too. I
would really appreciate if some one can provide more
info on this one.

Thanks,
Rahul.

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------------------------------

Date: Mon, 6 May 2002 11:37:20 -0700
From: "Bill Hargin" <[email-masked]>
Subject: RE: [IBIS-Users] Slew Rate Question.

Hi Rahul:

You need to delete the [Rising Waveform] and [Falling Waveform] tables if
you want to be sure that the simulator will see your change to the slew
rates.

(Make sure and save the file under a different name first, and put in a note
in the header, unless you're going to be the only one with access to it.)

Best Regards,
Bill Hargin
Direct: 425-702-0744
Fax:    425-702-0305

Cognition Consulting
Electronic Design Software and Consulting
http://www.CognitionConsulting.com

> -----Original Message-----
> From: [email-masked] [mailto:[email-masked]]On
> Behalf Of whiz kid
> Sent: Monday, May 06, 2002 10:40 AM
> To: [email-masked]
> Subject: [IBIS-Users] Slew Rate Question.
>
>
> Hi Folks,
> I have an IBIS model from a vendor. I am trying to
> change the slew rate. How do I go about changing the
> slew rate. Is it fine if I just change the dV_r/dt and
> dV_f/dt values under the Ramp Keyword or do I need to
> mess with the Rising and Falling wave forms too. I
> would really appreciate if some one can provide more
> info on this one.
>
> Thanks,
> Rahul.
>
> __________________________________________________
> Do You Yahoo!?
> Yahoo! Health - your guide to health and wellness
> http://health.yahoo.com
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------------------------------

Date: Mon, 6 May 2002 11:49:39 -0700 
From: "Peters, Stephen" <[email-masked]>
Subject: RE: [IBIS-Users] Slew Rate Question.

Hi Rahul:

  Assuming your simulator is using the [Rising Waveform] and [Falling
Waveform] data (which it should be) changing the data under [Ramp] will not
effect the slew rate.  You will have to change the waveform data itself.

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: whiz kid [mailto:[email-masked]]
Sent: Monday, May 06, 2002 10:40 AM
To: [email-masked]
Subject: [IBIS-Users] Slew Rate Question.

Hi Folks,
I have an IBIS model from a vendor. I am trying to
change the slew rate. How do I go about changing the
slew rate. Is it fine if I just change the dV_r/dt and
dV_f/dt values under the Ramp Keyword or do I need to
mess with the Rising and Falling wave forms too. I
would really appreciate if some one can provide more
info on this one.

Thanks,
Rahul.

__________________________________________________
Do You Yahoo!?
Yahoo! Health - your guide to health and wellness
http://health.yahoo.com
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------------------------------

Date: Tue, 7 May 2002 10:14:51 +0200 
From: "Baumann, Hans-Gerhard" <[email-masked]>
Subject: [IBIS-Users] rising and falling wave forms in IBIS files

Hi,
    from IBIS class I learned that in order to model 
rising and falling wave forms it is required to provide
two plots for each transition. One with load resistor
to VDD and one with load resistor to GND.

The IBIS models I found on the WEB mostly provide only 
one plot for each transition. Can someone point me to a
model from that I could learn how to setup two rising 
and two falling wave forms with corresponding load 
within an IBIS model ?

Thanks and Best Regards
Gerd Baumann

- ---------------------------------------------------------------------------
EUROPEAN HPA PRODUCT ENGINEERING
Texas Instruments, Haggertystr. 1, D-85356 Freising, Germany
E-mail:  [email-masked]
Phone:  +49 8161 804341
Fax:    +49 8161 804909
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------------------------------

Date: Tue, 7 May 2002 07:49:12 -0700 
From: "Muranyi, Arpad" <[email-masked]>
Subject: RE: [IBIS-Users] rising and falling wave forms in IBIS files

Gerd,

You can check out the examples I have on the IBIS web site
under:

http://www.eda.org/pub/ibis/training/

in IBIS_class_JEDEC.zip.  The lab exercises have a few
HSPICE templates for various buffer types and they all
generate two waveforms per edge direction.

Arpad
========================================================

- -----Original Message-----
From: Baumann, Hans-Gerhard [mailto:[email-masked]]
Sent: Tuesday, May 07, 2002 1:15 AM
To: [email-masked]
Subject: [IBIS-Users] rising and falling wave forms in IBIS files

Hi,
    from IBIS class I learned that in order to model 
rising and falling wave forms it is required to provide
two plots for each transition. One with load resistor
to VDD and one with load resistor to GND.

The IBIS models I found on the WEB mostly provide only 
one plot for each transition. Can someone point me to a
model from that I could learn how to setup two rising 
and two falling wave forms with corresponding load 
within an IBIS model ?

Thanks and Best Regards
Gerd Baumann

- ---------------------------------------------------------------------------
EUROPEAN HPA PRODUCT ENGINEERING
Texas Instruments, Haggertystr. 1, D-85356 Freising, Germany
E-mail:  [email-masked]
Phone:  +49 8161 804341
Fax:    +49 8161 804909
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------------------------------

Date: Tue, 07 May 2002 16:22:24 -0700
From: "Ross, Bob" <[email-masked]>
Subject: Re: [IBIS-Users] rising and falling wave forms in IBIS files

Hello Gerd:

IBIS permits using just a RAMP or even one waveform
per edge.  The EDA tools should handle these cases.

In most cases two waveforms are recommended.  In some
cases for terminated technologies or for open_* devices,
one waveform gives excellent results for the operating
regions of interest.

Bob Ross
Mentor Graphics

"Baumann, Hans-Gerhard" wrote:
> 
> Hi,
>     from IBIS class I learned that in order to model
> rising and falling wave forms it is required to provide
> two plots for each transition. One with load resistor
> to VDD and one with load resistor to GND.
> 
> The IBIS models I found on the WEB mostly provide only
> one plot for each transition. Can someone point me to a
> model from that I could learn how to setup two rising
> and two falling wave forms with corresponding load
> within an IBIS model ?
> 
> Thanks and Best Regards
> Gerd Baumann
> 
> ---------------------------------------------------------------------------
> EUROPEAN HPA PRODUCT ENGINEERING
> Texas Instruments, Haggertystr. 1, D-85356 Freising, Germany
> E-mail:  [email-masked]
> Phone:  +49 8161 804341
> Fax:    +49 8161 804909
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------------------------------

Date: Wed, 15 May 2002 19:19:32 -0400
From: John Angulo <[email-masked]>
Subject: [IBIS-Users] FW: Announcement

Forwarded to the list on behalf of Scott McMorrow.
Please send private replies to <[email-masked]>:

To all my friends and colleagues,

I wanted to inform you that I have embarked on a new endeavor.  My new
e-mail address is:

[email-masked]

For those who might wonder, I will continue to be a contributor to the
SI reflector, the IBIS forums and continue to be an iconclast within the

engineering community.  I look forward to talks and collaborations with
many of you in the future.

Best regards,

Scott

- --
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com

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------------------------------

Date: Fri, 17 May 2002 11:05:35 +0900
From: Kazu Tsukada <[email-masked]>
Subject: [IBIS-Users] EBD [Path Description] question

Hello

I have a question about EBD Path Description.
V3.2 spec says that :
  |               The Len, L, R, and C subparameters specify the length, the
  |               series inductance, resistance, and the capacitance to ground
  |               of each section in a path description.
  |
  |               Len     The physical length of a section.  Lengths are given
  |                       in terms of arbitrary 'units'.  Any non-zero length
  |                       requires that the parameters that follow must be
  |                       interpreted as distributed elements by the simulator.
  |               L       The series inductance of a section, in terms of
  |                       'inductance/unit length'.  For example, if the total
  |                       inductance of a section is 3.0 nH and the length of
  |                       the section is 2 'units', the inductance would be
  |                       listed as L = 1.5 nH  (i.e. 3.0 / 2). 
  |               C       The capacitance to ground of a section, in terms of
  |                       capacitance per unit length.
  |               R       The series DC (ohmic) resistance of a section, in
  |                       terms of ohms per unit length.
Does this R mean literally DC(at 0MHz) resistance ? 

There are some EDA tools which can consider skin effect when computing 
trace resistance. Some vender suggests to consider skin effect.
Thank you.
- -Kazu Tsukada/Melco,Inc.
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------------------------------

Date: Thu, 16 May 2002 22:53:01 -0700
From: Scott McMorrow <[email-masked]>
Subject: Re: [IBIS-Users] EBD [Path Description] question

Kazu,

You are correct.  In an EBD, R is DC resistance.  AC skin effect 
resistance is not
specified in an EBD file.  For high frequencies, you must account for 
skin effect,
dielectric loss, along with changes in inductance and capacitance as a 
function of
frequency.  A modeling method other than EBD is required for high 
frequencies
and fast edge rates.

regards,

scott

- -- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com

Kazu Tsukada wrote:

>Hello
>
>I have a question about EBD Path Description.
>V3.2 spec says that :
>  |               The Len, L, R, and C subparameters specify the length, the
>  |               series inductance, resistance, and the capacitance to ground
>  |               of each section in a path description.
>  |
>  |               Len     The physical length of a section.  Lengths are given
>  |                       in terms of arbitrary 'units'.  Any non-zero length
>  |                       requires that the parameters that follow must be
>  |                       interpreted as distributed elements by the simulator.
>  |               L       The series inductance of a section, in terms of
>  |                       'inductance/unit length'.  For example, if the total
>  |                       inductance of a section is 3.0 nH and the length of
>  |                       the section is 2 'units', the inductance would be
>  |                       listed as L = 1.5 nH  (i.e. 3.0 / 2). 
>  |               C       The capacitance to ground of a section, in terms of
>  |                       capacitance per unit length.
>  |               R       The series DC (ohmic) resistance of a section, in
>  |                       terms of ohms per unit length.
>Does this R mean literally DC(at 0MHz) resistance ? 
>
>There are some EDA tools which can consider skin effect when computing 
>trace resistance. Some vender suggests to consider skin effect.
>Thank you.
>-Kazu Tsukada/Melco,Inc.
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>
>
>  
>

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------------------------------

Date: Fri, 17 May 2002 19:38:05 -0400
From: John Angulo <[email-masked]>
Subject: [IBIS-Users] FW: IBIS model question

I'm forwarding the following post as it was erroneously bounced from the
list.  Send private replies to whiz kid <[email-masked]>:

Hi Guys,
I have an IBIS model which has a built in Sub model.
The sub model is Non Driving. In the gnd clamp section
 after the main Gnd clamp curves its listed as [Sub
Model Type] Dynamic Clamp and then the dynamic gnd
clamp values. My question is gurus, when initially the
sub model is Non driving what is the Use of the
Dynamic Gnd clamp. I would really appreciate any
information as to what exactly this means.

Thanks,
Rahul.

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------------------------------

Date: Wed, 22 May 2002 11:35:07 -0700
From: "Ross, Bob" <[email-masked]>
Subject: Re: [IBIS-Users] FW: IBIS model question

Rahul:

A brief answer is that the Dynamic Clamp can still be used
for an input model for several reasons:

  1. The dynamic voltage shifting may model the behavior
     of an input buffer that has the clamp reference triggered
     by a voltage and that changes with time.

  2. Or in a static mode, the Input mode of an I/O buffer may
     contain the clamp, but it is switched out during the
     driving mode.

  3. The dynamic clamp in static mode can also be used for
     an internal (on die) terminator that is switched in only
     for the Input mode of an I/O buffer.

Bob Ross
Mentor Graphics

John Angulo wrote:
> 
> I'm forwarding the following post as it was erroneously bounced from the
> list.  Send private replies to whiz kid <[email-masked]>:
> 
> Hi Guys,
> I have an IBIS model which has a built in Sub model.
> The sub model is Non Driving. In the gnd clamp section
>  after the main Gnd clamp curves its listed as [Sub
> Model Type] Dynamic Clamp and then the dynamic gnd
> clamp values. My question is gurus, when initially the
> sub model is Non driving what is the Use of the
> Dynamic Gnd clamp. I would really appreciate any
> information as to what exactly this means.
> 
> Thanks,
> Rahul.
> 
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------------------------------

Date: Fri, 24 May 2002 08:36:30 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] Agenda, IBIS Open Forum Teleconference 5/31

		     IBIS Open Forum Meeting Agenda
			      for 5/31/02

		    Bridge Number    Reservation #   Passcode
                1-888-316-5901   N/A             3778497
                (International Dial-In: 1-617-801-9781)

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Stephen Peters and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Peters

     - Intros of New IBIS Participants, Meeting Quorum       Peters
     - Membership Update and Treasurers Report               Peters
     - Review of Previous Meeting's Minutes (and ARs)        Peters
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Leventhal, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters
     - JEDEC JC-16 Modeling and Testing                      Sessions
     - T10, Project 1414-DT - SCSI Signal Modeling           Barnes

     Design Automation Conference IBIS Summit Meeting        Ross

     Following IBIS Summit Meetings                          Ross

     IBIS Qualification Committee                            Katz

     IBIS Open Source Parser Proposal Discussion             Katz

     IBIS Model Review Committee                             Ross

     Majordomo Update                                        Angulo

     New Administrative Issues                               All

8:45 Technical Discussion

     IBIS Version 4.0 Discussion/BIRD75                      Peters

     IBIS Version 4.0 Review                                 Peters

     IBIS Connector and Futures Group Report                 Peters

     BIRD74 - EMI Parameters                                 de Burgh

     BIRD75.1 - Multi-Lingual IBIS Model Support             Ross

     ibischk3 Status                                         Ross

     - BUG68 - False Messages with Repeated Voltages         Mirmak

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Peters

9:55 Sign Off

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------------------------------

Date: Fri, 24 May 2002 13:34:52 -0700
From: "Dolese, John" <[email-masked]>
Subject: [IBIS-Users] IBIS Model for Coupled, Differential Pins

When I make an IBIS model of differential pins such as an LVDS output I want
to know how our customers will interpret the VI and VT data I give them. It
occurs to me that I should take the VI curves with a differential voltage
applied about the common mode voltage. This will give the odd mode impedance
of the pin pair. Does the signal integrity software keep track of both pins
so that if an odd mode reflection occurs both pins will be excited together?
In short if the odd mode impedance is 50 Ohms and the single ended impedance
is 100 Ohms, which do I report?

I have seen the single pin spice model template used in the ibis to spice
converter from Intusoft. Is there a template somewhere for differential
inputs and outputs?  Such a templated would clear up any ambiguity about how
the ibis data is interpreted. 

Another thing I'm wondering is about Resistance_Matrix. Are the resistors in
this matrix lumped between the lead inductance and the package pin
capacitance the same as r_pkg? It seems more reasonable that any conductance
between pins would occur on the die side of l_pkg. 
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------------------------------

Date: Tue, 28 May 2002 17:06:26 +0800
From: "LIM,KEE-CHAI (A-Singapore,ex1)" <[email-masked]>
Subject: [IBIS-Users] IBIS Package Model

Hi guys,

I have a question on IBIS package model:

If I have a file containing RLC which is extracted from a package using some extraction tools such as Ansoft, can I represent it in IBIS model?

When I look at the IBIS file, it always contain other sections on capturing timing information such as V/I curve for rising and falling waveforms. It only captures package modeling in one of the sections in IBIS modle file.

In my case, Can I create a IBIS model file only contains package information and no timing information?

Thank you very much.
 
Best Regards
kee chai
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------------------------------

Date: Tue, 28 May 2002 10:06:20 -0700
From: Abdulrahman Rafiq <[email-masked]>
Subject: Re: [IBIS-Users] IBIS Package Model

- --------------93A37C6F9CF424D75D8D3C28
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Kee Chai,

To create and IBIS model file you need all the relevent V/I and V/T data points, a valid pinlist file, master Pin file, RLC file. Also make sure that you have the timin-process loads (Vmeas, Vref, Rref and Cref) for all I/O,
Output, 3-state buffers.

In order to create the pin-list section of the ibis file, you will need to extract the [Pim], signal_name, model_name, R_pin, L_pin and C_pin from the master-pin, pin-list and RLC files.  This you can do using MS-Excel,
Star-Office or you if you are prficient in a scripting langauge you can create script to do this.

I hope this helps

Abdulrahman Rafiq
Hardware Engineer
Cisco Systems, Inc

"LIM,KEE-CHAI (A-Singapore,ex1)" wrote:

> Hi guys,
>
> I have a question on IBIS package model:
>
> If I have a file containing RLC which is extracted from a package using some extraction tools such as Ansoft, can I represent it in IBIS model?
>
> When I look at the IBIS file, it always contain other sections on capturing timing information such as V/I curve for rising and falling waveforms. It only captures package modeling in one of the sections in IBIS modle file.
>
> In my case, Can I create a IBIS model file only contains package information and no timing information?
>
> Thank you very much.
>
> Best Regards
> kee chai
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- --
- ---------------------------------------------------------------------------
      |           |             Abdulrahman A. Rafiq
     :|:         :|:            Hardware Engineer
    :|||:       :|||:           HSS Engineering Services, (ISBU)
 .:|||||||:...:|||||||:.        Direct: (408) 527-5540
 C i s c o S y s t e m s        Fax   : (408) 526-6603
      www.cisco.com             email : [email-masked]
      800-250-4800              epage : [email-masked]
                                URL1  : http://wwwin-sipd.cisco.com
                                URL2  : http://wwwin-people.cisco.com/~arafiq
- -----------------------------------------------------------------------------

- --------------93A37C6F9CF424D75D8D3C28
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Kee Chai,
<p>To create and IBIS&nbsp;model file you need all the relevent V/I and
V/T data points, a valid pinlist file, master Pin file, RLC&nbsp;file.
Also make sure that you have the timin-process loads (Vmeas, Vref, Rref
and Cref)&nbsp;for all I/O, Output, 3-state buffers.
<p>In order to create the pin-list section of the ibis file, you will need
to extract the [Pim], signal_name, model_name, R_pin, L_pin and C_pin from
the master-pin, pin-list and RLC&nbsp;files.&nbsp; This you can do using
MS-Excel, Star-Office or you if you are prficient in a scripting langauge
you can create script to do this.
<p>I&nbsp;hope this helps
<p>Abdulrahman Rafiq
<br>Hardware Engineer
<br>Cisco Systems, Inc
<p>"LIM,KEE-CHAI (A-Singapore,ex1)" wrote:
<blockquote TYPE=CITE>Hi guys,
<p>I have a question on IBIS package model:
<p>If I have a file containing RLC which is extracted from a package using
some extraction tools such as Ansoft, can I represent it in IBIS model?
<p>When I look at the IBIS file, it always contain other sections on capturing
timing information such as V/I curve for rising and falling waveforms.
It only captures package modeling in one of the sections in IBIS modle
file.
<p>In my case, Can I create a IBIS model file only contains package information
and no timing information?
<p>Thank you very much.
<p>Best Regards
<br>kee chai
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<pre>--&nbsp;
- ---------------------------------------------------------------------------
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Abdulrahman A. Rafiq&nbsp;&nbsp;
&nbsp;&nbsp;&nbsp;&nbsp; :|:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; :|:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Hardware Engineer
&nbsp;&nbsp;&nbsp; :|||:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; :|||:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HSS Engineering Services, (ISBU)
&nbsp;.:|||||||:...:|||||||:.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Direct: (408) 527-5540
&nbsp;C i s c o S y s t e m s&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Fax&nbsp;&nbsp; : (408) 526-6603
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&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; URL2&nbsp; : <A HREF="http://wwwin-people.cisco.com/~arafiq">http://wwwin-people.cisco.com/~arafiq</A>
- -----------------------------------------------------------------------------</pre>
&nbsp;</html>

- --------------93A37C6F9CF424D75D8D3C28--

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------------------------------

Date: Tue, 28 May 2002 10:57:57 -0700
From: "Muranyi, Arpad" <[email-masked]>
Subject: RE: [IBIS-Users] IBIS Package Model

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C20671.32FEB6A0
Content-Type: text/plain;
	charset="iso-8859-1"

While this is true, one ***CAN*** make a separate package IBIS model
in a standalone .pkg file, which does not require all the IV and Vt
curves, or any of the buffer related parameters.
 
Arpad Muranyi
Intel Corporation
======================================================================
- -----Original Message-----
From: Abdulrahman Rafiq [mailto:[email-masked]]
Sent: Tuesday, May 28, 2002 10:06 AM
To: LIM,KEE-CHAI (A-Singapore,ex1)
Cc: [email-masked]'
Subject: Re: [IBIS-Users] IBIS Package Model

Kee Chai, 

To create and IBIS model file you need all the relevent V/I and V/T data
points, a valid pinlist file, master Pin file, RLC file. Also make sure that
you have the timin-process loads (Vmeas, Vref, Rref and Cref) for all I/O,
Output, 3-state buffers. 

In order to create the pin-list section of the ibis file, you will need to
extract the [Pim], signal_name, model_name, R_pin, L_pin and C_pin from the
master-pin, pin-list and RLC files.  This you can do using MS-Excel,
Star-Office or you if you are prficient in a scripting langauge you can
create script to do this. 

I hope this helps 

Abdulrahman Rafiq 
Hardware Engineer 
Cisco Systems, Inc 

"LIM,KEE-CHAI (A-Singapore,ex1)" wrote: 

Hi guys, 

I have a question on IBIS package model: 

If I have a file containing RLC which is extracted from a package using some
extraction tools such as Ansoft, can I represent it in IBIS model? 

When I look at the IBIS file, it always contain other sections on capturing
timing information such as V/I curve for rising and falling waveforms. It
only captures package modeling in one of the sections in IBIS modle file. 

In my case, Can I create a IBIS model file only contains package information
and no timing information? 

Thank you very much. 

Best Regards 
kee chai 
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E-mail since 1993

- -- 

- ---------------------------------------------------------------------------

      |           |             Abdulrahman A. Rafiq  

     :|:         :|:            Hardware Engineer

    :|||:       :|||:           HSS Engineering Services, (ISBU)

 .:|||||||:...:|||||||:.        Direct: (408) 527-5540

 C i s c o S y s t e m s        Fax   : (408) 526-6603

      www.cisco.com             email : [email-masked]

      800-250-4800              epage : [email-masked]

                                URL1  :  http://wwwin-sipd.cisco.com
<http://wwwin-sipd.cisco.com> 

                                URL2  :
http://wwwin-people.cisco.com/~arafiq
<http://wwwin-people.cisco.com/~arafiq> 

- ----------------------------------------------------------------------------
- -

- ------_=_NextPart_001_01C20671.32FEB6A0
Content-Type: text/html;
	charset="iso-8859-1"

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">

<META content="MSHTML 5.50.4727.700" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT face="Courier New" size=2><SPAN class=726125817-28052002>While this 
is true, one ***CAN*** make a separate package IBIS model</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=726125817-28052002>in a 
standalone .pkg file, which does not require all the IV and 
Vt</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=726125817-28052002>curves, or 
any of the buffer related parameters.</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=726125817-28052002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=726125817-28052002>Arpad 
Muranyi</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN class=726125817-28052002>Intel 
Corporation</SPAN></FONT></DIV>
<DIV><FONT face="Courier New" size=2><SPAN 
class=726125817-28052002>======================================================================</SPAN></FONT></DIV>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma 
size=2>-----Original Message-----<BR><B>From:</B> Abdulrahman Rafiq 
[mailto:[email-masked]]<BR><B>Sent:</B> Tuesday, May 28, 2002 10:06 
AM<BR><B>To:</B> LIM,KEE-CHAI (A-Singapore,ex1)<BR><B>Cc:</B> 
[email-masked]'<BR><B>Subject:</B> Re: [IBIS-Users] IBIS Package 
Model<BR><BR></FONT></DIV>Kee Chai, 
<P>To create and IBIS&nbsp;model file you need all the relevent V/I and V/T data 
points, a valid pinlist file, master Pin file, RLC&nbsp;file. Also make sure 
that you have the timin-process loads (Vmeas, Vref, Rref and Cref)&nbsp;for all 
I/O, Output, 3-state buffers. 
<P>In order to create the pin-list section of the ibis file, you will need to 
extract the [Pim], signal_name, model_name, R_pin, L_pin and C_pin from the 
master-pin, pin-list and RLC&nbsp;files.&nbsp; This you can do using MS-Excel, 
Star-Office or you if you are prficient in a scripting langauge you can create 
script to do this. 
<P>I&nbsp;hope this helps 
<P>Abdulrahman Rafiq <BR>Hardware Engineer <BR>Cisco Systems, Inc 
<P>"LIM,KEE-CHAI (A-Singapore,ex1)" wrote: 
<BLOCKQUOTE TYPE="CITE">Hi guys, 
  <P>I have a question on IBIS package model: 
  <P>If I have a file containing RLC which is extracted from a package using 
  some extraction tools such as Ansoft, can I represent it in IBIS model? 
  <P>When I look at the IBIS file, it always contain other sections on capturing 
  timing information such as V/I curve for rising and falling waveforms. It only 
  captures package modeling in one of the sections in IBIS modle file. 
  <P>In my case, Can I create a IBIS model file only contains package 
  information and no timing information? 
  <P>Thank you very much. 
  <P>Best Regards <BR>kee chai 
  <BR>|------------------------------------------------------------------ 
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- ---------------------------------------------------------------------------
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Abdulrahman A. Rafiq&nbsp;&nbsp;
&nbsp;&nbsp;&nbsp;&nbsp; :|:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; :|:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Hardware Engineer
&nbsp;&nbsp;&nbsp; :|||:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; :|||:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HSS Engineering Services, (ISBU)
&nbsp;.:|||||||:...:|||||||:.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Direct: (408) 527-5540
&nbsp;C i s c o S y s t e m s&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Fax&nbsp;&nbsp; : (408) 526-6603
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; www.cisco.com&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; email : [email-masked]
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 800-250-4800&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; epage : [email-masked]
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&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; URL2&nbsp; : <A href="http://wwwin-people.cisco.com/~arafiq">http://wwwin-people.cisco.com/~arafiq</A>
- -----------------------------------------------------------------------------</PRE>&nbsp; 
</BODY></HTML>

- ------_=_NextPart_001_01C20671.32FEB6A0--
|------------------------------------------------------------------
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|with just the appropriate command message(s) in the body:
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------------------------------

Date: Tue, 28 May 2002 11:36:11 -0700
From: Abdulrahman Rafiq <[email-masked]>
Subject: Re: [IBIS-Users] IBIS Package Model

- --------------3E496746ADC704DCCC8B1E99
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Arpad,

Si there a document depicting the methodology to create this
standalone.pkg file ?

"Muranyi, Arpad" wrote:

> While this is true, one ***CAN*** make a separate package IBIS modelin
> a standalone .pkg file, which does not require all the IV and
> Vtcurves, or any of the buffer related parameters.Arpad MuranyiIntel
> Corporation======================================================================
> -----Original Message-----
> From: Abdulrahman Rafiq [mailto:[email-masked]]
> Sent: Tuesday, May 28, 2002 10:06 AM
> To: LIM,KEE-CHAI (A-Singapore,ex1)
> Cc: [email-masked]'
> Subject: Re: [IBIS-Users] IBIS Package Model
> Kee Chai,
>
> To create and IBIS model file you need all the relevent V/I and V/T
> data points, a valid pinlist file, master Pin file, RLC file. Also
> make sure that you have the timin-process loads (Vmeas, Vref, Rref and
> Cref) for all I/O, Output, 3-state buffers.
>
> In order to create the pin-list section of the ibis file, you will
> need to extract the [Pim], signal_name, model_name, R_pin, L_pin and
> C_pin from the master-pin, pin-list and RLC files.  This you can do
> using MS-Excel, Star-Office or you if you are prficient in a scripting
> langauge you can create script to do this.
>
> I hope this helps
>
> Abdulrahman Rafiq
> Hardware Engineer
> Cisco Systems, Inc
>
> "LIM,KEE-CHAI (A-Singapore,ex1)" wrote:
>
>> Hi guys,
>>
>> I have a question on IBIS package model:
>>
>> If I have a file containing RLC which is extracted from a package
>> using some extraction tools such as Ansoft, can I represent it in
>> IBIS model?
>>
>> When I look at the IBIS file, it always contain other sections on
>> capturing timing information such as V/I curve for rising and
>> falling waveforms. It only captures package modeling in one of the
>> sections in IBIS modle file.
>>
>> In my case, Can I create a IBIS model file only contains package
>> information and no timing information?
>>
>> Thank you very much.
>>
>> Best Regards
>> kee chai
>> |------------------------------------------------------------------
>> |For help or to subscribe/unsubscribe, email [email-masked]
>> |with just the appropriate command message(s) in the body:
>> |
>> |  help
>> |  subscribe   ibis       <optional e-mail address, if different>
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>> |
>> |or email a written request to [email-masked].
>> |
>> |IBIS reflector archives exist under:
>> |
>> |  http://www.eda.org/pub/ibis/email_archive/  Recent
>> |  http://www.eda.org/pub/ibis/users_archive/  Recent
>> |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
>
> --
> ---------------------------------------------------------------------------
>       |           |             Abdulrahman A. Rafiq
>      :|:         :|:            Hardware Engineer
>     :|||:       :|||:           HSS Engineering Services, (ISBU)
>  .:|||||||:...:|||||||:.        Direct: (408) 527-5540
>  C i s c o S y s t e m s        Fax   : (408) 526-6603
>       www.cisco.com             email : [email-masked]
>       800-250-4800              epage : [email-masked]
>                                 URL1  : http://wwwin-sipd.cisco.com
>                                 URL2  : http://wwwin-people.cisco.com/~arafiq
> -----------------------------------------------------------------------------
>
>

- --
- ---------------------------------------------------------------------------
      |           |             Abdulrahman A. Rafiq
     :|:         :|:            Hardware Engineer
    :|||:       :|||:           HSS Engineering Services, (ISBU)
 .:|||||||:...:|||||||:.        Direct: (408) 527-5540
 C i s c o S y s t e m s        Fax   : (408) 526-6603
      www.cisco.com             email : [email-masked]
      800-250-4800              epage : [email-masked]
                                URL1  : http://wwwin-sipd.cisco.com
                                URL2  : http://wwwin-people.cisco.com/~arafiq
- -----------------------------------------------------------------------------

- --------------3E496746ADC704DCCC8B1E99
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Arpad,
<p>Si there a document depicting the methodology to create this standalone.pkg
file ?
<br>&nbsp;
<br>&nbsp;
<p>"Muranyi, Arpad" wrote:
<blockquote TYPE=CITE><span class=726125817-28052002><font face="Courier New"><font size=-1>While
this is true, one ***CAN*** make a separate package IBIS model</span><span class=726125817-28052002>in
a standalone .pkg file, which does not require all the IV and Vt</span><span class=726125817-28052002>curves,
or any of the buffer related parameters.</span><span 
class=726125817-28052002></span><span class=726125817-28052002>Arpad
Muranyi</span><span class=726125817-28052002>Intel Corporation</span><span 
class=726125817-28052002>======================================================================</font></font></span>
<div class="OutlookMessageHeader" dir="ltr"><font face="Tahoma"><font size=-1>-----Original
Message-----</font></font>
<br><font face="Tahoma"><font size=-1><b>From:</b> Abdulrahman Rafiq [<A HREF="mailto:[email-masked]">mailto:[email-masked]</A>]</font></font>
<br><font face="Tahoma"><font size=-1><b>Sent:</b> Tuesday, May 28, 2002
10:06 AM</font></font>
<br><font face="Tahoma"><font size=-1><b>To:</b> LIM,KEE-CHAI (A-Singapore,ex1)</font></font>
<br><font face="Tahoma"><font size=-1><b>Cc:</b> [email-masked]'</font></font>
<br><font face="Tahoma"><font size=-1><b>Subject:</b> Re: [IBIS-Users]
IBIS Package Model</font></font></div>
Kee Chai,
<p>To create and IBIS model file you need all the relevent V/I and V/T
data points, a valid pinlist file, master Pin file, RLC file. Also make
sure that you have the timin-process loads (Vmeas, Vref, Rref and Cref)
for all I/O, Output, 3-state buffers.
<p>In order to create the pin-list section of the ibis file, you will need
to extract the [Pim], signal_name, model_name, R_pin, L_pin and C_pin from
the master-pin, pin-list and RLC files.&nbsp; This you can do using MS-Excel,
Star-Office or you if you are prficient in a scripting langauge you can
create script to do this.
<p>I hope this helps
<p>Abdulrahman Rafiq
<br>Hardware Engineer
<br>Cisco Systems, Inc
<p>"LIM,KEE-CHAI (A-Singapore,ex1)" wrote:
<blockquote TYPE="CITE">Hi guys,
<p>I have a question on IBIS package model:
<p>If I have a file containing RLC which is extracted from a package using
some extraction tools such as Ansoft, can I represent it in IBIS model?
<p>When I look at the IBIS file, it always contain other sections on capturing
timing information such as V/I curve for rising and falling waveforms.
It only captures package modeling in one of the sections in IBIS modle
file.
<p>In my case, Can I create a IBIS model file only contains package information
and no timing information?
<p>Thank you very much.
<p>Best Regards
<br>kee chai
<br>|------------------------------------------------------------------
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E-mail since 1993</blockquote>

<pre>--&nbsp;
- ---------------------------------------------------------------------------
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Abdulrahman A. Rafiq&nbsp;&nbsp;
&nbsp;&nbsp;&nbsp;&nbsp; :|:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; :|:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Hardware Engineer
&nbsp;&nbsp;&nbsp; :|||:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; :|||:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HSS Engineering Services, (ISBU)
&nbsp;.:|||||||:...:|||||||:.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Direct: (408) 527-5540
&nbsp;C i s c o S y s t e m s&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Fax&nbsp;&nbsp; : (408) 526-6603
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; www.cisco.com&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; email : [email-masked]
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 800-250-4800&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; epage : [email-masked]
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; URL1&nbsp; : <a href="http://wwwin-sipd.cisco.com">http://wwwin-sipd.cisco.com
</a>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; URL2&nbsp; : <a href="http://wwwin-people.cisco.com/~arafiq">http://wwwin-people.cisco.com/~arafiq
</a>-----------------------------------------------------------------------------</pre>
&nbsp;</blockquote>

<pre>--&nbsp;
- ---------------------------------------------------------------------------
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Abdulrahman A. Rafiq&nbsp;&nbsp;
&nbsp;&nbsp;&nbsp;&nbsp; :|:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; :|:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Hardware Engineer
&nbsp;&nbsp;&nbsp; :|||:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; :|||:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; HSS Engineering Services, (ISBU)
&nbsp;.:|||||||:...:|||||||:.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Direct: (408) 527-5540
&nbsp;C i s c o S y s t e m s&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Fax&nbsp;&nbsp; : (408) 526-6603
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; www.cisco.com&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; email : [email-masked]
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 800-250-4800&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; epage : [email-masked]
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; URL1&nbsp; : <A HREF="http://wwwin-sipd.cisco.com">http://wwwin-sipd.cisco.com</A>
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; URL2&nbsp; : <A HREF="http://wwwin-people.cisco.com/~arafiq">http://wwwin-people.cisco.com/~arafiq</A>
- -----------------------------------------------------------------------------</pre>
&nbsp;</html>

- --------------3E496746ADC704DCCC8B1E99--

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
|
|  help
|  subscribe   ibis       <optional e-mail address, if different>
|  subscribe   ibis-users <optional e-mail address, if different>
|  unsubscribe ibis       <optional e-mail address, if different>
|  unsubscribe ibis-users <optional e-mail address, if different>
|
|or email a written request to [email-masked].
|
|IBIS reflector archives exist under:
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|  http://www.eda.org/pub/ibis/email_archive/  Recent
|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Tue, 28 May 2002 11:56:18 -0700
From: Scott McMorrow <[email-masked]>
Subject: Re: [IBIS-Users] IBIS Package Model

Abdulrahman,

The format is described in the IBIS 3.2 specification.

regards,

scott

- -- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com

Abdulrahman Rafiq wrote:

> Arpad,
>
> Si there a document depicting the methodology to create this 
> standalone.pkg file ?
>  
>  
>
> "Muranyi, Arpad" wrote:
>
>> While this is true, one ***CAN*** make a separate package IBIS 
>> modelin a standalone .pkg file, which does not require all the IV and 
>> Vtcurves, or any of the buffer related parameters.Arpad MuranyiIntel 
>> Corporation====================================================================== 
>>
>> -----Original Message-----
>> *From:* Abdulrahman Rafiq [mailto:[email-masked]]
>> *Sent:* Tuesday, May 28, 2002 10:06 AM
>> *To:* LIM,KEE-CHAI (A-Singapore,ex1)
>> *Cc:* [email-masked]'
>> *Subject:* Re: [IBIS-Users] IBIS Package Model
>> Kee Chai,
>>
>> To create and IBIS model file you need all the relevent V/I and V/T 
>> data points, a valid pinlist file, master Pin file, RLC file. Also 
>> make sure that you have the timin-process loads (Vmeas, Vref, Rref 
>> and Cref) for all I/O, Output, 3-state buffers.
>>
>> In order to create the pin-list section of the ibis file, you will 
>> need to extract the [Pim], signal_name, model_name, R_pin, L_pin and 
>> C_pin from the master-pin, pin-list and RLC files.  This you can do 
>> using MS-Excel, Star-Office or you if you are prficient in a 
>> scripting langauge you can create script to do this.
>>
>> I hope this helps
>>
>> Abdulrahman Rafiq
>> Hardware Engineer
>> Cisco Systems, Inc
>>
>> "LIM,KEE-CHAI (A-Singapore,ex1)" wrote:
>>
>>> Hi guys,
>>>
>>> I have a question on IBIS package model:
>>>
>>> If I have a file containing RLC which is extracted from a package 
>>> using some extraction tools such as Ansoft, can I represent it in 
>>> IBIS model?
>>>
>>> When I look at the IBIS file, it always contain other sections on 
>>> capturing timing information such as V/I curve for rising and 
>>> falling waveforms. It only captures package modeling in one of the 
>>> sections in IBIS modle file.
>>>
>>> In my case, Can I create a IBIS model file only contains package 
>>> information and no timing information?
>>>
>>> Thank you very much.
>>>
>>> Best Regards
>>> kee chai
>>> |------------------------------------------------------------------
>>> |For help or to subscribe/unsubscribe, email [email-masked]
>>> |with just the appropriate command message(s) in the body:
>>> |
>>> |  help
>>> |  subscribe   ibis       <optional e-mail address, if different>
>>> |  subscribe   ibis-users <optional e-mail address, if different>
>>> |  unsubscribe ibis       <optional e-mail address, if different>
>>> |  unsubscribe ibis-users <optional e-mail address, if different>
>>> |
>>> |or email a written request to [email-masked].
>>> |
>>> |IBIS reflector archives exist under:
>>> |
>>> |  http://www.eda.org/pub/ibis/email_archive/  Recent
>>> |  http://www.eda.org/pub/ibis/users_archive/  Recent
>>> |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
>>>
>>-- 
>>---------------------------------------------------------------------------
>>      |           |             Abdulrahman A. Rafiq  
>>     :|:         :|:            Hardware Engineer
>>    :|||:       :|||:           HSS Engineering Services, (ISBU)
>> .:|||||||:...:|||||||:.        Direct: (408) 527-5540
>> C i s c o S y s t e m s        Fax   : (408) 526-6603
>>      www.cisco.com             email : [email-masked]
>>      800-250-4800              epage : [email-masked]
>>                                URL1  : http://wwwin-sipd.cisco.com
>> <http://wwwin-sipd.cisco.com>                                URL2  : http://wwwin-people.cisco.com/~arafiq
>> <http://wwwin-people.cisco.com/%7Earafiq>-----------------------------------------------------------------------------
>>
>>  
>
>-- 
>---------------------------------------------------------------------------
>      |           |             Abdulrahman A. Rafiq  
>     :|:         :|:            Hardware Engineer
>    :|||:       :|||:           HSS Engineering Services, (ISBU)
> .:|||||||:...:|||||||:.        Direct: (408) 527-5540
> C i s c o S y s t e m s        Fax   : (408) 526-6603
>      www.cisco.com             email : [email-masked]
>      800-250-4800              epage : [email-masked]
>                                URL1  : http://wwwin-sipd.cisco.com
>                                URL2  : http://wwwin-people.cisco.com/~arafiq <http://wwwin-people.cisco.com/%7Earafiq>
>-----------------------------------------------------------------------------
>
>  

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
|
|  help
|  subscribe   ibis       <optional e-mail address, if different>
|  subscribe   ibis-users <optional e-mail address, if different>
|  unsubscribe ibis       <optional e-mail address, if different>
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|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Tue, 28 May 2002 15:04:47 -0700
From: Lieby David <[email-masked]>
Subject: [IBIS-Users] s2ibis2

Hi,

I have been trying to get s2ibis2 to work.  The s2ibis2.solaris works a little but does not run to completion.  I think I found a place to patch but when I recompile and produce another executable I get a message "Bad System Call".  I went back and tried compiling the stuff that came in the original TAR and it did the same thing.  

If anyone has got the tool to work I would like a couple of pointers.

- -- 
dav0 
David Lieby
Acuson Corp.
(650)694-5030
|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
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|  unsubscribe ibis       <optional e-mail address, if different>
|  unsubscribe ibis-users <optional e-mail address, if different>
|
|or email a written request to [email-masked].
|
|IBIS reflector archives exist under:
|
|  http://www.eda.org/pub/ibis/email_archive/  Recent
|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Tue, 28 May 2002 16:41:03 -0700 (PDT)
From: Syed Huq <[email-masked]>
Subject: Re: [IBIS-Users] s2ibis2

We use s2ibis2.sun4.fix(the solaris compiled version)with no problems.

What is the error message with the pre-compiled downloadable executeable
on the web.

Syed
Cisco Systems, Inc

> From: Lieby David <[email-masked]>
> To: IBIS Users <[email-masked]>
> Date: Tue, 28 May 2002 15:04:47 -0700
> X-Accept-Language: en
> MIME-Version: 1.0
> Subject: [IBIS-Users] s2ibis2
> Content-Transfer-Encoding: 7bit
> 
> Hi,
> 
> I have been trying to get s2ibis2 to work.  The s2ibis2.solaris works a 
little but does not run to completion.  I think I found a place to patch 
but when I recompile and produce another executable I get a message "Bad 
System Call".  I went back and tried compiling the stuff that came in the 
original TAR and it did the same thing.  
> 
> If anyone has got the tool to work I would like a couple of pointers.
> 
> -- 
> dav0 
> David Lieby
> Acuson Corp.
> (650)694-5030
> |------------------------------------------------------------------
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------------------------------

Date: Wed, 29 May 2002 07:39:07 -0700
From: Lieby David <[email-masked]>
Subject: Re: [IBIS-Users] s2ibis2

I got some time with an engineer working in the same environment and found out that they had never been able to get the strip command to work well.  We commented it out and the resulting executable did fine.  Sorry about the bandwidth consumption.

Thanks,
dav0
Acuson, Inc.

Syed Huq wrote:
> 
> We use s2ibis2.sun4.fix(the solaris compiled version)with no problems.
> 
> What is the error message with the pre-compiled downloadable executeable
> on the web.
> 
> Syed
> Cisco Systems, Inc
> 
> > From: Lieby David <[email-masked]>
> > To: IBIS Users <[email-masked]>
> > Date: Tue, 28 May 2002 15:04:47 -0700
> > X-Accept-Language: en
> > MIME-Version: 1.0
> > Subject: [IBIS-Users] s2ibis2
> > Content-Transfer-Encoding: 7bit
> >
> > Hi,
> >
> > I have been trying to get s2ibis2 to work.  The s2ibis2.solaris works a
> little but does not run to completion.  I think I found a place to patch
> but when I recompile and produce another executable I get a message "Bad
> System Call".  I went back and tried compiling the stuff that came in the
> original TAR and it did the same thing.
> >
> > If anyone has got the tool to work I would like a couple of pointers.
> >
> > --
> > dav0
> > David Lieby
> > Acuson Corp.
> > (650)694-5030
> > |------------------------------------------------------------------
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------------------------------

Date: Tue, 4 Jun 2002 20:41:57 -0400 
From: John Angulo <[email-masked]>
Subject: [IBIS-Users] FW:  ibis modeling question

The following is posted on behalf of Ping-Chung Li of TSMC.  Please send
private replies to [email-masked].

- ------------------
Dear IBIS experts,

I have three questions regarding IBIS modeling.
1. I have an I/O cell, where at the output pin I have connected a resistor
to a
reference voltage source. The purpose of this
resistor and voltage source is to model the surrounding environment of the
I/O
cell. How should I generate IBIS model for
this cell? Since the output node is connected to a voltage source via a
resistor, there is an current thru the resistor when I sweep
the output pin. Should I take out the resistor and voltage source when
generating Clamp V-I table?

2. How do I generate pull-up and pull-down tables for 3-state cells? my
understanding is that I generate power/ground clamp first,
with enable pin turned-off so that the output pin is high impedance. Then I
activate enable pin and sweep output pin, then subtract
both power/ground clamp tables from the pull-up/pull-down tables to get
pull-up
and pull-down V-I curves. Is this correct?

3. How does ibischk3 check the accuracy of my cell's rising and falling
waveform? My understanding is that it would take the sum
of pull-up and power/ground clamp tables (or pull-down and power/ground
clamp
tables) and compare them with the end points of
rising/falling
waveforms. Is this correct? With my cell, it seems ibischk3 does not work
this
way. Is there anything I missed?

your help on these questions is highly appropriated.

Ping-Chung Li
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------------------------------

Date: Wed, 05 Jun 2002 17:15:06 -0700
From: Monika Garg <[email-masked]>
Subject: [IBIS-Users] Info on IBIS for LVDS

Hi,

I need to generate IBIS Model for a chip that has 4 different types of 
IOs. As i understand i need to provide 4 IBIS Models for each different 
type of IO. These IOs are of LVDS type. Is there any information on what 
cautions i need to take while developing IBIS for LVDS?

Thanks in advance for all the help.
Monika

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------------------------------

Date: Thu, 6 Jun 2002 10:52:32 +0300 
From: "Hegazy, Hazem" <[email-masked]>
Subject: RE: [IBIS-Users] Info on IBIS for LVDS

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C20D2F.1D343D7D
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Hi,

This is one of my presentations in IBIS summits January 2001 describes
various modeling technique of LVDS buffers.
If you have any questions, fell free to email my with.

http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip

BR,

- -----Original Message-----
From: Monika Garg [mailto:[email-masked]]
Sent: Thursday, June 06, 2002 3:15 AM
To: [email-masked]
Subject: [IBIS-Users] Info on IBIS for LVDS

Hi,

I need to generate IBIS Model for a chip that has 4 different types of 
IOs. As i understand i need to provide 4 IBIS Models for each different 
type of IO. These IOs are of LVDS type. Is there any information on what 
cautions i need to take while developing IBIS for LVDS?

Thanks in advance for all the help.
Monika

|------------------------------------------------------------------
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5.5.2655.35">
<TITLE>RE: [IBIS-Users] Info on IBIS for LVDS</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>Hi,</FONT>
</P>

<P><FONT SIZE=3D2>This is one of my presentations in IBIS summits =
January 2001 describes various modeling technique of LVDS =
buffers.</FONT>
<BR><FONT SIZE=3D2>If you have any questions, fell free to email my =
with.</FONT>
</P>

<P><FONT SIZE=3D2><A =
HREF=3D"http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip" =
TARGET=3D"_blank">http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip</=
A></FONT>
</P>

<P><FONT SIZE=3D2>BR,</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Monika Garg [<A =
HREF=3D"mailto:[email-masked]">mailto:[email-masked]</A>]</FONT>
<BR><FONT SIZE=3D2>Sent: Thursday, June 06, 2002 3:15 AM</FONT>
<BR><FONT SIZE=3D2>To: [email-masked]</FONT>
<BR><FONT SIZE=3D2>Subject: [IBIS-Users] Info on IBIS for LVDS</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Hi,</FONT>
</P>

<P><FONT SIZE=3D2>I need to generate IBIS Model for a chip that has 4 =
different types of </FONT>
<BR><FONT SIZE=3D2>IOs. As i understand i need to provide 4 IBIS Models =
for each different </FONT>
<BR><FONT SIZE=3D2>type of IO. These IOs are of LVDS type. Is there any =
information on what </FONT>
<BR><FONT SIZE=3D2>cautions i need to take while developing IBIS for =
LVDS?</FONT>
</P>

<P><FONT SIZE=3D2>Thanks in advance for all the help.</FONT>
<BR><FONT SIZE=3D2>Monika</FONT>
</P>
<BR>

<P><FONT =
SIZE=3D2>|--------------------------------------------------------------=
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------------------------------

Date: Thu, 6 Jun 2002 06:48:18 -0400
From: "Barry Katz" <[email-masked]>
Subject: Re: [IBIS-Users] Info on IBIS for LVDS

This is a multi-part message in MIME format.

- ------=_NextPart_000_0162_01C20D26.246348C0
Content-Type: text/plain;
	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

RE: [IBIS-Users] Info on IBIS for LVDSHi Monika,

In addition to Hazem's presentation there was a paper given at this =
year's DesignCon by Adam Tambone (Fairchild).  Also, Doug Burns (SiSoft) =
will be giving a presentation on our experience with IBIS LVDS Modeling =
at the Design Automation Conference IBIS Summit next Thursday.  This =
presentation should be uploaded to the IBIS website shortly after the =
Summit.  You will be able to get Doug's presentation directly from me as =
well.

Barry

Barry Katz
President & CTO
Signal Integrity Software, Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
978 461 0449 x19
www.sisoft.com
  ----- Original Message -----=20
  From: Hegazy, Hazem=20
  To: 'Monika Garg' ; [email-masked]=20
  Sent: Thursday, June 06, 2002 3:52 AM
  Subject: RE: [IBIS-Users] Info on IBIS for LVDS

  Hi,=20

  This is one of my presentations in IBIS summits January 2001 describes =
various modeling technique of LVDS buffers.=20
  If you have any questions, fell free to email my with.=20

  http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip=20

  BR,=20

  -----Original Message-----=20
  From: Monika Garg [mailto:[email-masked]]=20
  Sent: Thursday, June 06, 2002 3:15 AM=20
  To: [email-masked]=20
  Subject: [IBIS-Users] Info on IBIS for LVDS=20

  Hi,=20

  I need to generate IBIS Model for a chip that has 4 different types of =

  IOs. As i understand i need to provide 4 IBIS Models for each =
different=20
  type of IO. These IOs are of LVDS type. Is there any information on =
what=20
  cautions i need to take while developing IBIS for LVDS?=20

  Thanks in advance for all the help.=20
  Monika=20

  |------------------------------------------------------------------=20
  |For help or to subscribe/unsubscribe, email [email-masked]=20
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  |=20
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>RE: [IBIS-Users] Info on IBIS for LVDS</TITLE>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
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</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>Hi Monika,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>In addition to Hazem's presentation there was a =
paper given at=20
this year's DesignCon by Adam Tambone (Fairchild).&nbsp; Also, Doug =
Burns=20
(SiSoft) will be giving a presentation on&nbsp;our experience with IBIS =
LVDS=20
Modeling at the Design Automation Conference IBIS Summit next =
Thursday.&nbsp;=20
This presentation should be uploaded to the IBIS website shortly after =
the=20
Summit.&nbsp; You will be able to get Doug's presentation directly =
from&nbsp;me=20
as well.</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>Barry</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV>Barry Katz<BR>President &amp; CTO<BR>Signal Integrity Software, =
Inc.<BR>6=20
Clock Tower Place, Suite 250<BR>Maynard, MA 01754<BR>978 461 0449 =
x19<BR><A=20
href=3D"http://www.sisoft.com">www.sisoft.com</A></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A href=3D"mailto:[email-masked]"=20
  title=[email-masked]>Hegazy, Hazem</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[email-masked]"=20
  title=[email-masked]>'Monika Garg'</A> ; <A =
href=3D"mailto:[email-masked]"=20
  title=[email-masked]>[email-masked]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, June 06, 2002 =
3:52=20
  AM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> RE: [IBIS-Users] Info =
on IBIS=20
  for LVDS</DIV>
  <DIV><BR></DIV>
  <P><FONT size=3D2>Hi,</FONT> </P>
  <P><FONT size=3D2>This is one of my presentations in IBIS summits =
January 2001=20
  describes various modeling technique of LVDS buffers.</FONT> <BR><FONT =

  size=3D2>If you have any questions, fell free to email my with.</FONT> =
</P>
  <P><FONT size=3D2><A =
href=3D"http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip"=20
  =
target=3D_blank>http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip</A><=
/FONT>=20
  </P>
  <P><FONT size=3D2>BR,</FONT> </P><BR>
  <P><FONT size=3D2>-----Original Message-----</FONT> <BR><FONT =
size=3D2>From:=20
  Monika Garg [<A=20
  href=3D"mailto:[email-masked]">mailto:[email-masked]</A>]</FONT> =
<BR><FONT=20
  size=3D2>Sent: Thursday, June 06, 2002 3:15 AM</FONT> <BR><FONT =
size=3D2>To: <A=20
  =
href=3D"mailto:[email-masked]">[email-masked]</A></=
FONT>=20
  <BR><FONT size=3D2>Subject: [IBIS-Users] Info on IBIS for LVDS</FONT> =
</P><BR>
  <P><FONT size=3D2>Hi,</FONT> </P>
  <P><FONT size=3D2>I need to generate IBIS Model for a chip that has 4 =
different=20
  types of </FONT><BR><FONT size=3D2>IOs. As i understand i need to =
provide 4 IBIS=20
  Models for each different </FONT><BR><FONT size=3D2>type of IO. These =
IOs are of=20
  LVDS type. Is there any information on what </FONT><BR><FONT =
size=3D2>cautions i=20
  need to take while developing IBIS for LVDS?</FONT> </P>
  <P><FONT size=3D2>Thanks in advance for all the help.</FONT> <BR><FONT =

  size=3D2>Monika</FONT> </P><BR>
  <P><FONT=20
  =
size=3D2>|---------------------------------------------------------------=
- ---</FONT>=20
  <BR><FONT size=3D2>|For help or to subscribe/unsubscribe, email=20
  [email-masked]</FONT> <BR><FONT size=3D2>|with just the appropriate =
command=20
  message(s) in the body:</FONT> <BR><FONT size=3D2>|</FONT> <BR><FONT=20
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subscribe&nbsp;&nbsp;=20
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------------------------------

Date: Thu, 6 Jun 2002 12:02:18 -0700 
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] Agenda, DAC2002 IBIS Summit

(Note: If you are planning on attending and haven't signed-up, please do so
by Monday June 10.  See the contact information for Guy de Burg below.)

                                 A G E N D A 
                D A C   I B I S   S U M M I T   M E E T I N G

                          Monday, June 13, 2002
                  Hilton Hotel, New Orleans Riverside
                          Grand Salon 7 and 10
                         New Orleans, Louisiana

8:00 AM      REFRESHMENTS (CONTINENTAL BREAKFAST)

8:30 AM      INTRODUCTIONS AND GENERAL BUSINESS
             - Introductions
             - Announcements
             - Opens & Other Business

8:45 AM      IBIS Annual Report
             - Stephen Peters, Intel Corp.

9:00 AM      IBIS Quality Checklist
             - Barry Katz, Signal Integrity Software (SiSoft)

9:30 AM      LVDS Modeling
             - Doug Burns, Signal Integrity Software (SiSoft)

10:00 AM     BREAK

10:15 AM     Election of Officers 2002-2003

10:30 AM     IBIS Models Today, Their Parameters and Their Accuracy
             - Eckhard Lenski, Siemens AG

11:00 AM     Pad Capacitance Extraction Spice Simulations
             Hazem Hegazy, Mentor Graphics
             (Presented by Bob Ross, Mentor Graphics)

11:30 AM      Buffer Impedance and IBIS Quality
             - Luca Giacotto, Altron Transport
 
12:00 PM     LUNCH (PROVIDED)

1:00 PM      Connector Modeling Experiences
             - Atsuji Ito, Matsushita Electric Industrial Co. (Panasonic)

1:30 PM      IBIS Connector Specification
             - Stephen Peters, Intel Corp.

2:00 PM      Multi-Lingual Modeling Applications and Issues
             - Bob Ross, Mentor Graphics

2:30 PM      BREAK AND REFRESHMENTS

2:45 PM      IBIS Version 4.0 Discussion
             - Stephen Peters, Intel Corp.

3:15 PM      IBIS Open Parser Discussion 
             
3:45 PM      Other Ad Hoc Discussion/Presentations

4:45 PM      Any Other Issues
             - Next Meeting

5:00 PM      END OF MEETING

____________________________________________________________________________
_

DAC 2002:  DAC is scheduled Monday - Friday, June 10 - 14, 2002. 
           The exhibitor portion is open from Monday - Wednesday. 

DAC URL:   http://www.dac.com/ 

PRESENTATIONS: 

           We are providing an LCD Projector and an Overhead Projector. 
           HOWEVER, Bring foils for backup, if needed, or as primary
           method of presentation. 

           Please provide 25 copies to handout at the meeting.
           Also send electronic copy for archiving to address below.

           Ad Hoc presentations and discussion issues are welcome and
           will be scheduled, time permitting.

CONTACT:   Guy de Burgh 
           IBIS Secretary 
           [email-masked] 
           (805) 988-8250 ext. 6823

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------------------------------

Date: Thu, 6 Jun 2002 13:54:52 -0700 
From: "Mohan, Prabhu" <[email-masked]>
Subject: RE: [IBIS-Users] Info on IBIS for LVDS

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

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Hi
 
Can you send a pointer to Adam Tambone's presentation. I can't seem to find
it.
 
Its not here http://www.eda.org/pub/ibis/summits/jan02/
<http://www.eda.org/pub/ibis/summits/jan02/> ?
 
Thanks
Prabhu/~

- -----Original Message-----
From: Barry Katz [mailto:[email-masked]]
Sent: Thursday, June 06, 2002 3:48 AM
To: Hegazy, Hazem; 'Monika Garg'; [email-masked]
Subject: Re: [IBIS-Users] Info on IBIS for LVDS

Hi Monika,
 
In addition to Hazem's presentation there was a paper given at this year's
DesignCon by Adam Tambone (Fairchild).  Also, Doug Burns (SiSoft) will be
giving a presentation on our experience with IBIS LVDS Modeling at the
Design Automation Conference IBIS Summit next Thursday.  This presentation
should be uploaded to the IBIS website shortly after the Summit.  You will
be able to get Doug's presentation directly from me as well.
 
Barry

Barry Katz
President & CTO
Signal Integrity Software, Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
978 461 0449 x19
www.sisoft.com <http://www.sisoft.com> 

- ----- Original Message ----- 
From: Hegazy, Hazem <mailto:[email-masked]>  
To: 'Monika Garg' <mailto:[email-masked]>  ; [email-masked]
<mailto:[email-masked]>  
Sent: Thursday, June 06, 2002 3:52 AM
Subject: RE: [IBIS-Users] Info on IBIS for LVDS

Hi, 

This is one of my presentations in IBIS summits January 2001 describes
various modeling technique of LVDS buffers. 
If you have any questions, fell free to email my with. 

http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip
<http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip>  

BR, 

- -----Original Message----- 
From: Monika Garg [ mailto:[email-masked] <mailto:[email-masked]> ] 
Sent: Thursday, June 06, 2002 3:15 AM 
To: [email-masked] <mailto:[email-masked]>  
Subject: [IBIS-Users] Info on IBIS for LVDS 

Hi, 

I need to generate IBIS Model for a chip that has 4 different types of 
IOs. As i understand i need to provide 4 IBIS Models for each different 
type of IO. These IOs are of LVDS type. Is there any information on what 
cautions i need to take while developing IBIS for LVDS? 

Thanks in advance for all the help. 
Monika 

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<TITLE>RE: [IBIS-Users] Info on IBIS for LVDS</TITLE>

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<DIV><FONT color=#0000ff face="Courier New" size=2><SPAN 
class=376395620-06062002>Hi</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face="Courier New" size=2><SPAN 
class=376395620-06062002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face="Courier New" size=2><SPAN 
class=376395620-06062002>Can you send a pointer to Adam Tambone's presentation. 
I can't seem to find it.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face="Courier New" size=2><SPAN 
class=376395620-06062002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face="Courier New" size=2><SPAN 
class=376395620-06062002>Its not here <A 
href="http://www.eda.org/pub/ibis/summits/jan02/">http://www.eda.org/pub/ibis/summits/jan02/</A>?</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face="Courier New" size=2><SPAN 
class=376395620-06062002></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face="Courier New" size=2><SPAN 
class=376395620-06062002>Thanks</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face="Courier New" size=2><SPAN 
class=376395620-06062002>Prabhu/~</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face="Courier New" size=2><SPAN 
class=376395620-06062002></SPAN></FONT>&nbsp;</DIV>
<BLOCKQUOTE style="MARGIN-RIGHT: 0px">
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma 
  size=2>-----Original Message-----<BR><B>From:</B> Barry Katz 
  [mailto:[email-masked]]<BR><B>Sent:</B> Thursday, June 06, 2002 3:48 
  AM<BR><B>To:</B> Hegazy, Hazem; 'Monika Garg'; 
  [email-masked]<BR><B>Subject:</B> Re: [IBIS-Users] Info on IBIS for 
  LVDS<BR><BR></DIV></FONT>
  <DIV><FONT size=2>Hi Monika,</FONT></DIV>
  <DIV>&nbsp;</DIV>
  <DIV><FONT size=2>In addition to Hazem's presentation there was a paper given 
  at this year's DesignCon by Adam Tambone (Fairchild).&nbsp; Also, Doug Burns 
  (SiSoft) will be giving a presentation on&nbsp;our experience with IBIS LVDS 
  Modeling at the Design Automation Conference IBIS Summit next Thursday.&nbsp; 
  This presentation should be uploaded to the IBIS website shortly after the 
  Summit.&nbsp; You will be able to get Doug's presentation directly 
  from&nbsp;me as well.</FONT></DIV>
  <DIV>&nbsp;</DIV>
  <DIV><FONT size=2>Barry</FONT></DIV>
  <DIV>&nbsp;</DIV>
  <DIV>&nbsp;</DIV>
  <DIV>Barry Katz<BR>President &amp; CTO<BR>Signal Integrity Software, Inc.<BR>6 
  Clock Tower Place, Suite 250<BR>Maynard, MA 01754<BR>978 461 0449 x19<BR><A 
  href="http://www.sisoft.com">www.sisoft.com</A></DIV>
  <BLOCKQUOTE 
  style="BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
    <DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
    <DIV 
    style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B> 
    <A href="mailto:[email-masked]" 
    title=[email-masked]>Hegazy, Hazem</A> </DIV>
    <DIV style="FONT: 10pt arial"><B>To:</B> <A href="mailto:[email-masked]" 
    title=[email-masked]>'Monika Garg'</A> ; <A 
    href="mailto:[email-masked]" 
    title=[email-masked]>[email-masked]</A> </DIV>
    <DIV style="FONT: 10pt arial"><B>Sent:</B> Thursday, June 06, 2002 3:52 
    AM</DIV>
    <DIV style="FONT: 10pt arial"><B>Subject:</B> RE: [IBIS-Users] Info on IBIS 
    for LVDS</DIV>
    <DIV><BR></DIV>
    <P><FONT size=2>Hi,</FONT> </P>
    <P><FONT size=2>This is one of my presentations in IBIS summits January 2001 
    describes various modeling technique of LVDS buffers.</FONT> <BR><FONT 
    size=2>If you have any questions, fell free to email my with.</FONT> </P>
    <P><FONT size=2><A 
    href="http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip" 
    target=_blank>http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip</A></FONT> 
    </P>
    <P><FONT size=2>BR,</FONT> </P><BR>
    <P><FONT size=2>-----Original Message-----</FONT> <BR><FONT size=2>From: 
    Monika Garg [<A 
    href="mailto:[email-masked]">mailto:[email-masked]</A>]</FONT> <BR><FONT 
    size=2>Sent: Thursday, June 06, 2002 3:15 AM</FONT> <BR><FONT size=2>To: <A 
    href="mailto:[email-masked]">[email-masked]</A></FONT> 
    <BR><FONT size=2>Subject: [IBIS-Users] Info on IBIS for LVDS</FONT> </P><BR>
    <P><FONT size=2>Hi,</FONT> </P>
    <P><FONT size=2>I need to generate IBIS Model for a chip that has 4 
    different types of </FONT><BR><FONT size=2>IOs. As i understand i need to 
    provide 4 IBIS Models for each different </FONT><BR><FONT size=2>type of IO. 
    These IOs are of LVDS type. Is there any information on what 
    </FONT><BR><FONT size=2>cautions i need to take while developing IBIS for 
    LVDS?</FONT> </P>
    <P><FONT size=2>Thanks in advance for all the help.</FONT> <BR><FONT 
    size=2>Monika</FONT> </P><BR>
    <P><FONT 
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------------------------------

Date: Thu, 6 Jun 2002 16:28:13 -0700 
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] CORRECTION: Agenda, DAC2002 IBIS Summit

The correct day is Thursday, June 13, 2002
=====================

                                 A G E N D A 
                D A C   I B I S   S U M M I T   M E E T I N G

                         Thursday, June 13, 2002
                  Hilton Hotel, New Orleans Riverside
                          Grand Salon 7 and 10
                         New Orleans, Louisiana

8:00 AM      REFRESHMENTS (CONTINENTAL BREAKFAST)

8:30 AM      INTRODUCTIONS AND GENERAL BUSINESS
             - Introductions
             - Announcements
             - Opens & Other Business

8:45 AM      IBIS Annual Report
             - Stephen Peters, Intel Corp.

9:00 AM      IBIS Quality Checklist
             - Barry Katz, Signal Integrity Software (SiSoft)

9:30 AM      LVDS Modeling
             - Doug Burns, Signal Integrity Software (SiSoft)

10:00 AM     BREAK

10:15 AM     Election of Officers 2002-2003

10:30 AM     IBIS Models Today, Their Parameters and Their Accuracy
             - Eckhard Lenski, Siemens AG

11:00 AM     Pad Capacitance Extraction Spice Simulations
             Hazem Hegazy, Mentor Graphics
             (Presented by Bob Ross, Mentor Graphics)

11:30 AM      Buffer Impedance and IBIS Quality
             - Luca Giacotto, Altron Transport
 
12:00 PM     LUNCH (PROVIDED)

1:00 PM      Connector Modeling Experiences
             - Atsuji Ito, Matsushita Electric Industrial Co. (Panasonic)

1:30 PM      IBIS Connector Specification
             - Stephen Peters, Intel Corp.

2:00 PM      Multi-Lingual Modeling Applications and Issues
             - Bob Ross, Mentor Graphics

2:30 PM      BREAK AND REFRESHMENTS

2:45 PM      IBIS Version 4.0 Discussion
             - Stephen Peters, Intel Corp.

3:15 PM      IBIS Open Parser Discussion 
             
3:45 PM      Other Ad Hoc Discussion/Presentations

4:45 PM      Any Other Issues
             - Next Meeting

5:00 PM      END OF MEETING

____________________________________________________________________________
_

DAC 2002:  DAC is scheduled Monday - Friday, June 10 - 14, 2002. 
           The exhibitor portion is open from Monday - Wednesday. 

DAC URL:   http://www.dac.com/ 

PRESENTATIONS: 

           We are providing an LCD Projector and an Overhead Projector. 
           HOWEVER, Bring foils for backup, if needed, or as primary
           method of presentation. 

           Please provide 25 copies to handout at the meeting.
           Also send electronic copy for archiving to address below.

           Ad Hoc presentations and discussion issues are welcome and
           will be scheduled, time permitting.

CONTACT:   Guy de Burgh 
           IBIS Secretary 
           [email-masked] 
           (805) 988-8250 ext. 6823

|------------------------------------------------------------------
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------------------------------

Date: Fri, 7 Jun 2002 06:43:53 -0400
From: "Barry Katz" <[email-masked]>
Subject: Re: [IBIS-Users] Info on IBIS for LVDS

This is a multi-part message in MIME format.

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	charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable

RE: [IBIS-Users] Info on IBIS for LVDSHi,

Adam gave his presentation in a session at DesignCon (not at the IBIS =
summit).  I know the papers are in the proceedings.  I will ask, Adam =
how presentation can be made available on the web.

Barry

- ----- Original Message -----=20
  From: Mohan, Prabhu=20
  To: [email-masked]=20
  Sent: Thursday, June 06, 2002 4:54 PM
  Subject: RE: [IBIS-Users] Info on IBIS for LVDS

  Hi
  =20
  Can you send a pointer to Adam Tambone's presentation. I can't seem to =
find it.
  =20
  Its not here http://www.eda.org/pub/ibis/summits/jan02/?
  =20
  Thanks
  Prabhu/~
  =20
    -----Original Message-----
    From: Barry Katz [mailto:[email-masked]]
    Sent: Thursday, June 06, 2002 3:48 AM
    To: Hegazy, Hazem; 'Monika Garg'; [email-masked]
    Subject: Re: [IBIS-Users] Info on IBIS for LVDS

    Hi Monika,

    In addition to Hazem's presentation there was a paper given at this =
year's DesignCon by Adam Tambone (Fairchild).  Also, Doug Burns (SiSoft) =
will be giving a presentation on our experience with IBIS LVDS Modeling =
at the Design Automation Conference IBIS Summit next Thursday.  This =
presentation should be uploaded to the IBIS website shortly after the =
Summit.  You will be able to get Doug's presentation directly from me as =
well.

    Barry

    Barry Katz
    President & CTO
    Signal Integrity Software, Inc.
    6 Clock Tower Place, Suite 250
    Maynard, MA 01754
    978 461 0449 x19
    www.sisoft.com
      ----- Original Message -----=20
      From: Hegazy, Hazem=20
      To: 'Monika Garg' ; [email-masked]=20
      Sent: Thursday, June 06, 2002 3:52 AM
      Subject: RE: [IBIS-Users] Info on IBIS for LVDS

      Hi,=20

      This is one of my presentations in IBIS summits January 2001 =
describes various modeling technique of LVDS buffers.=20
      If you have any questions, fell free to email my with.=20

      http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip=20

      BR,=20

      -----Original Message-----=20
      From: Monika Garg [mailto:[email-masked]]=20
      Sent: Thursday, June 06, 2002 3:15 AM=20
      To: [email-masked]=20
      Subject: [IBIS-Users] Info on IBIS for LVDS=20

      Hi,=20

      I need to generate IBIS Model for a chip that has 4 different =
types of=20
      IOs. As i understand i need to provide 4 IBIS Models for each =
different=20
      type of IO. These IOs are of LVDS type. Is there any information =
on what=20
      cautions i need to take while developing IBIS for LVDS?=20

      Thanks in advance for all the help.=20
      Monika=20

      =
|------------------------------------------------------------------=20
      |For help or to subscribe/unsubscribe, email [email-masked]=20
      |with just the appropriate command message(s) in the body:=20
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      |  subscribe   ibis-users <optional e-mail address, if different>=20
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      |=20
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      |=20
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<DIV><FONT size=3D2>Hi,</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV><FONT size=3D2>Adam gave his presentation in a session at DesignCon =
(not at=20
the IBIS summit).&nbsp; I know the papers are&nbsp;in the =
proceedings.&nbsp; I=20
will ask, Adam&nbsp;how presentation can be made available on the=20
web.</FONT></DIV>
<DIV><FONT size=3D2></FONT>&nbsp;</DIV>
<DIV><FONT size=3D2>Barry</FONT></DIV>
<DIV>&nbsp;</DIV>
<DIV>&nbsp;</DIV>
<DIV>----- Original Message ----- </DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
  <DIV=20
  style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
  <A href=3D"mailto:[email-masked]" =
title=[email-masked]>Mohan,=20
  Prabhu</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[email-masked]"=20
  title=[email-masked]>[email-masked]</A> </DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, June 06, 2002 =
4:54=20
  PM</DIV>
  <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> RE: [IBIS-Users] Info =
on IBIS=20
  for LVDS</DIV>
  <DIV><BR></DIV>
  <DIV><FONT color=3D#0000ff face=3D"Courier New" size=3D2><SPAN=20
  class=3D376395620-06062002>Hi</SPAN></FONT></DIV>
  <DIV><FONT color=3D#0000ff face=3D"Courier New" size=3D2><SPAN=20
  class=3D376395620-06062002></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT color=3D#0000ff face=3D"Courier New" size=3D2><SPAN=20
  class=3D376395620-06062002>Can you send a pointer to Adam Tambone's=20
  presentation. I can't seem to find it.</SPAN></FONT></DIV>
  <DIV><FONT color=3D#0000ff face=3D"Courier New" size=3D2><SPAN=20
  class=3D376395620-06062002></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT color=3D#0000ff face=3D"Courier New" size=3D2><SPAN=20
  class=3D376395620-06062002>Its not here <A=20
  =
href=3D"http://www.eda.org/pub/ibis/summits/jan02/">http://www.eda.org/pu=
b/ibis/summits/jan02/</A>?</SPAN></FONT></DIV>
  <DIV><FONT color=3D#0000ff face=3D"Courier New" size=3D2><SPAN=20
  class=3D376395620-06062002></SPAN></FONT>&nbsp;</DIV>
  <DIV><FONT color=3D#0000ff face=3D"Courier New" size=3D2><SPAN=20
  class=3D376395620-06062002>Thanks</SPAN></FONT></DIV>
  <DIV><FONT color=3D#0000ff face=3D"Courier New" size=3D2><SPAN=20
  class=3D376395620-06062002>Prabhu/~</SPAN></FONT></DIV>
  <DIV><FONT color=3D#0000ff face=3D"Courier New" size=3D2><SPAN=20
  class=3D376395620-06062002></SPAN></FONT>&nbsp;</DIV>
  <BLOCKQUOTE style=3D"MARGIN-RIGHT: 0px">
    <DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
    size=3D2>-----Original Message-----<BR><B>From:</B> Barry Katz [<A=20
    =
href=3D"mailto:[email-masked]">mailto:[email-masked]</A>]<BR><B>Sent:=
</B>=20
    Thursday, June 06, 2002 3:48 AM<BR><B>To:</B> Hegazy, Hazem; 'Monika =
Garg';=20
    <A=20
    =
href=3D"mailto:[email-masked]">[email-masked]</A><BR><B>Subject:<=
/B>=20
    Re: [IBIS-Users] Info on IBIS for LVDS<BR><BR></DIV></FONT>
    <DIV><FONT size=3D2>Hi Monika,</FONT></DIV>
    <DIV>&nbsp;</DIV>
    <DIV><FONT size=3D2>In addition to Hazem's presentation there was a =
paper=20
    given at this year's DesignCon by Adam Tambone (Fairchild).&nbsp; =
Also, Doug=20
    Burns (SiSoft) will be giving a presentation on&nbsp;our experience =
with=20
    IBIS LVDS Modeling at the Design Automation Conference IBIS Summit =
next=20
    Thursday.&nbsp; This presentation should be uploaded to the IBIS =
website=20
    shortly after the Summit.&nbsp; You will be able to get Doug's =
presentation=20
    directly from&nbsp;me as well.</FONT></DIV>
    <DIV>&nbsp;</DIV>
    <DIV><FONT size=3D2>Barry</FONT></DIV>
    <DIV>&nbsp;</DIV>
    <DIV>&nbsp;</DIV>
    <DIV>Barry Katz<BR>President &amp; CTO<BR>Signal Integrity Software, =

    Inc.<BR>6 Clock Tower Place, Suite 250<BR>Maynard, MA 01754<BR>978 =
461 0449=20
    x19<BR><A href=3D"http://www.sisoft.com">www.sisoft.com</A></DIV>
    <BLOCKQUOTE=20
    style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; =
MARGIN-RIGHT: 0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
      <DIV style=3D"FONT: 10pt arial">----- Original Message ----- =
</DIV>
      <DIV=20
      style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
      <A href=3D"mailto:[email-masked]"=20
      title=[email-masked]>Hegazy, Hazem</A> </DIV>
      <DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[email-masked]"=20
      title=[email-masked]>'Monika Garg'</A> ; <A=20
      href=3D"mailto:[email-masked]"=20
      title=[email-masked]>[email-masked]</A> </DIV>
      <DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, June 06, =
2002 3:52=20
      AM</DIV>
      <DIV style=3D"FONT: 10pt arial"><B>Subject:</B> RE: [IBIS-Users] =
Info on=20
      IBIS for LVDS</DIV>
      <DIV><BR></DIV>
      <P><FONT size=3D2>Hi,</FONT> </P>
      <P><FONT size=3D2>This is one of my presentations in IBIS summits =
January=20
      2001 describes various modeling technique of LVDS buffers.</FONT>=20
      <BR><FONT size=3D2>If you have any questions, fell free to email =
my=20
      with.</FONT> </P>
      <P><FONT size=3D2><A=20
      href=3D"http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip"=20
      =
target=3D_blank>http://www.eda.org/pub/ibis/summits/jan01/hegazy.zip</A><=
/FONT>=20
      </P>
      <P><FONT size=3D2>BR,</FONT> </P><BR>
      <P><FONT size=3D2>-----Original Message-----</FONT> <BR><FONT =
size=3D2>From:=20
      Monika Garg [<A=20
      href=3D"mailto:[email-masked]">mailto:[email-masked]</A>]</FONT> =
<BR><FONT=20
      size=3D2>Sent: Thursday, June 06, 2002 3:15 AM</FONT> <BR><FONT =
size=3D2>To:=20
      <A=20
      =
href=3D"mailto:[email-masked]">[email-masked]</A></=
FONT>=20
      <BR><FONT size=3D2>Subject: [IBIS-Users] Info on IBIS for =
LVDS</FONT>=20
      </P><BR>
      <P><FONT size=3D2>Hi,</FONT> </P>
      <P><FONT size=3D2>I need to generate IBIS Model for a chip that =
has 4=20
      different types of </FONT><BR><FONT size=3D2>IOs. As i understand =
i need to=20
      provide 4 IBIS Models for each different </FONT><BR><FONT =
size=3D2>type of=20
      IO. These IOs are of LVDS type. Is there any information on what=20
      </FONT><BR><FONT size=3D2>cautions i need to take while developing =
IBIS for=20
      LVDS?</FONT> </P>
      <P><FONT size=3D2>Thanks in advance for all the help.</FONT> =
<BR><FONT=20
      size=3D2>Monika</FONT> </P><BR>
      <P><FONT=20
      =
size=3D2>|---------------------------------------------------------------=
- ---</FONT>=20
      <BR><FONT size=3D2>|For help or to subscribe/unsubscribe, email=20
      [email-masked]</FONT> <BR><FONT size=3D2>|with just the =
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      command message(s) in the body:</FONT> <BR><FONT size=3D2>|</FONT> =
<BR><FONT=20
      size=3D2>|&nbsp; help</FONT> <BR><FONT size=3D2>|&nbsp; =
subscribe&nbsp;&nbsp;=20
      ibis&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; &lt;optional e-mail =
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      different&gt;</FONT> <BR><FONT size=3D2>|&nbsp; =
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      E-mail since 1993</FONT>=20
</P></BLOCKQUOTE></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>

- ------=_NextPart_000_01EE_01C20DEE.B09C3540--

|------------------------------------------------------------------
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|with just the appropriate command message(s) in the body:
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------------------------------

Date: Fri, 07 Jun 2002 08:46:56 -0700
From: "Ross, Bob" <[email-masked]>
Subject: Re: [IBIS-Users] Info on IBIS for LVDS

Hello Mohan:

Several contributions were made at the DesignCon 2002 and are available:

  http://www.iec.org/pubs/proceedings/2002/designcon.html

Adam's presentation or a variation of it is also available here:

http://www.commsdesign.com/design_center/netprocessing/design_corner/OEG20020403S0018

Best Regards,
Bob Ross
Mentor Graphics

- ----

Hi,
 
Adam gave his presentation in a session at DesignCon (not at the IBIS summit). 
I know the papers are in the proceedings.  I will ask, Adam how presentation can
be made available on the web.
 
Barry

- ----- Original Message ----- 

      From: Mohan, Prabhu 
      To: [email-masked] 
      Sent: Thursday, June 06, 2002 4:54 PM
      Subject: RE: [IBIS-Users] Info on IBIS for LVDS

      Hi
       
      Can you send a pointer to Adam Tambone's presentation. I can't seem to
find it.
       
      Its not here http://www.eda.org/pub/ibis/summits/jan02/?
       
      Thanks
      Prabhu/~
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------------------------------

Date: Mon, 10 Jun 2002 20:01:56 +0900
From: Takanobu Ura <[email-masked]>
Subject: [IBIS-Users] The buffer have a outside terminal: Pls teach me modeling method

Dear All,

Regarding IBIS modeling method, In case of the buffer have a outside pullup
terminal, Do we need to analyze with waveform-SPICE-netlist including outside 
pullup terminal?

For example, HSTL buffer is used as follows:
 Buffer terminal  Transmission line
 -----><-------><--------
        Vdd/2                  Vdd/2
         -+-                    -+-
          |                      |
          R                      R
          |       R=50ohm        |
     |>---+------/////-----------+---|>

We analyzed as follows:
V-I table

       |>--------------+
                       |
                       V   External Voltage Sweep
                       |    
                      /// GND

V-t table

   RisingWaveform/FalingWaveform
            VDD/2
             -+-
              |
              R1       V_fixture=Vdd/2
              |        R_fixture=R1
   Vin-|>-----+

When we generate IBIS-model with  above the SPICE-netlist, Ibischk3 reports
the below error message:
ERROR - Model HSTL1: The [Rising Waveform] 
      with [R_fixture]=50 Ohms and [V_fixture]=1.5V
      has TYP column DC endpoints of  0.00V and  1.29v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 0.16V and  1.50V),
      a difference of 100.00% and 14.00%, respectively.

Please let me know modeling method which the buffer have a outside pullup 
terminal.  

Best regards,
T.Ura
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------------------------------

Date: Mon, 10 Jun 2002 16:34:27 +0300
From: "Hegazy, Hazem" <[email-masked]>
Subject: RE: [IBIS-Users] The buffer have a outside terminal: Pls teach me modeling method

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C21083.8AF874F7
Content-Type: text/plain;
	charset="iso-2022-jp"

Hi,
From what I see here you made V-T table extraction with the PAD connected
with 50 Ohm resistor to ground and not VDD/2.
This clear from the ibischk3 warning it-self, as the wave form starts from
zero and going to 1.29 volts. This only happens when the load is connected
to ground or the starting (first) edge begins from wrong dc (Then you might
try the second rising/falling edge).

While the V_fixture inserted in the IBIS model was 1.5 volts for the same
V-T table!!
 
"ERROR - Model HSTL1: The [Rising Waveform] 
      with [R_fixture]=50 Ohms and [V_fixture]=1.5V
      has TYP column DC endpoints of  0.00V and  1.29v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 0.16V and  1.50V),
      a difference of 100.00% and 14.00%, respectively."

I think the I-V data is right as it doesn't begin from 0.0V at 50 Ohm to
1.5V which is normal.

BR,

- -----Original Message-----
From: Takanobu Ura [mailto:[email-masked]]
Sent: Monday, June 10, 2002 2:02 PM
To: [email-masked]
Cc: ???????; Ura Takanobu
Subject: [IBIS-Users] The buffer have a outside terminal: Pls teach me
modeling method

Dear All,

Regarding IBIS modeling method, In case of the buffer have a outside pullup
terminal, Do we need to analyze with waveform-SPICE-netlist including
outside 
pullup terminal?

For example, HSTL buffer is used as follows:
 Buffer terminal  Transmission line
 -----><-------><--------
        Vdd/2                  Vdd/2
         -+-                    -+-
          |                      |
          R                      R
          |       R=50ohm        |
     |>---+------/////-----------+---|>

We analyzed as follows:
V-I table

       |>--------------+
                       |
                       V   External Voltage Sweep
                       |    
                      /// GND

V-t table

   RisingWaveform/FalingWaveform
            VDD/2
             -+-
              |
              R1       V_fixture=Vdd/2
              |        R_fixture=R1
   Vin-|>-----+

When we generate IBIS-model with  above the SPICE-netlist, Ibischk3 reports
the below error message:
ERROR - Model HSTL1: The [Rising Waveform] 
      with [R_fixture]=50 Ohms and [V_fixture]=1.5V
      has TYP column DC endpoints of  0.00V and  1.29v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 0.16V and  1.50V),
      a difference of 100.00% and 14.00%, respectively.

Please let me know modeling method which the buffer have a outside pullup 
terminal.  

Best regards,
T.Ura
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|with just the appropriate command message(s) in the body:
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- ------_=_NextPart_001_01C21083.8AF874F7
Content-Type: text/html;
	charset="iso-2022-jp"
Content-Transfer-Encoding: quoted-printable

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<HTML>
<HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-2022-jp">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2655.35">
<TITLE>RE: [IBIS-Users] The buffer have a outside terminal: Pls teach =
me modeling method</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>Hi,</FONT>
<BR><FONT SIZE=3D2>From what I see here you made V-T table extraction =
with the PAD connected with 50 Ohm resistor to ground and not =
VDD/2.</FONT>
<BR><FONT SIZE=3D2>This clear from the ibischk3 warning it-self, as the =
wave form starts from zero and going to 1.29 volts. This only happens =
when the load is connected to ground or the starting (first) edge =
begins from wrong dc (Then you might try the second rising/falling =
edge).</FONT></P>

<P><FONT SIZE=3D2>While the V_fixture inserted in the IBIS model was =
1.5 volts for the same V-T table!!</FONT>
<BR><FONT SIZE=3D2>&nbsp;</FONT>
<BR><FONT SIZE=3D2>&quot;ERROR - Model HSTL1: The [Rising Waveform] =
</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; with [R_fixture]=3D50 =
Ohms and [V_fixture]=3D1.5V</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; has TYP column DC =
endpoints of&nbsp; 0.00V and&nbsp; 1.29v, but</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; an equivalent load =
applied to the model's I-V tables yields</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; different voltages ( =
0.16V and&nbsp; 1.50V),</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; a difference of =
100.00% and 14.00%, respectively.&quot;</FONT>
</P>

<P><FONT SIZE=3D2>I think the I-V data is right as it doesn't begin =
from 0.0V at 50 Ohm to 1.5V which is normal.</FONT>
</P>

<P><FONT SIZE=3D2>BR,</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Takanobu Ura [<A =
HREF=3D"mailto:[email-masked]">mailto:[email-masked]</A>]</FON=
T>
<BR><FONT SIZE=3D2>Sent: Monday, June 10, 2002 2:02 PM</FONT>
<BR><FONT SIZE=3D2>To: [email-masked]</FONT>
<BR><FONT SIZE=3D2>Cc: ???????; Ura Takanobu</FONT>
<BR><FONT SIZE=3D2>Subject: [IBIS-Users] The buffer have a outside =
terminal: Pls teach me modeling method</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Dear All,</FONT>
</P>

<P><FONT SIZE=3D2>Regarding IBIS modeling method, In case of the buffer =
have a outside pullup</FONT>
<BR><FONT SIZE=3D2>terminal, Do we need to analyze with =
waveform-SPICE-netlist including outside </FONT>
<BR><FONT SIZE=3D2>pullup terminal?</FONT>
</P>

<P><FONT SIZE=3D2>For example, HSTL buffer is used as follows:</FONT>
<BR><FONT SIZE=3D2>&nbsp;Buffer terminal&nbsp; Transmission line</FONT>
<BR><FONT SIZE=3D2>&nbsp;-----&gt;&lt;-------&gt;&lt;--------</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Vdd/2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Vdd/2</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
- -+-&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -+-</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
|&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
R&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
|&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
R=3D50ohm&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp; =
|&gt;---+------/////-----------+---|&gt;</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>We analyzed as follows:</FONT>
<BR><FONT SIZE=3D2>V-I table</FONT>
</P>

<P><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
|&gt;--------------+</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
|</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
V&nbsp;&nbsp; External Voltage Sweep</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
|&nbsp;&nbsp;&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; /// =
GND</FONT>
</P>

<P><FONT SIZE=3D2>V-t table</FONT>
</P>

<P><FONT SIZE=3D2>&nbsp;&nbsp; RisingWaveform/FalingWaveform</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp; VDD/2</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp; -+-</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; |</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; R1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
V_fixture=3DVdd/2</FONT>
<BR><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
R_fixture=3DR1</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp; Vin-|&gt;-----+</FONT>
</P>

<P><FONT SIZE=3D2>When we generate IBIS-model with&nbsp; above the =
SPICE-netlist, Ibischk3 reports</FONT>
<BR><FONT SIZE=3D2>the below error message:</FONT>
<BR><FONT SIZE=3D2>ERROR - Model HSTL1: The [Rising Waveform] </FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; with [R_fixture]=3D50 =
Ohms and [V_fixture]=3D1.5V</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; has TYP column DC =
endpoints of&nbsp; 0.00V and&nbsp; 1.29v, but</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; an equivalent load =
applied to the model's I-V tables yields</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; different voltages ( =
0.16V and&nbsp; 1.50V),</FONT>
<BR><FONT SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; a difference of =
100.00% and 14.00%, respectively.</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Please let me know modeling method which the buffer =
have a outside pullup </FONT>
<BR><FONT SIZE=3D2>terminal.&nbsp; </FONT>
</P>

<P><FONT SIZE=3D2>Best regards,</FONT>
<BR><FONT SIZE=3D2>T.Ura</FONT>
<BR><FONT =
SIZE=3D2>|--------------------------------------------------------------=
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</BODY>
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------------------------------

Date: Tue, 11 Jun 2002 13:57:03 -0400
From: John Angulo <[email-masked]>
Subject: [IBIS-Users] FW: IBIS Modeling Clarification

The following is posted on behalf of Andris Lauzums.  Please send all
private replies to [email-masked].

- -------------------------------------
Hello.  I am currently constructing an IBIS model for a RS-485 Differential
Output transceiver.   This is my first attempt at IBIS modeling, and I am
uncertain about what values to specify for certain [model] parameters.

I am attempting to extract rising and falling waveform data on a bench using
a Tektronics TDS-3040 (300MHZ  2.5GS/s ....The 300mHZ bandwidth does not
seem to be limiting my rise and fall time readings)  along with a 10X  8.7pF
test probe and a HP 8131A Pulse Generator.  My test board is a copper-clad
type breadboard that does not seem to adversely affect my AC test readings.

The model type is an RECEIVER/DRIVER_BI  I/O (Driver output, Receiver Input)

I am uncertain about what Vinh, Vinl, Vmeas, Cref, Rref, and Vref parameters
to specify.

The datasheet specifies high and low Voltage input thresholds at 0.8V, and
2.0V....Do i use these values for Vinh, and Vinl?  What high and low input
voltages do I set on my pulse generator?  

Is the Vmeas parameter the delta between Vinh and Vin?   What is this
"Reference Voltage for timing Measurements"?

What do i specify for my Cref value?  My board has 12.5pF of capacitance
betewwn my I/O pin and GND.  Do i use my board capacitance value?  I not
using any caps from my I/O pin to GND

I terminated my differential output pins with a 54.9 ohm resistor.  Is this
the R_ref,  R_load, or R_fixture value that i need to specify?  

Is my V_fixture value the same as my V_meas as well?

What do i specify for C_fixture and L_fixture?

In other words:

I am trying to figure out what values to include for the following
parameters:

Vinh
Vinl
Vmeas
Cref
Rref
Rload
Rfixture
Vfixture
Cfixture
Lifixture

I have read through the various articles on the ANSI/EIA-656-A Homepage.  It
has proved to be a great source of information, although because of my
unfamillarity with IBIS, it has left me unclear on the problems that I
describe above.  I would appreciate any assistance that can be provided.  I
can be reached at (321) 729-4811.  I hope this forum can help me get my
project underway.  

Thanks, 

Andris Lauzums

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------------------------------

Date: Thu, 13 Jun 2002 20:34:49 -0400
From: John Angulo <[email-masked]>
Subject: [IBIS-Users] FW: ibis doubt

The following is posted on behalf of Akhilesh Chandra.  Please send all
private replies to [email-masked].

John Angulo
IBIS Open Forum Postmaster

- -----Original Message-----
From: [email-masked] [mailto:[email-masked]]
Sent: Thursday, June 13, 2002 4:12 AM
To: [email-masked]
Subject: ibis doubt

Hello,

      Can you explain me what information we put in Vmeans, Cref, Rref &
Vref keywards & how this information used by customer.

I have some problems

1-     Our ibischecker take file name in small & if we put file name     
   in capital then it gives error Why it is so. 
       Except IBIS all others models file name in capital so when we     
   use IBIS model in our flow then it is crash.
       So it is better if our ibischecker take file name case            
   insensitive.

 2-   Some time our file name is more than 12 character then also our    
    ibischecker gives error, it should we user dependent not             
  hardcoded.

 3-   When our file name have more then one period then ibischecker also 
   shows error I think ibischecker shoud read more then one period.

  Thanks in advance for your prompt response.

Regards
Akhilesh
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------------------------------

Date: Thu, 13 Jun 2002 18:22:45 -0700
From: "Bill Hargin" <[email-masked]>
Subject: RE: [IBIS-Users] FW: ibis doubt

Hello Akhilesh:

>       Can you explain me what information we put in Vmeans, Cref, Rref &
> Vref keywards & how this information used by customer.

Cref, Rref, Vref, and Vmeas are optional subparameters to the [Model]
keyword.  Include them, typically, to facilitate board-level timing
simulation.  Cref and Rref subparameters correspond to the test load that
the semiconductor vendor uses when specifying the propagation delay and/or
output switching time of the model.  The IBIS 3.2 spec shows the assumed
connections as:

|                            _________
|                           |         |
|                           |      |\ |            Rref
|                           |Driver| \|------o----/\/\/\----o Vref
|                           |      | /|      |
|                           |      |/ |     === Cref
|                           |_________|      |
|                                            |
|                                           GND

> 1-     Our ibischecker take file name in small & if we put file name
>    in capital then it gives error Why it is so.

It's probably easier to just go with the IBIS spec--which only supports 8.3
file names, all lower case characters--than to fight it.  The reason for
these formatting requirements is to support both Windows and UNIX platforms
seamlessly.

I mentioned this on the SI List earlier, so I'll do it here too.  My company
does IBIS training and SPICE-to-IBIS conversions.  Details and links below.

IBIS Training - http://www.CognitionConsulting.com/seminars.htm
     IBIS 101 — Introduction/overview.
                (½ - 1 day, depending on customer needs.)
                Can be incorporated with "High Speed Design" and/or
                HyperLynx training.
     IBIS 501 — Advanced IBIS modeling class; emphasis on IBIS 3.2 features
                and SPICE-to-IBIS conversions. (1 day)
     IBIS 505 — Advanced; emphasis on LVDS. (1 day)

IBIS Modeling; SPICE-2-IBIS Conversion -
http://www.CognitionConsulting.com/ibis.htm

Best Regards,
Bill Hargin
Direct: 425-702-0744
Fax:    425-702-0305

Cognition Consulting
Electronic Design Software and Consulting
http://www.CognitionConsulting.com

> -----Original Message-----
> From: [email-masked]
> [mailto:[email-masked]]On Behalf Of John Angulo
> Sent: Thursday, June 13, 2002 5:35 PM
> To: [email-masked]
> Subject: [IBIS-Users] FW: ibis doubt
>
>
> The following is posted on behalf of Akhilesh Chandra.  Please send all
> private replies to [email-masked].
>
> John Angulo
> IBIS Open Forum Postmaster
>
> -----Original Message-----
> From: [email-masked] [mailto:[email-masked]]
> Sent: Thursday, June 13, 2002 4:12 AM
> To: [email-masked]
> Subject: ibis doubt
>
>
> Hello,
>
>       Can you explain me what information we put in Vmeans, Cref, Rref &
> Vref keywards & how this information used by customer.
>
> I have some problems
>
> 1-     Our ibischecker take file name in small & if we put file name
>    in capital then it gives error Why it is so.
>        Except IBIS all others models file name in capital so when we
>    use IBIS model in our flow then it is crash.
>        So it is better if our ibischecker take file name case
>    insensitive.
>
>  2-   Some time our file name is more than 12 character then also our
>     ibischecker gives error, it should we user dependent not
>   hardcoded.
>
>  3-   When our file name have more then one period then ibischecker also
>    shows error I think ibischecker shoud read more then one period.
>
>   Thanks in advance for your prompt response.
>
> Regards
> Akhilesh
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------------------------------

Date: Thu, 13 Jun 2002 18:44:07 -0700
From: Kar Hooi Kuan <[email-masked]>
Subject: [IBIS-Users] ibis

Hello,

      Can you explain me what information we put in Vmeans, Cref, Rref &
Vref keywards & how this information used by customer.

Regards,
________________________________
Kar Hooi Kuan
Applications Engineer
Altera Corporation Penang
Plot 6, Bayan Lepas Technoplex, Medan Bayan Lepas
11900 Penang, Malaysia
Tel(hp): 6012-5611508
     (O) : 604-6366471
   (Fax): 604-642-8525 

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------------------------------

Date: Thu, 13 Jun 2002 20:48:52 -0700
From: "Bill Hargin" <[email-masked]>
Subject: RE: [IBIS-Users] ibis

Hi Kar Hooi:

>       Can you explain me what information we put in Vmeans, Cref, Rref &
> Vref keywards & how this information used by customer.

See my last e-mail for a generic overview of Vmeas, Cref, Rref & Vref.

More info. on Vmeas:
The Vmeas subparameter is the reference voltage level that the semiconductor
vendor uses for the model.

Vmeas is used -- by an SI simulator, for example -- for timing calculations.
It's the Output equivalent of Vinl and Vinh for an Input model.  (An I/O
could include all three.)  Vmeas is the point at which the Driver is
considered to be "switched."

Timing delay can be calculated by subtracting the point at which a the
Driver crosses Vmeas from the point at which the Receiver waveform crosses
Vinl (falling edge) or Vinh (rising edge).

Best Regards,
Bill Hargin
Direct: 425-702-0744
Fax:    425-702-0305

Cognition Consulting
Electronic Design Software and Consulting
http://www.CognitionConsulting.com

> -----Original Message-----
> From: [email-masked]
> [mailto:[email-masked]]On Behalf Of Kar Hooi Kuan
> Sent: Thursday, June 13, 2002 6:44 PM
> To: [email-masked]
> Subject: [IBIS-Users] ibis
>
>
> Hello,
>
>       Can you explain me what information we put in Vmeans, Cref, Rref &
> Vref keywards & how this information used by customer.
>
>
> Regards,
> ________________________________
> Kar Hooi Kuan
> Applications Engineer
> Altera Corporation Penang
> Plot 6, Bayan Lepas Technoplex, Medan Bayan Lepas
> 11900 Penang, Malaysia
> Tel(hp): 6012-5611508
>      (O) : 604-6366471
>    (Fax): 604-642-8525
>
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------------------------------

Date: Mon, 17 Jun 2002 11:46:44 -0700
From: "Ross, Bob" <[email-masked]>
Subject: [IBIS-Users] Re: ibis doubt

Hello Akhilesh:

I have some parser responses in your text.

Bob Ross
Mentor Graphics

[email-masked] wrote:
> 
> Hello,
> 
>       Can you explain me what information we put in Vmeans, Cref, Rref &
> Vref keywards & how this information used by customer.
> 
> I have some problems
> 
> 1-     Our ibischecker take file name in small & if we put file name
>    in capital then it gives error Why it is so.
>        Except IBIS all others models file name in capital so when we
>    use IBIS model in our flow then it is crash.
>        So it is better if our ibischecker take file name case
>    insensitive.

We chose to make the file name lower case to avoid case sensitive
distinctions in Unix systems and also to standardize in Windows
formats.

> 
>  2-   Some time our file name is more than 12 character then also our
>     ibischecker gives error, it should we user dependent not
>   hardcoded.

Set the [IBIS Ver] to 3.2 and the error should go away.  We went with
20.3 in Version 3.2.

> 
>  3-   When our file name have more then one period then ibischecker also
>    shows error I think ibischecker shoud read more then one period.

I do not believe we support the "." in a file name other than to separate
the file name from the "ibs" or other legal extension.

> 
>   Thanks in advance for your prompt response.
> 
> Regar
> Akhilesh
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------------------------------

Date: Tue, 18 Jun 2002 18:35:35 -0400
From: John Angulo <[email-masked]>
Subject: [IBIS-Users] FW: Quickstart into IBIS / Service for urgent IBIS m odeling

The following is posted on behalf of Harald Hardter.  Please send all
private replies to [email-masked].

- ------------------------
Hello,

Micronas need to start IBIS support for our customers. Details are not
discussed yet but we have already an urgent request from Sony to provide
IBIS model for one of our new ICs.
Do you have a list of service providers offering HSPICE to IBIS conversion
in Germany. 

Thanks in advance

Harald Härdter
[email-masked]
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------------------------------

Date: Fri, 21 Jun 2002 08:47:14 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] Agenda, IBIS Open Forum Meeting 6/28

		     IBIS Open Forum Meeting Agenda
			      for 6/28/02

		 Bridge Number    Reservation #   Passcode
             1-888-316-5901   N/A             2358667
             (International Dial-In: 1-617-801-9781)

All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
meeting, ask for the IBIS Open Forum hosted by Stephen Peters and give the
Reservation Number and Passcode.

8:00 Check-In, Intros, Announcements                         Peters

     - Intros of New IBIS Participants, Meeting Quorum       Peters
     - Membership Update and Treasurers Report               Peters
     - Review of Previous Meeting's Minutes (and ARs)        Peters
     - Miscellany/Announcements                              All
     - Press & Web Page Updates                              Huq, All
     - New Models Available, Library Update                  Leventhal, All
     - Opens for New Issues                                  All

8:15 Administrative and Project Discussions

     International/External Progress
     - IEC 62014-3 (ICEM) Integrated Circuits Electromagnetic 
       Model Proposal (IEC 93/67/NP IBIS and EMC Simulation) Perrin/Peters
     - JEDEC JC-16 Modeling and Testing                      Sessions
     - T10, Project 1414-DT - SCSI Signal Modeling           Barnes

     DAC IBIS Summit Meeting Feedback                        Peters

     Following IBIS Summit Meetings                          Peters

     IBIS Qualification Committee                            Katz

     IBIS Open Source Parser Proposal Discussion             Katz

     IBIS Model Review Committee                             Peters

     Majordomo Update                                        Angulo

     New Administrative Issues                               All

8:45 Technical Discussion

     IBIS Version 4.0 Discussion/BIRD75                      Peters

     IBIS Version 4.0 Review                                 Peters

     IBIS Connector and Futures Group Report                 Peters

     BIRD74.1 - EMI Parameters                               de Burgh

     BIRD75.1 - Multi-Lingual IBIS Model Support             Peters/Muranyi

     ibischk3 Status                                         Peters

     New Technical Issues                                    All

9:50 Wrap Up and Next Meetings Plans                         Peters

9:55 Sign Off

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------------------------------

Date: Wed, 26 Jun 2002 13:51:42 -0400
From: John Angulo <[email-masked]>
Subject: [IBIS-Users] Reg spice model file usage

The following is posted on behalf of Senthilkumar Kalidoss at IDT.  Please
send all private replies to [email-masked].

John Angulo
IBIS Open Forum Postmaster 

- -----Original Message-----

Date: Tue, 25 Jun 2002 14:12:36 -0700
From: "Senthilkumar.Kalidoss" <[email-masked]>
Organization: Integrated Device Technology
To: [email-masked]
Subject: Reg spice model file usage

Hi,
  I am trying to run s2ibis2.11 to get IBIS model. Unlike the example
spice model file which does not have any library definition inside, my
current Spice model file has TT,SS,FF etc library definitions. Under
each MOS library there are 12 cases. How do i refer the models in the
s2i file . In [model file] i can only specify just file names.

I appreciate your reply.

Thank You,

Senthil

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------------------------------

Date: Thu, 27 Jun 2002 11:27:32 -0500
From: John Phillippe <[email-masked]>
Subject: [IBIS-Users] Rising/Falling Waveform generation

Dear Everyone,
  I can't seem to generate decent rising and falling waveforms in IBIS. 
After looking at the generated spice files, I found that the problem was
with the Rfixture and Vfixture.  I found that if I didn't use a test
fixture of any kind, then the waveforms came out correct.  However I had
to manually generate them.  So I went back and tried monkeying with the
Rfixture values, and found that a 100K resistor seems to allow IBIS to
generate a good waveform.  
  I've never used an IBIS model in a simulation environment before, and
so I guess my question is regarding the Rfixture, and what it is used
for.  Could I manually generate my edges and then specify an Rfixture of
0 ohms in the ibis file?  Is having an Rfixture of 100k going to cause
any problems for the end users?

- -- 
John Phillippe
SPS, 32 Bit Embedded Controller Division, IC Creation
Motorola      -  512-895-1835
Austin, TX    -  [email-masked]
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------------------------------

Date: Thu, 27 Jun 2002 09:52:11 -0700
From: Scott McMorrow <[email-masked]>
Subject: Re: [IBIS-Users] Rising/Falling Waveform generation

John,

My guess is there is something wrong with your simulation deck setup. 
 Rfixture and Vfixture is simple load placed on the output of your 
buffer during VT table extraction.  It is no different than setting up 
your spice deck by hand, attaching a pulse source to the input of the 
buffer and a resistive load to the output of the buffer and simulating. 
 If your buffer is capable of driving a 50 ohm load, then there should 
not be a problem with spice2ibis.  If there is, it would be generally a 
setup or connectivity problem.

An Rfixture of 100K would be useless to an ibis simulator, since the 
simulator will attempt to scale the rising and falling waveforms to the 
actual load impedance of 50 to 75 ohms in system.  This scaling would 
cause significant waveform errors.

My suggestion is to setup the buffer independently of spice2ibis and 
verify that it actually is capable of driving a standard load.  If it 
is, then you have an issue with the connections  in the decks used for 
ibis extraction.

Regards,

Scott

John Phillippe wrote:

>Dear Everyone,
>  I can't seem to generate decent rising and falling waveforms in IBIS. 
>After looking at the generated spice files, I found that the problem was
>with the Rfixture and Vfixture.  I found that if I didn't use a test
>fixture of any kind, then the waveforms came out correct.  However I had
>to manually generate them.  So I went back and tried monkeying with the
>Rfixture values, and found that a 100K resistor seems to allow IBIS to
>generate a good waveform.  
>  I've never used an IBIS model in a simulation environment before, and
>so I guess my question is regarding the Rfixture, and what it is used
>for.  Could I manually generate my edges and then specify an Rfixture of
>0 ohms in the ibis file?  Is having an Rfixture of 100k going to cause
>any problems for the end users?
>
>  
>

- -- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com

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------------------------------

Date: Fri, 28 Jun 2002 13:39:36 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] BIRD75 -- Additional Information Related to C_comp Refinements

Greetings:

  During the editorial review of IBIS 4.0 several issues were noted with
text added by BIRD65, C_comp 
Refinements.  The following BIRD is intended to address these issues.  While
no technical changes were
made, and the intent of  BIRD65 remains the same, the text changes were
extensive enough to warrant
official documentation as a BIRD.

BIRD76 is scheduled for discussion and vote at the June 19, 2002
teleconference, and will proceed any
vote on the IBIS 4.0 specification itself.  

If you have any comments on this bird please you are encouraged to post them
to the IBIS reflector
for discussion.

  Regards,
  Stephen Peters
  Intel Corp.
  Chair EIA/IBIS Open Forum

****************************************************************************
**
****************************************************************************
**

BIRD ID#:        76
ISSUE TITLE:     Additional Information Related to C_comp Refinements
REQUESTER:       Arpad Muranyi, Stephen Peters, Intel
DATE SUBMITTED:  June 28, 2002
DATE ACCEPTED BY IBIS OPEN FORUM: Pending

****************************************************************************
**
****************************************************************************
**

STATEMENT OF THE ISSUE:

During the review of IBIS 4.0, several documentation issues were raised with
the original BIRD 65.2. Important information was only documented in the
"Statement of the issue", "Statement of the resolved specifications" and
"Analysis data/path that led to specification" sections of the BIRD.
Specifically, there was no text added to the specification that described
how
the additional distributed capacitances created by BIRD65 were to be applied
to the prototype simulation model.  In addition, some of the usage rules did
not
distinquish between use of a subparameter and use of its value.  Therefore,
this
BIRD is proposed.

This new version contains only editorial changes and additions to the
current
text.  Changes are indicated by "****" at the beginning of the changed
lines. 

****************************************************************************
**

STATEMENT OF THE RESOLVED SPECIFICATIONS:

Four new subparameters shall be introduced in the IBIS specification under
the [Model] keyword to provide means for a more detailed description for the
die capacitance.  These new subparameters, C_comp_pullup, C_comp_pulldown,
C_comp_power, and C_comp_gnd are associated with the corresponding voltage
reference keywords, [Pullup Reference], [Pulldown Reference], [Power Clamp
Reference], and [GND Clamp Reference], respectively.  This mechanism allows
the association of a specific capacitance between the I/O node and the four
possible supply nodes without disturbing the submodel syntax.

The syntax of these four new subparameters are identical to the existing
C_comp subparameter.

|===========================================================================
==
|     Keyword:  [Model] 
|    Required:  Yes.
| Description:  Used to define a model, and its attributes.
|  Sub-Params:  Model_type, Polarity, Enable, Vinl, Vinh, C_comp,
|****           C_comp_pullup, C_comp_pulldown, C_comp_power_clamp, and
|****           C_comp_gnd_clamp Vmeas, Cref, Rref, Vref
| Usage Rules:  Each model type must begin with the keyword [Model].  The
|               model name must match the one that is listed under a [Pin],
|               [Model Selector] or [Series Pin Mapping] keyword and must
not
|               contain more than 20 characters.  A .ibs file must contain
|               enough [Model] keywords to cover all of the model names
|               specified under the [Pin], [Model Selector] and [Series Pin
|               Mapping] keywords, except for those model names that use
|               reserved words (POWER, GND and NC).
|
|               Model_type must be one of the following:
|
|               Input, Output, I/O, 3-state, Open_drain, I/O_open_drain,
|               Open_sink, I/O_open_sink, Open_source, I/O_open_source,
|               Input_ECL, Output_ECL, I/O_ECL, 3-state_ECL, Terminator,
|               Series, and Series_switch.
|
|               Special usage rules apply to the following.  Some
definitions
|               are included for clarification:
|
|               Input              These model types must have Vinl and Vinh
|               I/O                defined.  If they are not defined, the
|               I/O_open_drain     parser issues a warning and the default
|               I/O_open_sink      values of Vinl = 0.8 V and Vinh = 2.0 V
are
|               I/O_open_source    assumed.
|
|               Input_ECL          These model types must have Vinl and Vinh
|               I/O_ECL            defined.  If they are not defined, the
|                                  parser issues a warning and the default
|                                  values of Vinl = -1.475 V and Vinh =
|                                  -1.165 V are assumed.
|
|               Terminator         This model type is an input-only model
|                                  that can have analog loading effects on
the
|                                  circuit being simulated but has no
digital
|                                  logic thresholds.  Examples of
Terminators
|                                  are: capacitors, termination diodes, and
|                                  pullup resistors.
|
|               Output             This model type indicates that an output
|                                  always sources and/or sinks current and
|                                  cannot be disabled.
|
|               3-state            This model type indicates that an output
|                                  can be disabled, i.e. put into a high
|                                  impedance state.
|
|               Open_sink          These model types indicate that the
output
|               Open_drain         has an OPEN side (do not use the [Pullup]
|                                  keyword, or if it must be used, set I =
|                                  0 mA for all voltages specified) and the
|                                  output SINKS current.  Open_drain model
|                                  type is retained for backward
|                                  compatibility.
|
|               Open_source        This model type indicates that the output
|                                  has an OPEN side (do not use the
[Pulldown]
|                                  keyword, or if it must be used, set I =
|                                  0 mA for all voltages specified) and the
|                                  output SOURCES current.
|
|               Input_ECL          These model types specify that the model
|               Output_ECL         represents an ECL type logic that follows
|               I/O_ECL            different conventions for the [Pulldown]
|               3-state_ECL        keyword.
|
|               Series             This model type is for series models that
|                                  can be described by [R Series], [L
Series],
|                                  [Rl Series], [C Series], [Lc Series],
|                                  [Rc Series], [Series Current] and [Series
|                                  MOSFET] keywords
|                                 
|               Series_switch      This model type is for series switch
|                                  models that can be described by [On],
|                                  [Off], [R Series], [L Series], [Rl
Series],  
|                                  [C Series], [Lc Series], [Rc Series],
|                                  [Series Current] and [Series MOSFET]
|                                  keywords
|
|**             The Model_type subparameter is required.
|****
|****           The C_comp subparameter is required only when C_comp_pullup,
|****           C_comp_pulldown, C_comp_power_clamp, and C_comp_gnd_clamp
are
|****           not present.  If the C_comp subparameter is not present, at
|****           least one of the C_comp_pullup, C_comp_pulldown,
|****           C_comp_power_clamp, or C_comp_gnd_clamp subparameters is
|****           required.  It is not illegal to include the C_comp
subparameter 
|****           together with one or more of the remaining C_comp* 
|****           subparameters, but in that case the simulator tool will have
to
|****           make a decision whether to use C_comp or the C_comp_pullup,
|****           C_comp_pulldown, C_comp_power_clamp, and C_comp_gnd_clamp
|****           subparameters.  Under no circumstances should the simulator
use
|****           the value of C_comp simultaneously with the values of other
|****           C_comp* subparameters.
|
|****           C_comp_pullup, C_comp_pulldown, C_comp_power_clamp, and
|****           C_comp_gnd_clamp are intended to represent the parasitic
|****           capacitances of those structures who's I-V characteristics
|****           are described by the [Pullup], [Pulldown], [POWER Clamp] and
|****           [GND Clamp] I-V curves.  For this reason, the simulator tool
|****           should generate a circuit netlist so that, if defined, each
of
|****           the C_comp* capacitors are connected parallel with their
|****           corresponding I-V curve generators, that is between the
signal
|****           pad and the nodes defined by the [Pullup Reference],
|****           [Pulldown Reference], [POWER Clamp Reference] and [GND Clamp
|****           Reference] keywords, or the [Voltage Range] keyword and GND.
|
|****           The C_comp and C_comp* parameters define die capacitance.
These
|****           values should not include the capacitance of the package.
|****           C_comp and C_comp* are allowed to use "NA" for the min and
max
|****           values only.  
|
|****           The Polarity, Enable, Vinl, Vinh, Vmeas, Cref, Rref, and
Vref
|****           subparameters are optional.  The Polarity subparameter can
be
|               defined as either Non-Inverting or Inverting, and the Enable
|               subparameter can be defined as either Active-High or
|               Active-Low.
|
|               The Cref and Rref subparameters correspond to the test load
|               that the semiconductor vendor uses when specifying the
|               propagation delay and/or output switching time of the model.
|               The Vmeas subparameter is the reference voltage level that
the
|               semiconductor vendor uses for the model.  Include Cref,
Rref,
|               Vref, and Vmeas information to facilitate board-level timing
|               simulation.  The assumed connections for Cref, Rref, and
Vref
|               are shown in the following diagram:
|
|                            _________
|                           |         |
|                           |      |\ |            Rref
|                           |Driver| \|------o----/\/\/\----o Vref
|                           |      | /|      |
|                           |      |/ |     === Cref
|                           |_________|      |
|                                            |
|                                           GND
|
| Other Notes:  A complete [Model] description normally contains the
following
|               keywords:  [Voltage Range], [Pullup], [Pulldown], [GND
Clamp],
|               [POWER Clamp], and [Ramp].  A Terminator model uses one or
|               more of the [Rgnd], [Rpower], [Rac], and [Cac].  However,
some
|               models may have only a subset of these keywords.  For
example,
|               an input structure normally only needs the [Voltage Range],
|               [GND Clamp], and possibly the [POWER Clamp] keywords.  If
one
|               or more of [Rgnd], [Rpower], [Rac], and [Cac] keywords are
|               used, then the Model_type must be Terminator.
|---------------------------------------------------------------------------
- --
| Signals       CLK1, CLK2,...         | Optional signal list, if desired
[Model]         Clockbuffer
Model_type      I/O
Polarity        Non-Inverting
Enable          Active-High
Vinl = 0.8V                            | input logic "low" DC voltage, if
any
Vinh = 2.0V                            | input logic "high" DC voltage, if
any
Vmeas = 1.5V              | Reference voltage for timing measurements
Cref = 50pF               | Timing specification test load capacitance value
Rref = 500                | Timing specification test load resistance value
Vref = 0                  | Timing specification test load voltage
| variable      typ             min             max
C_comp          12.0pF          10.0pF          15.0pF
|
|===========================================================================
==
|
[Model]         Clockbuffer
Model_type      I/O
Vinl = 0.8V                            | input logic "low" DC voltage, if
any
Vinh = 2.0V                            | input logic "high" DC voltage, if
any
|
| variable      typ             min             max
C_comp_pullup   3.0pF           2.5pF           3.5pF
C_comp_pulldown 2.0pF           1.5pF           2.5pF
C_comp_power    1.0pF           0.5pF           1.5pF
C_comp_gnd      1.0pF           0.5pF           1.5pF
|

The last paragraph of the Usage Rules section of the [Rising Waveform], 
[Falling Waveform] keyword description is changed as follows:

|               All tables assume that the die capacitance is included.
|               Potential numerical problems associated with processing the
|*              data using the effective C_comp (C_comp or C_comp* as
|*              appropriate) for effective die capacitance may be handled
|*              differently among simulators.

****************************************************************************
**

ANALYSIS PATH/DATA THAT LED TO SPECIFICATION:

Needed information on where the distributed capacitance went, thus the
addition
of a paragraph to explain this.  

Also, the names of two of the original subparameters, "C_comp_power" and 
"C_comp_gnd", were changed to "C_comp_power_clamp" and "C_comp_gnd_clamp"
respectivly to better reflect their purpose.  Some minor wording changes
to the current draft text were also done.

Finally, updated a bit of text in the waveform keywords, per John Angulo's
sugestion.

****************************************************************************
**

ANY OTHER BACKGROUND INFORMATION:

****************************************************************************
**
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------------------------------

Date: Fri, 28 Jun 2002 17:43:26 -0500
From: John Phillippe <[email-masked]>
Subject: Re: [IBIS-Users] Rising/Falling Waveform generation

Scott McMorrow wrote:
> 
> John,
> 
> My guess is there is something wrong with your simulation deck setup.
>  Rfixture and Vfixture is simple load placed on the output of your
> buffer during VT table extraction.  It is no different than setting up
> your spice deck by hand, attaching a pulse source to the input of the
> buffer and a resistive load to the output of the buffer and simulating.
>  If your buffer is capable of driving a 50 ohm load, then there should
> not be a problem with spice2ibis.  If there is, it would be generally a
> setup or connectivity problem.
> 
> An Rfixture of 100K would be useless to an ibis simulator, since the
> simulator will attempt to scale the rising and falling waveforms to the
> actual load impedance of 50 to 75 ohms in system.  This scaling would
> cause significant waveform errors.
> 
> My suggestion is to setup the buffer independently of spice2ibis and
> verify that it actually is capable of driving a standard load.  If it
> is, then you have an issue with the connections  in the decks used for
> ibis extraction.
> 
> Regards,
> 
> Scott
> 
> John Phillippe wrote:
> 
> >Dear Everyone,
> >  I can't seem to generate decent rising and falling waveforms in IBIS.
> >After looking at the generated spice files, I found that the problem was
> >with the Rfixture and Vfixture.  I found that if I didn't use a test
> >fixture of any kind, then the waveforms came out correct.  However I had
> >to manually generate them.  So I went back and tried monkeying with the
> >Rfixture values, and found that a 100K resistor seems to allow IBIS to
> >generate a good waveform.
> >  I've never used an IBIS model in a simulation environment before, and
> >so I guess my question is regarding the Rfixture, and what it is used
> >for.  Could I manually generate my edges and then specify an Rfixture of
> >0 ohms in the ibis file?  Is having an Rfixture of 100k going to cause
> >any problems for the end users?

Scott,
  When I setup the rising/falling test with a 50ohm load, and let s2ibis
do it's runs, I get corresponding rising and falling waveforms, my
problems lie in the fact that my waveforms never go from gnd to Vdd. 
The following 4 lines are taken from one of my .s2i files.

[Rising waveform] 50 5.0 4.75 5.25 NA 50pF 233.0m 9.35nH 0.87pF
[Falling waveform] 50 5.0 4.75 5.25 NA 50pF 233.0m 9.35nH 0.87pF
[Rising waveform] 50 0 NA NA NA 50pF 233.0m 9.35nH 0.87pF
[Falling waveform] 50 0 NA NA NA 50pF 233.0m 9.35nH 0.87pF

When looking at the results, the rising and falling waveforms with a
Vfixture of 5V, have a rising waveform starting at a value above 0V, and
ending at 5V. The falling waveform starts at 5V, and ends above 0V.  The
waveforms with a Vfixture of 0V have a bottom of 0V, but a ceiling of
less than 5V.  It doesn't "seem right."  If this is how it should be
however, someone please let me know!  I would expect voltage range of
between 0V and 5V. Thanks.

- -- 
John Phillippe
SPS, 32 Bit Embedded Controller Division, IC Creation
Motorola      -  512-895-1835
Austin, TX    -  [email-masked]
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|with just the appropriate command message(s) in the body:
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|
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|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Fri, 28 Jun 2002 17:21:11 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] BIRD 76 - Additional Information Related to C_comp Refinements

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_000_01C21F02.DF568460
Content-Type: text/plain;
	charset="iso-8859-1"

(Resending with the correct subject line and as an attachement to eliminate
line wraps
  Appologies,
  Stephen)

Greetings:

  During the editorial review of IBIS 4.0 several issues were noted with
text added by BIRD65, C_comp Refinements.  The following BIRD is intended to
address these issues.  While no technical changes were made, and the intent
of  BIRD65 remains the same, the text changes were extensive enough to
warrant official documentation as a BIRD.

BIRD76 is scheduled for discussion and vote at the June 19, 2002
teleconference, and will proceed any vote on the IBIS 4.0 specification
itself.  

If you have any comments on this bird please you are encouraged to post them
to the IBIS reflector for discussion.

  Regards,
  Stephen Peters
  Intel Corp.
  Chair EIA/IBIS Open Forum

 <<bird76.ZIP>> 

- ------_=_NextPart_000_01C21F02.DF568460
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|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
|
|  help
|  subscribe   ibis       <optional e-mail address, if different>
|  subscribe   ibis-users <optional e-mail address, if different>
|  unsubscribe ibis       <optional e-mail address, if different>
|  unsubscribe ibis-users <optional e-mail address, if different>
|
|or email a written request to [email-masked].
|
|IBIS reflector archives exist under:
|
|  http://www.eda.org/pub/ibis/email_archive/  Recent
|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

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