Subject: ibis-users V1 #8
From: owner-ibis-users@ (ibis-users)
To: [email-masked]

ibis-users         Wednesday, August 14 2002         Volume 01 : Number 008

----------------------------------------------------------------------

Date: Wed, 24 Jul 2002 00:47:22 -0700
From: Shee Kian Wong <[email-masked]>
Subject: [IBIS-Users] IBIS Specification Question

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Hi all,

I'm currently studying the IBIS Specification. I have some ambiguities about
the I/O Buffer Modeling Cookbook prepared by IBIS Forum. 

A typical simulation setup for an output or I/O buffer is given in Page 8 of
the Cookbook, as shown below: 

 

I understand that for an I/O (3-stateable) buffer four sets of I/V curves
are required; one with the pulldown transistor turned on (output in the low
state) (pulldown curve), one with the pullup transistor turned on (output in
the high state) (pullup curve), and two with the output in a high impedance
state (power clamp and ground clamp curves).  

For example, when we want to enable the pullup transistor, we would supply
ENABLE pin with vcc (logic 1) and INPUT pin with 0 (logic 0). However, when
the voltage source sweeps in the range of -vcc to 0, the NMOS will be turned
on as well. This is due to the fact that Vpad is smaller than Vgnd, then the
drain of the NMOS would be at the ground side. Since Vgs>0 (G=Logic 0,
S<logic 0), the NMOS is turned on.

Therefore, some ground clamp currents flow through the pulldown transistor.
Why the equation Vpullup(table) = Vpullup - Vpower_clamp does not take care
of the ground clamp current? Also, some current will flow through the pullup
transistor during this voltage sweep range, do we call it pullup current or
ground clamp current?

When the voltage source sweeps from vcc to 2*vcc, again, some current flow
through the pullup transistor. Do we call this current pullup current or
power clamp current?

The same thing occurs to pulldown I/V case.

There are no ambiguities for power clamp and ground clamp curves.

Please kind advice and correct me if I'm wrong.

 

Much appreciated,

Shee Kian Wong

Applications Engineer

Altera Corporation (M) S/B

 

 

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<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Hi all,</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>I'm currently studying the IBIS Specification. I have
some ambiguities about the I/O Buffer Modeling Cookbook prepared by IBIS Forum.
</span></font></p>

<p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:
12.0pt'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>A typical simulation setup for an output or I/O buffer is
given in Page 8 of the Cookbook, as shown below: </span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'><img width=624 height=359
src="cid:[email-masked]"></span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>I understand that for an I/O (3-stateable) buffer four sets
of I/V curves are required; one with the pulldown transistor turned on (output
in the low state) (pulldown curve), one with the pullup transistor turned on
(output in the high state) (pullup curve), and two with the output in a high
impedance state (power clamp and ground clamp curves).&nbsp; </span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>For example, when we want to enable the pullup transistor,
we would supply ENABLE pin with vcc (logic 1) and INPUT pin with 0 (logic 0).
However, when the voltage source sweeps in the range of -vcc to 0, the
NMOS will be turned on as well. This is due to the fact that Vpad is smaller
than Vgnd, then the drain of the NMOS would be at the ground side. Since Vgs&gt;0
(G=Logic 0, S&lt;logic 0), the NMOS is turned on.</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Therefore, some ground clamp currents flow through the pulldown
transistor. Why the equation Vpullup(table) = Vpullup - Vpower_clamp does
not take care of the ground clamp current? Also, some current will flow through
the pullup transistor during this voltage sweep range, do we call it pullup
current or ground clamp current?</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>When the voltage source sweeps from vcc to 2*vcc, again,
some current flow through the pullup transistor. Do we call this current pullup
current or power clamp current?</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>The same thing occurs to pulldown I/V case.</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>There are no ambiguities for power clamp and ground clamp
curves.</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Please kind advice and correct me if I'm wrong.</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Much appreciated,</span></font></p>

<p class=MsoNormal><font size=1 face=Arial><span style='font-size:7.5pt;
font-family:Arial'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Shee Kian Wong</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Applications Engineer</span></font></p>

<p class=MsoNormal><font size=2 face=Arial><span style='font-size:10.0pt;
font-family:Arial'>Altera Corporation (M) S/B</span></font></p>

<p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:
12.0pt'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=3 face="Times New Roman">&nbsp;</font></p>

<br clear=ALL>

<p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:
12.0pt'>&nbsp;</span></font></p>

<p class=MsoNormal><font size=3 face="Times New Roman"><span style='font-size:
12.0pt'>&nbsp;</span></font></p>

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Date: Wed, 24 Jul 2002 08:40:40 -0500
From: [email-masked]
Subject: RE: [IBIS-Users] IBIS Specification Question

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For what it's worth, I've seen some IBIS models contain both power clamp and
and pull up data in the pull up curve.  I would think that this would
accurately represent the superposition of the two.  If you want to separate
the two, I would think that the power clamp should include only the effects
of the diode, and the pull up should contain only the effects of the
transistor.
 
Hope this helps,
JR

- -----Original Message-----
From: Shee Kian Wong [mailto:[email-masked]]
Sent: Wednesday, July 24, 2002 2:47 AM
To: [email-masked]
Subject: [IBIS-Users] IBIS Specification Question

Hi all,

I'm currently studying the IBIS Specification. I have some ambiguities about
the I/O Buffer Modeling Cookbook prepared by IBIS Forum. 

A typical simulation setup for an output or I/O buffer is given in Page 8 of
the Cookbook, as shown below: 

 

I understand that for an I/O (3-stateable) buffer four sets of I/V curves
are required; one with the pulldown transistor turned on (output in the low
state) (pulldown curve), one with the pullup transistor turned on (output in
the high state) (pullup curve), and two with the output in a high impedance
state (power clamp and ground clamp curves).  

For example, when we want to enable the pullup transistor, we would supply
ENABLE pin with vcc (logic 1) and INPUT pin with 0 (logic 0). However, when
the voltage source sweeps in the range of -vcc to 0, the NMOS will be turned
on as well. This is due to the fact that Vpad is smaller than Vgnd, then the
drain of the NMOS would be at the ground side. Since Vgs>0 (G=Logic 0,
S<logic 0), the NMOS is turned on.

Therefore, some ground clamp currents flow through the pulldown transistor.
Why the equation Vpullup(table) = Vpullup - Vpower_clamp does not take care
of the ground clamp current? Also, some current will flow through the pullup
transistor during this voltage sweep range, do we call it pullup current or
ground clamp current?

When the voltage source sweeps from vcc to 2*vcc, again, some current flow
through the pullup transistor. Do we call this current pullup current or
power clamp current?

The same thing occurs to pulldown I/V case.

There are no ambiguities for power clamp and ground clamp curves.

Please kind advice and correct me if I'm wrong.

 

Much appreciated,

Shee Kian Wong

Applications Engineer

Altera Corporation (M) S/B

 

 

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<BODY lang=EN-US vLink=purple link=blue>
<DIV><SPAN class=368373213-24072002><FONT face=Arial color=#0000ff size=2>For 
what it's worth, I've seen some IBIS models contain both power clamp and and 
pull up data in the pull up curve.&nbsp; I would think that this would 
accurately represent the superposition of the two.&nbsp; If you want to separate 
the two, I would think that the power clamp should include only the effects of 
the diode, and the pull up should contain only the effects of the 
transistor.</FONT></SPAN></DIV>
<DIV><SPAN class=368373213-24072002><FONT face=Arial color=#0000ff 
size=2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=368373213-24072002><FONT face=Arial color=#0000ff size=2>Hope 
this helps,</FONT></SPAN></DIV>
<DIV><SPAN class=368373213-24072002><FONT face=Arial color=#0000ff 
size=2>JR</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
  <DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma 
  size=2>-----Original Message-----<BR><B>From:</B> Shee Kian Wong 
  [mailto:[email-masked]]<BR><B>Sent:</B> Wednesday, July 24, 2002 2:47 
  AM<BR><B>To:</B> [email-masked]<BR><B>Subject:</B> [IBIS-Users] IBIS 
  Specification Question<BR><BR></FONT></DIV>
  <DIV class=Section1>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">Hi all,</SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">I'm currently studying the IBIS 
  Specification. I have some ambiguities about the I/O Buffer Modeling Cookbook 
  prepared by IBIS Forum. </SPAN></FONT></P>
  <P class=MsoNormal><FONT face="Times New Roman" size=3><SPAN 
  style="FONT-SIZE: 12pt"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">A typical simulation setup for an 
  output or I/O buffer is given in Page 8 of the Cookbook, as shown below: 
  </SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial"><IMG height=359 
  src="cid:368373213@24072002-0007" width=624></SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">I understand that for an I/O 
  (3-stateable) buffer four sets of I/V curves are required; one with the 
  pulldown transistor turned on (output in the low state) (pulldown curve), one 
  with the pullup transistor turned on (output in the high state) (pullup 
  curve), and two with the output in a high impedance state (power clamp and 
  ground clamp curves).&nbsp; </SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">For example, when we want to 
  enable the pullup transistor, we would supply ENABLE pin with vcc (logic 1) 
  and INPUT pin with 0 (logic 0). However, when the voltage source sweeps in the 
  range of -vcc to 0, the NMOS will be turned on as well. This is due to the 
  fact that Vpad is smaller than Vgnd, then the drain of the NMOS would be at 
  the ground side. Since Vgs&gt;0 (G=Logic 0, S&lt;logic 0), the NMOS is turned 
  on.</SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">Therefore, some ground clamp 
  currents flow through the pulldown transistor. Why the equation Vpullup(table) 
  = Vpullup - Vpower_clamp does not take care of the ground clamp current? Also, 
  some current will flow through the pullup transistor during this voltage sweep 
  range, do we call it pullup current or ground clamp current?</SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">When the voltage source sweeps 
  from vcc to 2*vcc, again, some current flow through the pullup transistor. Do 
  we call this current pullup current or power clamp current?</SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">The same thing occurs to pulldown 
  I/V case.</SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">There are no ambiguities for power 
  clamp and ground clamp curves.</SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">Please kind advice and correct me 
  if I'm wrong.</SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">Much 
appreciated,</SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=1><SPAN 
  style="FONT-SIZE: 7.5pt; FONT-FAMILY: Arial"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">Shee Kian Wong</SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">Applications 
  Engineer</SPAN></FONT></P>
  <P class=MsoNormal><FONT face=Arial size=2><SPAN 
  style="FONT-SIZE: 10pt; FONT-FAMILY: Arial">Altera Corporation (M) 
  S/B</SPAN></FONT></P>
  <P class=MsoNormal><FONT face="Times New Roman" size=3><SPAN 
  style="FONT-SIZE: 12pt"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face="Times New Roman" size=3></FONT>&nbsp;</P><BR 
  clear=all>
  <P class=MsoNormal><FONT face="Times New Roman" size=3><SPAN 
  style="FONT-SIZE: 12pt"></SPAN></FONT>&nbsp;</P>
  <P class=MsoNormal><FONT face="Times New Roman" size=3><SPAN 
  style="FONT-SIZE: 12pt"></SPAN></FONT>&nbsp;</P></DIV></BLOCKQUOTE></BODY></HTML>

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------------------------------

Date: Thu, 25 Jul 2002 17:10:17 +0200
From: [email-masked]
Subject: RE: [IBIS-Users] LVDS RECEIVER TERMINATION Question

Hello All,

R Series appears to be not supported  by the Ibis simulators, which is a shame, since it has been prepared so well in Ibis 3.2

What do you think about the following approach:
Use a resistor of Rdiff/2 to a fixed point at the level of the desired common mode voltage.
This could be achieved by using the model Terminator and using Rgnd and Rpower.

Looking forward to your reactions,

Rob
__________________________________________________________________________
Rob Mataheroe                                                                                           Philips Semiconductors bv
P.G. Logic Product Group PD&S                                                           Building AM1.108
Senior Design Modeling Engineer                                                       Gerstweg 2
Tel. ++31 (0)24 353 2370                                                                           6534 AE Nijmegen
Fax. ++31 (0)24 353 2820                                                                          The Netherlands
Email: [email-masked]
Seri: matahero@nyhp04

                                                                                                                                              
                      "Hegazy, Hazem"                                                                                                         
                      <hazem_hegazy@mentor             To:  "'Peter LaFlamme '" <[email-masked]>                                           
                      g.com>                            "'Hassan Ali '" <[email-masked]>                                                 
                      Sent by:                         cc:  "[email-masked] '" <[email-masked]>                        
                      owner-ibis-users@ser              (bcc: Rob Mataheroe/NYM/SC/PHILIPS)                                                   
                      ver.eda.org                      Subject:   RE: [IBIS-Users] LVDS RECEIVER TERMINATION Question                         
                                                                                                                                              
                                                       Classification:                                                                        
                      07/23/02 11:01 PM                                                                                                       

 Hi,
I've a solution...I didn't test it yet but, I suggest that based on an old solution of mine for 100 terminated LVDS DRIVERS in IBIS summit Jan 2001 "hegazy.pdf or zip on IBIS home page".

In the driver case, I consider the internal termination as a part of the buffer itself, I could not take it away "In some cases we can" so, I want to get the I-V characteristics based on this.

What are the I-V characteristics? Simply, it's the steady state solution of the voltage and current at all possible loads.

So, I put a resistor between P node and N node and measure "steady state voltage and current" now, vary the resistor value from zero to infinity (open circuit) and do the same extraction to complete your I-V table. You will have the actual behavior of the
buffer (Interactive) on all possible loading conditions. This is verified  with a lot of LVDS buffers for very famous customer.

For the receiver we can't do that as there is no source of current like in the driver case to measure the I and V.
So, my suggestion is to put a voltage source between the p and n nodes (differential voltage source). Vary the voltage source value in normal DC analysis and measure the P voltage with the current through the voltage source to form the I-V table with the
interaction of the n node inherited inside it.

I'll try this solution with some validation and keep you all informed.
I might have goofed!!

BR,

- -----Original Message-----
From: Peter LaFlamme
To: Hassan Ali
Cc: [email-masked]
Sent: 7/23/02 6:52 PM
Subject: Re: [IBIS-Users] LVDS RECEIVER TERMINATION Question

Hi Hassan,
Thanks alot for the comments and information. I have done the same thing
previously in simulations. I have also received input models that had
the internal termination modeled as a dynamic clamp. In comparisons
between dynamic clamp modeled terminations
and your method, I found that (just in my case) there was not real good
correlation.

Regards,
Peter

Peter LaFlamme

Applied Micro Circuits Corp.
System Applications Engineer
200 Minuteman Rd, 3rd Floor
Andover, MA 01810

978-247-8470 phone
978-623-0055 Fax

Hassan Ali wrote:
>
> Hi Peter,
>
> I had the same situation a few months ago and I only had to go with an
> adhoc solution.
>
> Yes indeed most simulators do not have good support for differential
> models with [R Series] termination. I ended up creating a single-ended
> input buffer model (same for the P and N side) with no termination
> between P and N sides. This only captured the clamping function.
>
> In my simulation I had to recreate the terminated differential input
> buffer by using two single-ended buffers (one for the P and one for
the
> N pin) with a termination resistor tied between them. The package
> parasitics were also tied to the two pins. I manually changed the
values
> of the termination resistor and package parasitics to cover their
> variation in the typical, minimum and maximum corners.
>
> Probably there is a better solution, but that's what I did as a
> quick-and-dirty work-around.
>
> Regards.
>
> Hassan.
>
> Hassan Ali, Ph.D.
> Signal Integrity Specialist   -Talented, innovative designers
> Fidus Systems Inc.               -Highly competitive rates
> Tel: (613) 828-0063 Ext.342   -Fixed-price business model
> Fax: (613) 828-3113              -State-of-the-art design tools
> http://www.fidus.ca                -Customer-friendly attitude
>
> -----Original Message-----
> From: Peter LaFlamme [mailto:[email-masked]]
> Sent: Tuesday, July 23, 2002 9:01 AM
> To: [email-masked]
> Subject: [IBIS-Users] LVDS RECEIVER TERMINATION Question
>
> Hi All,
> I am tasked with creating an IBIS model for an LVDS receiver cell that
> has an internal 100 ohm termination between the P and N nodes. I had
> asked Bob Ross about this a while ago and as usual he was very
helpful.
> >From his response I used the following
> implementation:
>
> |****************************************************************
> |                       Component:  LVDSRCV
> |****************************************************************
> |
> [Component]      LVDSRCV
> [Manufacturer]   AMCC
> |
> |
> |
> [Package]
> |  variable       typ          min           max
> R_pkg            1E-3          NA            NA
> L_pkg            1E-9          NA            NA
> C_pkg            1E-12          NA            NA
> |
> [Pin]        signal_name     model_name         R_pin   L_pin   C_pin
>   1             PAD          lvdsrcv            NA      NA      NA
>   2             PADN         lvdsrcv            NA      NA      NA
> |
> [Series Pin Mapping]    pin_2   model_name      function_table_group
> 1                     2           rterm_100
>
> |
> [Diff_pin]      inv_pin     vdiff     tdelay_typ    tdelay_min
> tdelay_max
> |
>    1               2          0.2          0             0
0
>
> [Model]  rterm_100
> C_comp                   0.1pF   0.1pF  0.1pF
>
> Model_type  Series
> |variable        R(typ)  R(min)  R(max)
> [R Series]      100     80      120
>
> [Temperature Range]     25.00    125.00    0.00
> [Voltage Range]         1.800    1.650   1.950
>
>
************************************************************************
> ****************
>
> I was able to get the model past the IBIS checker but my simulations
did
> not show the 100 ohm terminator. I was using a tool which I believe
does
> not support this implementation (no need to mention names). I have
seen
> other implementations where I believe
>
> a "Dynamic clamp" is used to model the termination behavior, but I am
> unsure. Can anyone guide me to some reference material or weigh in
with
> your experience or help.
>
> Thanks alot,
> Peter
>
>
>
> --
> Peter LaFlamme
>
> Applied Micro Circuits Corp.
> System Applications Engineer
> 200 Minuteman Rd, 3rd Floor
> Andover, MA 01810
>
> 978-247-8470 phone
> 978-623-0055 Fax
> |------------------------------------------------------------------
> |For help or to subscribe/unsubscribe, email [email-masked]
> |with just the appropriate command message(s) in the body:
> |
> |  help
> |  subscribe   ibis       <optional e-mail address, if different>
> |  subscribe   ibis-users <optional e-mail address, if different>
> |  unsubscribe ibis       <optional e-mail address, if different>
> |  unsubscribe ibis-users <optional e-mail address, if different>
> |
> |or email a written request to [email-masked].
> |
> |IBIS reflector archives exist under:
> |
> |  http://www.eda.org/pub/ibis/email_archive/  Recent
> |  http://www.eda.org/pub/ibis/users_archive/  Recent
> |  http://www.eda.org/pub/ibis/email/          E-mail since 1993

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|with just the appropriate command message(s) in the body:
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------------------------------

Date: Thu, 25 Jul 2002 21:10:25 +0300
From: "Hegazy, Hazem" <[email-masked]>
Subject: RE: [IBIS-Users] LVDS RECEIVER TERMINATION Question

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C23406.79E9DBA6
Content-Type: text/plain

 Hi,
Yes, it's not supported in SOME simulators but not all.
The Rdiff/2 to certain CM voltage might be a good solution if the common
mode voltage itself doesn't change with different loads. I've seen a lot of
LVDS driver with common mode voltage changes with the differential load
value. I don't see if this applicable in the receiver case or not, I'm just
saying the one should be careful.

BR, 

- -----Original Message-----
From: [email-masked]
To: Hegazy, Hazem
Cc: 'Hassan Ali '; [email-masked] ';
[email-masked]; 'Peter LaFlamme '
Sent: 7/25/02 4:10 PM
Subject: RE: [IBIS-Users] LVDS RECEIVER TERMINATION Question

Hello All,

R Series appears to be not supported  by the Ibis simulators, which is a
shame, since it has been prepared so well in Ibis 3.2

What do you think about the following approach:
Use a resistor of Rdiff/2 to a fixed point at the level of the desired
common mode voltage.
This could be achieved by using the model Terminator and using Rgnd and
Rpower.

Looking forward to your reactions,

Rob
________________________________________________________________________
__
Rob Mataheroe
Philips Semiconductors bv
P.G. Logic Product Group PD&S
Building AM1.108
Senior Design Modeling Engineer
Gerstweg 2
Tel. ++31 (0)24 353 2370
6534 AE Nijmegen
Fax. ++31 (0)24 353 2820
The Netherlands
Email: [email-masked]
Seri: matahero@nyhp04

 

                      "Hegazy, Hazem"

                      <hazem_hegazy@mentor             To:  "'Peter
LaFlamme '" <[email-masked]>

                      g.com>                            "'Hassan Ali '"
<[email-masked]>                                                 
                      Sent by:                         cc:
"[email-masked] '" <[email-masked]>

                      owner-ibis-users@ser              (bcc: Rob
Mataheroe/NYM/SC/PHILIPS)

                      ver.eda.org                      Subject:   RE:
[IBIS-Users] LVDS RECEIVER TERMINATION Question                         

                                                       Classification:

                      07/23/02 11:01 PM

 

 Hi,
I've a solution...I didn't test it yet but, I suggest that based on an
old solution of mine for 100 terminated LVDS DRIVERS in IBIS summit Jan
2001 "hegazy.pdf or zip on IBIS home page".

In the driver case, I consider the internal termination as a part of the
buffer itself, I could not take it away "In some cases we can" so, I
want to get the I-V characteristics based on this.

What are the I-V characteristics? Simply, it's the steady state solution
of the voltage and current at all possible loads.

So, I put a resistor between P node and N node and measure "steady state
voltage and current" now, vary the resistor value from zero to infinity
(open circuit) and do the same extraction to complete your I-V table.
You will have the actual behavior of the
buffer (Interactive) on all possible loading conditions. This is
verified  with a lot of LVDS buffers for very famous customer.

For the receiver we can't do that as there is no source of current like
in the driver case to measure the I and V.
So, my suggestion is to put a voltage source between the p and n nodes
(differential voltage source). Vary the voltage source value in normal
DC analysis and measure the P voltage with the current through the
voltage source to form the I-V table with the
interaction of the n node inherited inside it.

I'll try this solution with some validation and keep you all informed.
I might have goofed!!

BR,

- -----Original Message-----
From: Peter LaFlamme
To: Hassan Ali
Cc: [email-masked]
Sent: 7/23/02 6:52 PM
Subject: Re: [IBIS-Users] LVDS RECEIVER TERMINATION Question

Hi Hassan,
Thanks alot for the comments and information. I have done the same thing
previously in simulations. I have also received input models that had
the internal termination modeled as a dynamic clamp. In comparisons
between dynamic clamp modeled terminations
and your method, I found that (just in my case) there was not real good
correlation.

Regards,
Peter

Peter LaFlamme

Applied Micro Circuits Corp.
System Applications Engineer
200 Minuteman Rd, 3rd Floor
Andover, MA 01810

978-247-8470 phone
978-623-0055 Fax

Hassan Ali wrote:
>
> Hi Peter,
>
> I had the same situation a few months ago and I only had to go with an
> adhoc solution.
>
> Yes indeed most simulators do not have good support for differential
> models with [R Series] termination. I ended up creating a single-ended
> input buffer model (same for the P and N side) with no termination
> between P and N sides. This only captured the clamping function.
>
> In my simulation I had to recreate the terminated differential input
> buffer by using two single-ended buffers (one for the P and one for
the
> N pin) with a termination resistor tied between them. The package
> parasitics were also tied to the two pins. I manually changed the
values
> of the termination resistor and package parasitics to cover their
> variation in the typical, minimum and maximum corners.
>
> Probably there is a better solution, but that's what I did as a
> quick-and-dirty work-around.
>
> Regards.
>
> Hassan.
>
> Hassan Ali, Ph.D.
> Signal Integrity Specialist   -Talented, innovative designers
> Fidus Systems Inc.               -Highly competitive rates
> Tel: (613) 828-0063 Ext.342   -Fixed-price business model
> Fax: (613) 828-3113              -State-of-the-art design tools
> http://www.fidus.ca                -Customer-friendly attitude
>
> -----Original Message-----
> From: Peter LaFlamme [mailto:[email-masked]]
> Sent: Tuesday, July 23, 2002 9:01 AM
> To: [email-masked]
> Subject: [IBIS-Users] LVDS RECEIVER TERMINATION Question
>
> Hi All,
> I am tasked with creating an IBIS model for an LVDS receiver cell that
> has an internal 100 ohm termination between the P and N nodes. I had
> asked Bob Ross about this a while ago and as usual he was very
helpful.
> >From his response I used the following
> implementation:
>
> |****************************************************************
> |                       Component:  LVDSRCV
> |****************************************************************
> |
> [Component]      LVDSRCV
> [Manufacturer]   AMCC
> |
> |
> |
> [Package]
> |  variable       typ          min           max
> R_pkg            1E-3          NA            NA
> L_pkg            1E-9          NA            NA
> C_pkg            1E-12          NA            NA
> |
> [Pin]        signal_name     model_name         R_pin   L_pin   C_pin
>   1             PAD          lvdsrcv            NA      NA      NA
>   2             PADN         lvdsrcv            NA      NA      NA
> |
> [Series Pin Mapping]    pin_2   model_name      function_table_group
> 1                     2           rterm_100
>
> |
> [Diff_pin]      inv_pin     vdiff     tdelay_typ    tdelay_min
> tdelay_max
> |
>    1               2          0.2          0             0
0
>
> [Model]  rterm_100
> C_comp                   0.1pF   0.1pF  0.1pF
>
> Model_type  Series
> |variable        R(typ)  R(min)  R(max)
> [R Series]      100     80      120
>
> [Temperature Range]     25.00    125.00    0.00
> [Voltage Range]         1.800    1.650   1.950
>
>
************************************************************************
> ****************
>
> I was able to get the model past the IBIS checker but my simulations
did
> not show the 100 ohm terminator. I was using a tool which I believe
does
> not support this implementation (no need to mention names). I have
seen
> other implementations where I believe
>
> a "Dynamic clamp" is used to model the termination behavior, but I am
> unsure. Can anyone guide me to some reference material or weigh in
with
> your experience or help.
>
> Thanks alot,
> Peter
>
>
>
> --
> Peter LaFlamme
>
> Applied Micro Circuits Corp.
> System Applications Engineer
> 200 Minuteman Rd, 3rd Floor
> Andover, MA 01810
>
> 978-247-8470 phone
> 978-623-0055 Fax
> |------------------------------------------------------------------
> |For help or to subscribe/unsubscribe, email [email-masked]
> |with just the appropriate command message(s) in the body:
> |
> |  help
> |  subscribe   ibis       <optional e-mail address, if different>
> |  subscribe   ibis-users <optional e-mail address, if different>
> |  unsubscribe ibis       <optional e-mail address, if different>
> |  unsubscribe ibis-users <optional e-mail address, if different>
> |
> |or email a written request to [email-masked].
> |
> |IBIS reflector archives exist under:
> |
> |  http://www.eda.org/pub/ibis/email_archive/  Recent
> |  http://www.eda.org/pub/ibis/users_archive/  Recent
> |  http://www.eda.org/pub/ibis/email/          E-mail since 1993

- --

|------------------------------------------------------------------
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|with just the appropriate command message(s) in the body:
|
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|  subscribe   ibis       <optional e-mail address, if different>
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|  unsubscribe ibis-users <optional e-mail address, if different>
|
|or email a written request to [email-masked].
|
|IBIS reflector archives exist under:
|
|  http://www.eda.org/pub/ibis/email_archive/  Recent
|  http://www.eda.org/pub/ibis/users_archive/  Recent
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5.5.2655.35">
<TITLE>RE: [IBIS-Users] LVDS RECEIVER TERMINATION Question</TITLE>
</HEAD>
<BODY>

<P><FONT SIZE=3D2>&nbsp;Hi,</FONT>
<BR><FONT SIZE=3D2>Yes, it's not supported in SOME simulators but not =
all.</FONT>
<BR><FONT SIZE=3D2>The Rdiff/2 to certain CM voltage might be a good =
solution if the common mode voltage itself doesn't change with =
different loads. I've seen a lot of LVDS driver with common mode =
voltage changes with the differential load value. I don't see if this =
applicable in the receiver case or not, I'm just saying the one should =
be careful.</FONT></P>

<P><FONT SIZE=3D2>BR, </FONT>
</P>
<BR>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: [email-masked]</FONT>
<BR><FONT SIZE=3D2>To: Hegazy, Hazem</FONT>
<BR><FONT SIZE=3D2>Cc: 'Hassan Ali '; [email-masked] '; =
[email-masked]; 'Peter LaFlamme '</FONT>
<BR><FONT SIZE=3D2>Sent: 7/25/02 4:10 PM</FONT>
<BR><FONT SIZE=3D2>Subject: RE: [IBIS-Users] LVDS RECEIVER TERMINATION =
Question</FONT>
</P>

<P><FONT SIZE=3D2>Hello All,</FONT>
</P>

<P><FONT SIZE=3D2>R Series appears to be not supported&nbsp; by the =
Ibis simulators, which is a</FONT>
<BR><FONT SIZE=3D2>shame, since it has been prepared so well in Ibis =
3.2</FONT>
</P>

<P><FONT SIZE=3D2>What do you think about the following =
approach:</FONT>
<BR><FONT SIZE=3D2>Use a resistor of Rdiff/2 to a fixed point at the =
level of the desired</FONT>
<BR><FONT SIZE=3D2>common mode voltage.</FONT>
<BR><FONT SIZE=3D2>This could be achieved by using the model Terminator =
and using Rgnd and</FONT>
<BR><FONT SIZE=3D2>Rpower.</FONT>
</P>

<P><FONT SIZE=3D2>Looking forward to your reactions,</FONT>
</P>

<P><FONT SIZE=3D2>Rob</FONT>
<BR><FONT =
SIZE=3D2>_______________________________________________________________=
_________</FONT>
<BR><FONT SIZE=3D2>__</FONT>
<BR><FONT SIZE=3D2>Rob Mataheroe</FONT>
<BR><FONT SIZE=3D2>Philips Semiconductors bv</FONT>
<BR><FONT SIZE=3D2>P.G. Logic Product Group PD&amp;S</FONT>
<BR><FONT SIZE=3D2>Building AM1.108</FONT>
<BR><FONT SIZE=3D2>Senior Design Modeling Engineer</FONT>
<BR><FONT SIZE=3D2>Gerstweg 2</FONT>
<BR><FONT SIZE=3D2>Tel. ++31 (0)24 353 2370</FONT>
<BR><FONT SIZE=3D2>6534 AE Nijmegen</FONT>
<BR><FONT SIZE=3D2>Fax. ++31 (0)24 353 2820</FONT>
<BR><FONT SIZE=3D2>The Netherlands</FONT>
<BR><FONT SIZE=3D2>Email: [email-masked]</FONT>
<BR><FONT SIZE=3D2>Seri: matahero@nyhp04</FONT>
</P>
<BR>
<BR>
<BR>
<BR>
<BR>

<P><FONT SIZE=3D2>&nbsp;</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
&quot;Hegazy, Hazem&quot;</FONT>
</P>

<P><FONT =
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&lt;hazem_hegazy@mentor&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp; To:&nbsp; &quot;'Peter</FONT>
<BR><FONT SIZE=3D2>LaFlamme '&quot; &lt;[email-masked]&gt;</FONT>
</P>

<P><FONT =
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sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; &quot;'Hassan Ali '&quot;</FONT>
<BR><FONT =
SIZE=3D2>&lt;[email-masked]&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
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p;&nbsp;&nbsp;&nbsp;&nbsp; (bcc: Rob</FONT>
<BR><FONT SIZE=3D2>Mataheroe/NYM/SC/PHILIPS)</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
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ver.eda.org&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Subject:&nbsp;&nbsp; RE:</FONT>
<BR><FONT SIZE=3D2>[IBIS-Users] LVDS RECEIVER TERMINATION =
Question&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp; </FONT>
<BR><FONT SIZE=3D2>&nbsp;</FONT>
</P>

<P><FONT =
SIZE=3D2>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
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<P><FONT =
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sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
07/23/02 11:01 PM</FONT>
</P>

<P><FONT SIZE=3D2>&nbsp;</FONT>
</P>

<P><FONT SIZE=3D2>&nbsp;</FONT>
</P>
<BR>
<BR>
<BR>
<BR>

<P><FONT SIZE=3D2>&nbsp;Hi,</FONT>
<BR><FONT SIZE=3D2>I've a solution...I didn't test it yet but, I =
suggest that based on an</FONT>
<BR><FONT SIZE=3D2>old solution of mine for 100 terminated LVDS DRIVERS =
in IBIS summit Jan</FONT>
<BR><FONT SIZE=3D2>2001 &quot;hegazy.pdf or zip on IBIS home =
page&quot;.</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>In the driver case, I consider the internal =
termination as a part of the</FONT>
<BR><FONT SIZE=3D2>buffer itself, I could not take it away &quot;In =
some cases we can&quot; so, I</FONT>
<BR><FONT SIZE=3D2>want to get the I-V characteristics based on =
this.</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>What are the I-V characteristics? Simply, it's the =
steady state solution</FONT>
<BR><FONT SIZE=3D2>of the voltage and current at all possible =
loads.</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>So, I put a resistor between P node and N node and =
measure &quot;steady state</FONT>
<BR><FONT SIZE=3D2>voltage and current&quot; now, vary the resistor =
value from zero to infinity</FONT>
<BR><FONT SIZE=3D2>(open circuit) and do the same extraction to =
complete your I-V table.</FONT>
<BR><FONT SIZE=3D2>You will have the actual behavior of the</FONT>
<BR><FONT SIZE=3D2>buffer (Interactive) on all possible loading =
conditions. This is</FONT>
<BR><FONT SIZE=3D2>verified&nbsp; with a lot of LVDS buffers for very =
famous customer.</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>For the receiver we can't do that as there is no =
source of current like</FONT>
<BR><FONT SIZE=3D2>in the driver case to measure the I and V.</FONT>
<BR><FONT SIZE=3D2>So, my suggestion is to put a voltage source between =
the p and n nodes</FONT>
<BR><FONT SIZE=3D2>(differential voltage source). Vary the voltage =
source value in normal</FONT>
<BR><FONT SIZE=3D2>DC analysis and measure the P voltage with the =
current through the</FONT>
<BR><FONT SIZE=3D2>voltage source to form the I-V table with the</FONT>
<BR><FONT SIZE=3D2>interaction of the n node inherited inside =
it.</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>I'll try this solution with some validation and keep =
you all informed.</FONT>
<BR><FONT SIZE=3D2>I might have goofed!!</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>BR,</FONT>
</P>
<BR>
<BR>
<BR>
<BR>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Peter LaFlamme</FONT>
<BR><FONT SIZE=3D2>To: Hassan Ali</FONT>
<BR><FONT SIZE=3D2>Cc: [email-masked]</FONT>
<BR><FONT SIZE=3D2>Sent: 7/23/02 6:52 PM</FONT>
<BR><FONT SIZE=3D2>Subject: Re: [IBIS-Users] LVDS RECEIVER TERMINATION =
Question</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Hi Hassan,</FONT>
<BR><FONT SIZE=3D2>Thanks alot for the comments and information. I have =
done the same thing</FONT>
<BR><FONT SIZE=3D2>previously in simulations. I have also received =
input models that had</FONT>
<BR><FONT SIZE=3D2>the internal termination modeled as a dynamic clamp. =
In comparisons</FONT>
<BR><FONT SIZE=3D2>between dynamic clamp modeled terminations</FONT>
<BR><FONT SIZE=3D2>and your method, I found that (just in my case) =
there was not real good</FONT>
<BR><FONT SIZE=3D2>correlation.</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Regards,</FONT>
<BR><FONT SIZE=3D2>Peter</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Peter LaFlamme</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>Applied Micro Circuits Corp.</FONT>
<BR><FONT SIZE=3D2>System Applications Engineer</FONT>
<BR><FONT SIZE=3D2>200 Minuteman Rd, 3rd Floor</FONT>
<BR><FONT SIZE=3D2>Andover, MA 01810</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>978-247-8470 phone</FONT>
<BR><FONT SIZE=3D2>978-623-0055 Fax</FONT>
</P>
<BR>
<BR>
<BR>
<BR>

<P><FONT SIZE=3D2>Hassan Ali wrote:</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; Hi Peter,</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; I had the same situation a few months ago and I =
only had to go with an</FONT>
<BR><FONT SIZE=3D2>&gt; adhoc solution.</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; Yes indeed most simulators do not have good =
support for differential</FONT>
<BR><FONT SIZE=3D2>&gt; models with [R Series] termination. I ended up =
creating a single-ended</FONT>
<BR><FONT SIZE=3D2>&gt; input buffer model (same for the P and N side) =
with no termination</FONT>
<BR><FONT SIZE=3D2>&gt; between P and N sides. This only captured the =
clamping function.</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; In my simulation I had to recreate the =
terminated differential input</FONT>
<BR><FONT SIZE=3D2>&gt; buffer by using two single-ended buffers (one =
for the P and one for</FONT>
<BR><FONT SIZE=3D2>the</FONT>
<BR><FONT SIZE=3D2>&gt; N pin) with a termination resistor tied between =
them. The package</FONT>
<BR><FONT SIZE=3D2>&gt; parasitics were also tied to the two pins. I =
manually changed the</FONT>
<BR><FONT SIZE=3D2>values</FONT>
<BR><FONT SIZE=3D2>&gt; of the termination resistor and package =
parasitics to cover their</FONT>
<BR><FONT SIZE=3D2>&gt; variation in the typical, minimum and maximum =
corners.</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; Probably there is a better solution, but that's =
what I did as a</FONT>
<BR><FONT SIZE=3D2>&gt; quick-and-dirty work-around.</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; Regards.</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; Hassan.</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; Hassan Ali, Ph.D.</FONT>
<BR><FONT SIZE=3D2>&gt; Signal Integrity Specialist&nbsp;&nbsp; =
- -Talented, innovative designers</FONT>
<BR><FONT SIZE=3D2>&gt; Fidus Systems =
Inc.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp; -Highly competitive rates</FONT>
<BR><FONT SIZE=3D2>&gt; Tel: (613) 828-0063 Ext.342&nbsp;&nbsp; =
- -Fixed-price business model</FONT>
<BR><FONT SIZE=3D2>&gt; Fax: (613) =
828-3113&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp; -State-of-the-art design tools</FONT>
<BR><FONT SIZE=3D2>&gt; <A HREF=3D"http://www.fidus.ca" =
TARGET=3D"_blank">http://www.fidus.ca</A>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
- -Customer-friendly attitude</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; -----Original Message-----</FONT>
<BR><FONT SIZE=3D2>&gt; From: Peter LaFlamme [<A =
HREF=3D"mailto:[email-masked]">mailto:[email-masked]</A>]</FONT>
<BR><FONT SIZE=3D2>&gt; Sent: Tuesday, July 23, 2002 9:01 AM</FONT>
<BR><FONT SIZE=3D2>&gt; To: [email-masked]</FONT>
<BR><FONT SIZE=3D2>&gt; Subject: [IBIS-Users] LVDS RECEIVER TERMINATION =
Question</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; Hi All,</FONT>
<BR><FONT SIZE=3D2>&gt; I am tasked with creating an IBIS model for an =
LVDS receiver cell that</FONT>
<BR><FONT SIZE=3D2>&gt; has an internal 100 ohm termination between the =
P and N nodes. I had</FONT>
<BR><FONT SIZE=3D2>&gt; asked Bob Ross about this a while ago and as =
usual he was very</FONT>
<BR><FONT SIZE=3D2>helpful.</FONT>
<BR><FONT SIZE=3D2>&gt; &gt;From his response I used the =
following</FONT>
<BR><FONT SIZE=3D2>&gt; implementation:</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; =
|****************************************************************</FONT>=

<BR><FONT SIZE=3D2>&gt; =
|&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Component:&nbsp; LVDSRCV</FONT>
<BR><FONT SIZE=3D2>&gt; =
|****************************************************************</FONT>=

<BR><FONT SIZE=3D2>&gt; |</FONT>
<BR><FONT SIZE=3D2>&gt; [Component]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
LVDSRCV</FONT>
<BR><FONT SIZE=3D2>&gt; [Manufacturer]&nbsp;&nbsp; AMCC</FONT>
<BR><FONT SIZE=3D2>&gt; |</FONT>
<BR><FONT SIZE=3D2>&gt; |</FONT>
<BR><FONT SIZE=3D2>&gt; |</FONT>
<BR><FONT SIZE=3D2>&gt; [Package]</FONT>
<BR><FONT SIZE=3D2>&gt; |&nbsp; =
variable&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
typ&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
min&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
max</FONT>
<BR><FONT SIZE=3D2>&gt; =
R_pkg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
1E-3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA</FONT>
<BR><FONT SIZE=3D2>&gt; =
L_pkg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
1E-9&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA</FONT>
<BR><FONT SIZE=3D2>&gt; =
C_pkg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
1E-12&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA</FONT>
<BR><FONT SIZE=3D2>&gt; |</FONT>
<BR><FONT SIZE=3D2>&gt; [Pin]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
signal_name&nbsp;&nbsp;&nbsp;&nbsp; =
model_name&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
R_pin&nbsp;&nbsp; L_pin&nbsp;&nbsp; C_pin</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp;&nbsp; =
1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; PAD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
lvdsrcv&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp;&nbsp; =
2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; PADN&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
lvdsrcv&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA</FONT>
<BR><FONT SIZE=3D2>&gt; |</FONT>
<BR><FONT SIZE=3D2>&gt; [Series Pin Mapping]&nbsp;&nbsp;&nbsp; =
pin_2&nbsp;&nbsp; model_name&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
function_table_group</FONT>
<BR><FONT SIZE=3D2>&gt; =
1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
rterm_100</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; |</FONT>
<BR><FONT SIZE=3D2>&gt; [Diff_pin]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
inv_pin&nbsp;&nbsp;&nbsp;&nbsp; vdiff&nbsp;&nbsp;&nbsp;&nbsp; =
tdelay_typ&nbsp;&nbsp;&nbsp; tdelay_min</FONT>
<BR><FONT SIZE=3D2>&gt; tdelay_max</FONT>
<BR><FONT SIZE=3D2>&gt; |</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp; =
1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp; 2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
0.2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; 0</FONT>
<BR><FONT SIZE=3D2>0</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; [Model]&nbsp; rterm_100</FONT>
<BR><FONT SIZE=3D2>&gt; =
C_comp&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.1pF&nbsp;&nbsp; =
0.1pF&nbsp; 0.1pF</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; Model_type&nbsp; Series</FONT>
<BR><FONT SIZE=3D2>&gt; =
|variable&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R(typ)&nbsp; =
R(min)&nbsp; R(max)</FONT>
<BR><FONT SIZE=3D2>&gt; [R Series]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
100&nbsp;&nbsp;&nbsp;&nbsp; 80&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 120</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; [Temperature Range]&nbsp;&nbsp;&nbsp;&nbsp; =
25.00&nbsp;&nbsp;&nbsp; 125.00&nbsp;&nbsp;&nbsp; 0.00</FONT>
<BR><FONT SIZE=3D2>&gt; [Voltage =
Range]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
1.800&nbsp;&nbsp;&nbsp; 1.650&nbsp;&nbsp; 1.950</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT =
SIZE=3D2>***************************************************************=
*********</FONT>
<BR><FONT SIZE=3D2>&gt; ****************</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; I was able to get the model past the IBIS =
checker but my simulations</FONT>
<BR><FONT SIZE=3D2>did</FONT>
<BR><FONT SIZE=3D2>&gt; not show the 100 ohm terminator. I was using a =
tool which I believe</FONT>
<BR><FONT SIZE=3D2>does</FONT>
<BR><FONT SIZE=3D2>&gt; not support this implementation (no need to =
mention names). I have</FONT>
<BR><FONT SIZE=3D2>seen</FONT>
<BR><FONT SIZE=3D2>&gt; other implementations where I believe</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; a &quot;Dynamic clamp&quot; is used to model =
the termination behavior, but I am</FONT>
<BR><FONT SIZE=3D2>&gt; unsure. Can anyone guide me to some reference =
material or weigh in</FONT>
<BR><FONT SIZE=3D2>with</FONT>
<BR><FONT SIZE=3D2>&gt; your experience or help.</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; Thanks alot,</FONT>
<BR><FONT SIZE=3D2>&gt; Peter</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; --</FONT>
<BR><FONT SIZE=3D2>&gt; Peter LaFlamme</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; Applied Micro Circuits Corp.</FONT>
<BR><FONT SIZE=3D2>&gt; System Applications Engineer</FONT>
<BR><FONT SIZE=3D2>&gt; 200 Minuteman Rd, 3rd Floor</FONT>
<BR><FONT SIZE=3D2>&gt; Andover, MA 01810</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; 978-247-8470 phone</FONT>
<BR><FONT SIZE=3D2>&gt; 978-623-0055 Fax</FONT>
<BR><FONT SIZE=3D2>&gt; =
|------------------------------------------------------------------</FON=
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------------------------------

Date: Fri, 26 Jul 2002 21:29:10 -0400
From: Kevin Fisher <[email-masked]>
Subject: Re: [IBIS-Users] LVDS RECEIVER TERMINATION Question

All,

One technique we have used for terminated LVDS receivers is to model 
the differential termination behavior in the power clamp and ground 
clamp curves themselves. The setup for this technique is similar to a 
popular technique for LVDS drivers: tie the sweeping DC voltage source 
(v_sweep) to the p-pad, tie a VCVS equal to v_sweep and a gain of -1 on 
the n-pad (v_sweep_bar) and bias both pads at the desired common mode 
voltage.

Modeling termination using this approach can also be applied to 
single-ended receivers that have termination on-die. We have had success 
using IBIS models generated with this technique in various simulators 
because it uses only basic IBIS syntax. As Hazem points out though, IBIS 
models generated for a certain Vcm is limited to nets where the common 
mode voltage doesn't vary from the one used to model the receiver.

We are currently looking into other possible solutions that are portable 
across multiple simulators and don't have the Vcm limitation.

Hope this helps.

- -- 
Kevin M. Fisher
Consultant
Signal Integrity Software Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
Phone: (978) 461-0449, ext 11
http://www.sisoft.com

Hegazy, Hazem wrote:
>  Hi,
> Yes, it's not supported in SOME simulators but not all.
> The Rdiff/2 to certain CM voltage might be a good solution if the common 
> mode voltage itself doesn't change with different loads. I've seen a lot 
> of LVDS driver with common mode voltage changes with the differential 
> load value. I don't see if this applicable in the receiver case or not, 
> I'm just saying the one should be careful.
> 
> BR,
> 
> 
> -----Original Message-----
> From: [email-masked]
> To: Hegazy, Hazem
> Cc: 'Hassan Ali '; [email-masked] '; 
> [email-masked]; 'Peter LaFlamme '
> Sent: 7/25/02 4:10 PM
> Subject: RE: [IBIS-Users] LVDS RECEIVER TERMINATION Question
> 
> Hello All,
> 
> R Series appears to be not supported  by the Ibis simulators, which is a
> shame, since it has been prepared so well in Ibis 3.2
> 
> What do you think about the following approach:
> Use a resistor of Rdiff/2 to a fixed point at the level of the desired
> common mode voltage.
> This could be achieved by using the model Terminator and using Rgnd and
> Rpower.
> 
> Looking forward to your reactions,
> 
> Rob
> ________________________________________________________________________
> __
> Rob Mataheroe
> Philips Semiconductors bv
> P.G. Logic Product Group PD&S
> Building AM1.108
> Senior Design Modeling Engineer
> Gerstweg 2
> Tel. ++31 (0)24 353 2370
> 6534 AE Nijmegen
> Fax. ++31 (0)24 353 2820
> The Netherlands
> Email: [email-masked]
> Seri: matahero@nyhp04
> 
> 
> 
> 
> 
> 
>  
> 
>                       "Hegazy, Hazem"
> 
>                       <hazem_hegazy@mentor             To:  "'Peter
> LaFlamme '" <[email-masked]>
> 
>                       g.com>                            "'Hassan Ali '"
> <[email-masked]>                                                
>                       Sent by:                         cc:
> "[email-masked] '" <[email-masked]>
> 
>                       owner-ibis-users@ser              (bcc: Rob
> Mataheroe/NYM/SC/PHILIPS)
> 
>                       ver.eda.org                      Subject:   RE:
> [IBIS-Users] LVDS RECEIVER TERMINATION Question                        
>  
> 
>                                                        Classification:
> 
>                       07/23/02 11:01 PM
> 
>  
> 
>  
> 
> 
> 
> 
> 
>  Hi,
> I've a solution...I didn't test it yet but, I suggest that based on an
> old solution of mine for 100 terminated LVDS DRIVERS in IBIS summit Jan
> 2001 "hegazy.pdf or zip on IBIS home page".
> 
> 
> In the driver case, I consider the internal termination as a part of the
> buffer itself, I could not take it away "In some cases we can" so, I
> want to get the I-V characteristics based on this.
> 
> 
> What are the I-V characteristics? Simply, it's the steady state solution
> of the voltage and current at all possible loads.
> 
> 
> So, I put a resistor between P node and N node and measure "steady state
> voltage and current" now, vary the resistor value from zero to infinity
> (open circuit) and do the same extraction to complete your I-V table.
> You will have the actual behavior of the
> buffer (Interactive) on all possible loading conditions. This is
> verified  with a lot of LVDS buffers for very famous customer.
> 
> 
> For the receiver we can't do that as there is no source of current like
> in the driver case to measure the I and V.
> So, my suggestion is to put a voltage source between the p and n nodes
> (differential voltage source). Vary the voltage source value in normal
> DC analysis and measure the P voltage with the current through the
> voltage source to form the I-V table with the
> interaction of the n node inherited inside it.
> 
> 
> I'll try this solution with some validation and keep you all informed.
> I might have goofed!!
> 
> 
> BR,
> 
> 
> 
> 
> 
> -----Original Message-----
> From: Peter LaFlamme
> To: Hassan Ali
> Cc: [email-masked]
> Sent: 7/23/02 6:52 PM
> Subject: Re: [IBIS-Users] LVDS RECEIVER TERMINATION Question
> 
> 
> Hi Hassan,
> Thanks alot for the comments and information. I have done the same thing
> previously in simulations. I have also received input models that had
> the internal termination modeled as a dynamic clamp. In comparisons
> between dynamic clamp modeled terminations
> and your method, I found that (just in my case) there was not real good
> correlation.
> 
> 
> Regards,
> Peter
> 
> 
> Peter LaFlamme
> 
> 
> Applied Micro Circuits Corp.
> System Applications Engineer
> 200 Minuteman Rd, 3rd Floor
> Andover, MA 01810
> 
> 
> 978-247-8470 phone
> 978-623-0055 Fax
> 
> 
> 
> 
> 
> Hassan Ali wrote:
>  >
>  > Hi Peter,
>  >
>  > I had the same situation a few months ago and I only had to go with an
>  > adhoc solution.
>  >
>  > Yes indeed most simulators do not have good support for differential
>  > models with [R Series] termination. I ended up creating a single-ended
>  > input buffer model (same for the P and N side) with no termination
>  > between P and N sides. This only captured the clamping function.
>  >
>  > In my simulation I had to recreate the terminated differential input
>  > buffer by using two single-ended buffers (one for the P and one for
> the
>  > N pin) with a termination resistor tied between them. The package
>  > parasitics were also tied to the two pins. I manually changed the
> values
>  > of the termination resistor and package parasitics to cover their
>  > variation in the typical, minimum and maximum corners.
>  >
>  > Probably there is a better solution, but that's what I did as a
>  > quick-and-dirty work-around.
>  >
>  > Regards.
>  >
>  > Hassan.
>  >
>  > Hassan Ali, Ph.D.
>  > Signal Integrity Specialist   -Talented, innovative designers
>  > Fidus Systems Inc.               -Highly competitive rates
>  > Tel: (613) 828-0063 Ext.342   -Fixed-price business model
>  > Fax: (613) 828-3113              -State-of-the-art design tools
>  > http://www.fidus.ca                -Customer-friendly attitude
>  >
>  > -----Original Message-----
>  > From: Peter LaFlamme [mailto:[email-masked]]
>  > Sent: Tuesday, July 23, 2002 9:01 AM
>  > To: [email-masked]
>  > Subject: [IBIS-Users] LVDS RECEIVER TERMINATION Question
>  >
>  > Hi All,
>  > I am tasked with creating an IBIS model for an LVDS receiver cell that
>  > has an internal 100 ohm termination between the P and N nodes. I had
>  > asked Bob Ross about this a while ago and as usual he was very
> helpful.
>  > >From his response I used the following
>  > implementation:
>  >
>  > |****************************************************************
>  > |                       Component:  LVDSRCV
>  > |****************************************************************
>  > |
>  > [Component]      LVDSRCV
>  > [Manufacturer]   AMCC
>  > |
>  > |
>  > |
>  > [Package]
>  > |  variable       typ          min           max
>  > R_pkg            1E-3          NA            NA
>  > L_pkg            1E-9          NA            NA
>  > C_pkg            1E-12          NA            NA
>  > |
>  > [Pin]        signal_name     model_name         R_pin   L_pin   C_pin
>  >   1             PAD          lvdsrcv            NA      NA      NA
>  >   2             PADN         lvdsrcv            NA      NA      NA
>  > |
>  > [Series Pin Mapping]    pin_2   model_name      function_table_group
>  > 1                     2           rterm_100
>  >
>  > |
>  > [Diff_pin]      inv_pin     vdiff     tdelay_typ    tdelay_min
>  > tdelay_max
>  > |
>  >    1               2          0.2          0             0
> 0
>  >
>  > [Model]  rterm_100
>  > C_comp                   0.1pF   0.1pF  0.1pF
>  >
>  > Model_type  Series
>  > |variable        R(typ)  R(min)  R(max)
>  > [R Series]      100     80      120
>  >
>  > [Temperature Range]     25.00    125.00    0.00
>  > [Voltage Range]         1.800    1.650   1.950
>  >
>  >
> ************************************************************************
>  > ****************
>  >
>  > I was able to get the model past the IBIS checker but my simulations
> did
>  > not show the 100 ohm terminator. I was using a tool which I believe
> does
>  > not support this implementation (no need to mention names). I have
> seen
>  > other implementations where I believe
>  >
>  > a "Dynamic clamp" is used to model the termination behavior, but I am
>  > unsure. Can anyone guide me to some reference material or weigh in
> with
>  > your experience or help.
>  >
>  > Thanks alot,
>  > Peter
>  >
>  >
>  >
>  > --
>  > Peter LaFlamme
>  >
>  > Applied Micro Circuits Corp.
>  > System Applications Engineer
>  > 200 Minuteman Rd, 3rd Floor
>  > Andover, MA 01810
>  >
>  > 978-247-8470 phone
>  > 978-623-0055 Fax
>  > |------------------------------------------------------------------
>  > |For help or to subscribe/unsubscribe, email [email-masked]
>  > |with just the appropriate command message(s) in the body:
>  > |
>  > |  help
>  > |  subscribe   ibis       <optional e-mail address, if different>
>  > |  subscribe   ibis-users <optional e-mail address, if different>
>  > |  unsubscribe ibis       <optional e-mail address, if different>
>  > |  unsubscribe ibis-users <optional e-mail address, if different>
>  > |
>  > |or email a written request to [email-masked].
>  > |
>  > |IBIS reflector archives exist under:
>  > |
>  > |  http://www.eda.org/pub/ibis/email_archive/  Recent
>  > |  http://www.eda.org/pub/ibis/users_archive/  Recent
>  > |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
> 
> 
> -- 
> 
> 
> 
> 
> 
> 
> 
> 
> |------------------------------------------------------------------
> |For help or to subscribe/unsubscribe, email [email-masked]
> |with just the appropriate command message(s) in the body:
> |
> |  help
> |  subscribe   ibis       <optional e-mail address, if different>
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> |  unsubscribe ibis       <optional e-mail address, if different>
> |  unsubscribe ibis-users <optional e-mail address, if different>
> |
> |or email a written request to [email-masked].
> |
> |IBIS reflector archives exist under:
> |
> |  http://www.eda.org/pub/ibis/email_archive/  Recent
> |  http://www.eda.org/pub/ibis/users_archive/  Recent
> |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
> 

- -- 
Kevin M. Fisher
Consultant
Signal Integrity Software Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
Phone: (978) 461-0449, ext 11
http://www.sisoft.com

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
|
|  help
|  subscribe   ibis       <optional e-mail address, if different>
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|  unsubscribe ibis       <optional e-mail address, if different>
|  unsubscribe ibis-users <optional e-mail address, if different>
|
|or email a written request to [email-masked].
|
|IBIS reflector archives exist under:
|
|  http://www.eda.org/pub/ibis/email_archive/  Recent
|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Fri, 26 Jul 2002 13:47:35 -0400
From: [email-masked]
Subject: Re: [IBIS-Users] LVDS RECEIVER TERMINATION Question

Thanks Kevin,

Just as I suspected.

Adam

|---------+--------------------------->
|         |           Kevin Fisher    |
|         |           <kfisher@sisoft.|
|         |           com>            |
|         |           Sent by:        |
|         |           owner-ibis-users|
|         |           @eda.org        |
|         |                           |
|         |                           |
|         |           07/26/02 09:29  |
|         |           PM              |
|         |                           |
|---------+--------------------------->
  >-------------------------------------------------------------------------------------------------------------------------------|
  |                                                                                                                               |
  |        To:      "Hegazy, Hazem" <[email-masked]>                                                                    |
  |        cc:      "[email-masked] '" <[email-masked]>, "''Hassan Ali ' '" <[email-masked]>,         |
  |        "[email-masked] ' '" <[email-masked]>, "[email-masked] '"                           |
  |        <[email-masked]>, "''Peter LaFlamme ' '" <[email-masked]>                                                 |
  |        Subject: Re: [IBIS-Users] LVDS RECEIVER TERMINATION Question                                                           |
  >-------------------------------------------------------------------------------------------------------------------------------|

All,

One technique we have used for terminated LVDS receivers is to model
the differential termination behavior in the power clamp and ground
clamp curves themselves. The setup for this technique is similar to a
popular technique for LVDS drivers: tie the sweeping DC voltage source
(v_sweep) to the p-pad, tie a VCVS equal to v_sweep and a gain of -1 on
the n-pad (v_sweep_bar) and bias both pads at the desired common mode
voltage.

Modeling termination using this approach can also be applied to
single-ended receivers that have termination on-die. We have had success
using IBIS models generated with this technique in various simulators
because it uses only basic IBIS syntax. As Hazem points out though, IBIS
models generated for a certain Vcm is limited to nets where the common
mode voltage doesn't vary from the one used to model the receiver.

We are currently looking into other possible solutions that are portable
across multiple simulators and don't have the Vcm limitation.

Hope this helps.

- --
Kevin M. Fisher
Consultant
Signal Integrity Software Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
Phone: (978) 461-0449, ext 11
http://www.sisoft.com

Hegazy, Hazem wrote:
>  Hi,
> Yes, it's not supported in SOME simulators but not all.
> The Rdiff/2 to certain CM voltage might be a good solution if the common
> mode voltage itself doesn't change with different loads. I've seen a lot
> of LVDS driver with common mode voltage changes with the differential
> load value. I don't see if this applicable in the receiver case or not,
> I'm just saying the one should be careful.
>
> BR,
>
>
> -----Original Message-----
> From: [email-masked]
> To: Hegazy, Hazem
> Cc: 'Hassan Ali '; [email-masked] ';
> [email-masked]; 'Peter LaFlamme '
> Sent: 7/25/02 4:10 PM
> Subject: RE: [IBIS-Users] LVDS RECEIVER TERMINATION Question
>
> Hello All,
>
> R Series appears to be not supported  by the Ibis simulators, which is a
> shame, since it has been prepared so well in Ibis 3.2
>
> What do you think about the following approach:
> Use a resistor of Rdiff/2 to a fixed point at the level of the desired
> common mode voltage.
> This could be achieved by using the model Terminator and using Rgnd and
> Rpower.
>
> Looking forward to your reactions,
>
> Rob
> ________________________________________________________________________
> __
> Rob Mataheroe
> Philips Semiconductors bv
> P.G. Logic Product Group PD&S
> Building AM1.108
> Senior Design Modeling Engineer
> Gerstweg 2
> Tel. ++31 (0)24 353 2370
> 6534 AE Nijmegen
> Fax. ++31 (0)24 353 2820
> The Netherlands
> Email: [email-masked]
> Seri: matahero@nyhp04
>
>
>
>
>
>
>
>
>                       "Hegazy, Hazem"
>
>                       <hazem_hegazy@mentor             To:  "'Peter
> LaFlamme '" <[email-masked]>
>
>                       g.com>                            "'Hassan Ali '"
> <[email-masked]>
>                       Sent by:                         cc:
> "[email-masked] '" <[email-masked]>
>
>                       owner-ibis-users@ser              (bcc: Rob
> Mataheroe/NYM/SC/PHILIPS)
>
>                       ver.eda.org                      Subject:   RE:
> [IBIS-Users] LVDS RECEIVER TERMINATION Question
>
>
>                                                        Classification:
>
>                       07/23/02 11:01 PM
>
>
>
>
>
>
>
>
>
>  Hi,
> I've a solution...I didn't test it yet but, I suggest that based on an
> old solution of mine for 100 terminated LVDS DRIVERS in IBIS summit Jan
> 2001 "hegazy.pdf or zip on IBIS home page".
>
>
> In the driver case, I consider the internal termination as a part of the
> buffer itself, I could not take it away "In some cases we can" so, I
> want to get the I-V characteristics based on this.
>
>
> What are the I-V characteristics? Simply, it's the steady state solution
> of the voltage and current at all possible loads.
>
>
> So, I put a resistor between P node and N node and measure "steady state
> voltage and current" now, vary the resistor value from zero to infinity
> (open circuit) and do the same extraction to complete your I-V table.
> You will have the actual behavior of the
> buffer (Interactive) on all possible loading conditions. This is
> verified  with a lot of LVDS buffers for very famous customer.
>
>
> For the receiver we can't do that as there is no source of current like
> in the driver case to measure the I and V.
> So, my suggestion is to put a voltage source between the p and n nodes
> (differential voltage source). Vary the voltage source value in normal
> DC analysis and measure the P voltage with the current through the
> voltage source to form the I-V table with the
> interaction of the n node inherited inside it.
>
>
> I'll try this solution with some validation and keep you all informed.
> I might have goofed!!
>
>
> BR,
>
>
>
>
>
> -----Original Message-----
> From: Peter LaFlamme
> To: Hassan Ali
> Cc: [email-masked]
> Sent: 7/23/02 6:52 PM
> Subject: Re: [IBIS-Users] LVDS RECEIVER TERMINATION Question
>
>
> Hi Hassan,
> Thanks alot for the comments and information. I have done the same thing
> previously in simulations. I have also received input models that had
> the internal termination modeled as a dynamic clamp. In comparisons
> between dynamic clamp modeled terminations
> and your method, I found that (just in my case) there was not real good
> correlation.
>
>
> Regards,
> Peter
>
>
> Peter LaFlamme
>
>
> Applied Micro Circuits Corp.
> System Applications Engineer
> 200 Minuteman Rd, 3rd Floor
> Andover, MA 01810
>
>
> 978-247-8470 phone
> 978-623-0055 Fax
>
>
>
>
>
> Hassan Ali wrote:
>  >
>  > Hi Peter,
>  >
>  > I had the same situation a few months ago and I only had to go with an
>  > adhoc solution.
>  >
>  > Yes indeed most simulators do not have good support for differential
>  > models with [R Series] termination. I ended up creating a single-ended
>  > input buffer model (same for the P and N side) with no termination
>  > between P and N sides. This only captured the clamping function.
>  >
>  > In my simulation I had to recreate the terminated differential input
>  > buffer by using two single-ended buffers (one for the P and one for
> the
>  > N pin) with a termination resistor tied between them. The package
>  > parasitics were also tied to the two pins. I manually changed the
> values
>  > of the termination resistor and package parasitics to cover their
>  > variation in the typical, minimum and maximum corners.
>  >
>  > Probably there is a better solution, but that's what I did as a
>  > quick-and-dirty work-around.
>  >
>  > Regards.
>  >
>  > Hassan.
>  >
>  > Hassan Ali, Ph.D.
>  > Signal Integrity Specialist   -Talented, innovative designers
>  > Fidus Systems Inc.               -Highly competitive rates
>  > Tel: (613) 828-0063 Ext.342   -Fixed-price business model
>  > Fax: (613) 828-3113              -State-of-the-art design tools
>  > http://www.fidus.ca                -Customer-friendly attitude
>  >
>  > -----Original Message-----
>  > From: Peter LaFlamme [mailto:[email-masked]]
>  > Sent: Tuesday, July 23, 2002 9:01 AM
>  > To: [email-masked]
>  > Subject: [IBIS-Users] LVDS RECEIVER TERMINATION Question
>  >
>  > Hi All,
>  > I am tasked with creating an IBIS model for an LVDS receiver cell that
>  > has an internal 100 ohm termination between the P and N nodes. I had
>  > asked Bob Ross about this a while ago and as usual he was very
> helpful.
>  > >From his response I used the following
>  > implementation:
>  >
>  > |****************************************************************
>  > |                       Component:  LVDSRCV
>  > |****************************************************************
>  > |
>  > [Component]      LVDSRCV
>  > [Manufacturer]   AMCC
>  > |
>  > |
>  > |
>  > [Package]
>  > |  variable       typ          min           max
>  > R_pkg            1E-3          NA            NA
>  > L_pkg            1E-9          NA            NA
>  > C_pkg            1E-12          NA            NA
>  > |
>  > [Pin]        signal_name     model_name         R_pin   L_pin   C_pin
>  >   1             PAD          lvdsrcv            NA      NA      NA
>  >   2             PADN         lvdsrcv            NA      NA      NA
>  > |
>  > [Series Pin Mapping]    pin_2   model_name      function_table_group
>  > 1                     2           rterm_100
>  >
>  > |
>  > [Diff_pin]      inv_pin     vdiff     tdelay_typ    tdelay_min
>  > tdelay_max
>  > |
>  >    1               2          0.2          0             0
> 0
>  >
>  > [Model]  rterm_100
>  > C_comp                   0.1pF   0.1pF  0.1pF
>  >
>  > Model_type  Series
>  > |variable        R(typ)  R(min)  R(max)
>  > [R Series]      100     80      120
>  >
>  > [Temperature Range]     25.00    125.00    0.00
>  > [Voltage Range]         1.800    1.650   1.950
>  >
>  >
> ************************************************************************
>  > ****************
>  >
>  > I was able to get the model past the IBIS checker but my simulations
> did
>  > not show the 100 ohm terminator. I was using a tool which I believe
> does
>  > not support this implementation (no need to mention names). I have
> seen
>  > other implementations where I believe
>  >
>  > a "Dynamic clamp" is used to model the termination behavior, but I am
>  > unsure. Can anyone guide me to some reference material or weigh in
> with
>  > your experience or help.
>  >
>  > Thanks alot,
>  > Peter
>  >
>  >
>  >
>  > --
>  > Peter LaFlamme
>  >
>  > Applied Micro Circuits Corp.
>  > System Applications Engineer
>  > 200 Minuteman Rd, 3rd Floor
>  > Andover, MA 01810
>  >
>  > 978-247-8470 phone
>  > 978-623-0055 Fax
>  > |------------------------------------------------------------------
>  > |For help or to subscribe/unsubscribe, email [email-masked]
>  > |with just the appropriate command message(s) in the body:
>  > |
>  > |  help
>  > |  subscribe   ibis       <optional e-mail address, if different>
>  > |  subscribe   ibis-users <optional e-mail address, if different>
>  > |  unsubscribe ibis       <optional e-mail address, if different>
>  > |  unsubscribe ibis-users <optional e-mail address, if different>
>  > |
>  > |or email a written request to [email-masked].
>  > |
>  > |IBIS reflector archives exist under:
>  > |
>  > |  http://www.eda.org/pub/ibis/email_archive/  Recent
>  > |  http://www.eda.org/pub/ibis/users_archive/  Recent
>  > |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
>
>
> --
>
>
>
>
>
>
>
>
> |------------------------------------------------------------------
> |For help or to subscribe/unsubscribe, email [email-masked]
> |with just the appropriate command message(s) in the body:
> |
> |  help
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> |
> |or email a written request to [email-masked].
> |
> |IBIS reflector archives exist under:
> |
> |  http://www.eda.org/pub/ibis/email_archive/  Recent
> |  http://www.eda.org/pub/ibis/users_archive/  Recent
> |  http://www.eda.org/pub/ibis/email/          E-mail since 1993
>

- --
Kevin M. Fisher
Consultant
Signal Integrity Software Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
Phone: (978) 461-0449, ext 11
http://www.sisoft.com

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
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|
|or email a written request to [email-masked].
|
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|
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|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
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|
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|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Fri, 26 Jul 2002 13:51:49 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: [IBIS-Users] Minutes, IBIS Open Forum Teleconference (07/19/02)

DATE: 7/26/02

SUBJECT: July 19, 2002 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2002 PARTICIPANTS LIST:
Ansoft Corporation             (Eric Bracken)
Apple Computer                 Kim Helliwell
Applied Simulation Technology  Fred Balistreri, Norio Matsui
Cadence Design                 Lynne Green*, Patrick dos Santos, Lance Wang
Cisco Systems                  Syed Huq, Abdulrahmun Rafiq, Zhiping Yang
Cypress Semiconductor          (Rajesh Manapat)
Huawei Technologies            (Jiang Xiang Zhong)
IBM                            Greg Edlund*, Pravin Patel*
Innoveda (Merged with Mentor   John Angulo*, Guy de Burgh*, Steve Gascoigne
  Graphics)
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Will Hobbs,
                               Pete Block, Ben Silva, Tony Lewis,
                               Michael Mirmak
LSI Logic                      [Larry Barnes], Frank Gasparik*
Matsushita (Panasonic)         Atsuji Ito
Mentor Graphics                Bob Ross*, Ian Dodd, Mike Donnelly,
                               Matt Hogan, Sherif Hammad, Tom Dagostino,
                               Eric Rongere, Karine Loudet
Micron Technology              Randy Wolff*
Mitsubishi                     Pat Hefferan
Molex Incorporated             Gus Panella
Motorola                       Rick Kingen
National Semiconductor         Milt Schwartz
NEC Corporation                (Akimoto Tetsuya)
North East Systems Associates  (Edward Sayre)
Philips Semiconductor          (D.C. Sessions)
Quantic EMC                    (Mike Ventham)
Siemens (& Automotive) AG      Helmut Katzier, Katja Koller, Eckhard Lenski*
Signal Integrity Software      Barry Katz, Walter Katz, Robert Moles,
                               Daniel Nilsson, Kevin Fisher, Steve Coe,
                               Wiley Gillmor, Douglas Burns, Eric Brock,
Sigrity                        Raj Raghuram
SiQual                         [Scott McMorrow], Dave Macemon, Rob Hinz
Texas Instruments              Thomas Fisher, Jean-Claude Perrin
Teraspeed                      (Scott McMorrow)
Time Domain Analysis Systems   Steve Corey, Dima Smolyansky
Via Technologies               (Weber Chuang)
Zuken (& Incases)              Caroline Legendre, Ralf Bruening

OTHER PARTICIPANTS IN 2002:
3Com (& CommWorks)             [Roy Leventhal], James Goshorn
Actel                          Prabhu Mohan
Agilent                        Herbert Lage
Airbus                         Claude Huet
Alstom Transport               Luca Giacotto
Apt Software                   Atul Agarwal
Astrium                        Olivier Prieur
Avanti                         (Hailong Wang)
Bee Technologies Corporation   Tsuyoshi Horigome
Brocade Communications         Robert Badal
Compaq                         Shafier-ur-Rahman
EADS CCR                       Alix de la Villeguerin
EFM                            Ekkehard Miersch
EIA                            [Cecilia Fleming], Chris Denham*
EMC Corporation                (Brian Arsenault)
Fairchild Semiconductor        Adam Tambone
Force Computers                Roger Sukiennik
Harman/Becker Automotive       Hartmut Exler
  Systems
Japan Electronics and          Kiyomi Daishido
  Information Technology
  Industries Association
  (JEITA)
Leventhal Design and           Roy Leventhal*
  Communication
National Institute of Applied  Sebastian Calvet (& Motorola), Etienne
Sicard,
  Science (INSA)               Stephane Baffreau
Northrup (Litton)              Robert Bremer
Sagam SA                       Quang Ngo, Matthieu Fontaines
Shindengen Elecric Mfg. Co.    [Tsuyoshi Horigome]
Sintecs                        Hans Klos
STMicroelectronics             Fabrice Boissieres
TDK                            Yoshikazu Fujishiro
Thales                         Saverio Lerose
Tyco Electronics               (Tim Minnick)
UTMC                           Greg Haynes
Xilinx                         Susan Wu, J.L. de Long
Independent                    Larry Barnes

In the list above, attendees at the meeting are indicated by *.  Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences
are as follows:

  Date                Bridge Number    Reservation #    Passcode
  August 9, 2002      1-888-316-5901      N/A           8515116
  (International Dial-In: 1-617-801-9781)

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas
out 7 days before each Open Forum, and meeting minutes out within 7 days
after.  When you call into the meeting, ask for the IBIS Open Forum hosted
by Stephen Peters and give the reservation number and passcode.

NOTE: "AR" = Action Required.

- -------------------------------- MINUTES -----------------------------------
INTRODUCTIONS AND MEETING QUORUM
No new participants.

MEMBERSHIP UPDATE AND TREASURER'S REPORT
Stephen Peters reported that Teraspeed Consulting has joined as a Voting
member listed above, making a total of 31 members.  Stephen and Bob Ross are
still contacting several other prospective member companies.  Our financial
reporting from EIA usually lags actual receipt of payments, so our official
reports typically show fewer members until months later.

REVIEW OF MINUTES AND AR'S
Stephen Peters noted that the June 28, 2002 minutes had the subject line
omitted

  SUBJECT: June 28, 2002 EIA IBIS Open Forum Meeting Minutes

Also the spelling of Atul Agarwal was corrected in the IBISCHK3 section.
These changes were made in the uploaded copy.  The minutes were approved
with
these corrections.

The ARs were discussed during the meeting.

MISCELLANY/ANNOUNCEMENTS
None.

PRESS AND WEB PAGE UPDATES
Stephen Peters reported that the Syed Huq updated the IBIS upcoming
events page and the roster page. 

Bob Ross reported that the July 8, 2002 article "Mesh Slimming Speeds
Spicelink Simulation" in Electrical Engineering Times, page 44, mentions an
IBIS driver addition to the Ansoft tool.

NEW MODELS AVAILABLE, LIBRARY UPDATE
Roy Leventhal reported no new updates since June.  Stephen Peters remarked
that he had visited the model web page recently and thought that the look
and feel of the page was improved.  Stephen thanked Roy for his upkeep of
the page.

OPENS FOR NEW ISSUES
None.

INTERNATIONAL/EXTERNAL PROGRESS
- - IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal
  (formerly, IEC 93/67/NP IBIS and EMC Simulation) - Stephen Peters needs
  to review the some comments on the Cookbook and Report document.

- - JEDEC JC-16 - Modeling and Testing - No report.

- - T10, Project 1414-DT - SCSI Signal Modeling (a Technical Committee of
  the National Committee for Information Technology (NCITS)) - No Report.

Because there have not been any reports from either the JC-16 committee or
the T10 SCSI Signal Modeling group in over a year, Stephen Peters announced
that we will drop these items from future agendas.

IBIS QUALITY COMMITTEE
Bob Ross reported that the IBIS Quality committee met on July 2, 2002 
and again on July 16, 2002.  The committee continues working on the 
checklist, and expect to have it ready by the October summit meeting.
Greg Edlund, reading from the quality committee minutes, noted that one
topic for discussion has been the addition of a header at the top of the
IBIS file that would summarize what is in the check list.

Bob Ross mentioned that as a result of the IBIS parser update the parser
test cases have been uploaded on the Quality Web Site.

IBIS OPEN SOURCE PARSER PROPOSAL DISCUSSION
No report.

IBIS MODEL REVIEW COMMITTEE DISCUSSION
Bob Ross reported that he is previewing a model.  It may be sent back to the
originator.

NEW ADMINISTRATIVE ISSUES
John Angulo reported that he has removed several old e-mail addresses from
the reflector mail list. 

BIRD76 - Additional Information Related to C_comp Refinements 
Stephen Peters introduced BIRD76 as an editorial correction to the IBIS 4.0
draft.  The purpose of this bird was to clarify the usage of the additional
C_comp parameters introduced by BIRD65.2.  Stephen emphasized that this BIRD
does not change any of the technical content or intent of the original
BIRD65.2, it only adds clarification language.

Changes include changing the name of two of the C_comp subparameters: 
C_comp_power has been changed to C_comp_power_clamp and C_comp_gnd has been
changed to C_comp_gnd_clamp.  In addition, the usage rules for the added
subparameters have been reworded to distinguish between the use of a 
subparameter and the use of its value.  A paragraph was also added that
clarifies what each added distributed capacitance represents (i.e. which
prototype circuit element the capacitance parallels). Finally, the last
paragraph under the [Rising Waveform] and [Falling Waveform] keyword
usage rules was updated to refer to the new C_comp subparameters.

Bob Ross had a few editorial comments.
1. Under sub-params:  remove the word "and" from the list and add a missing
   comma
2. In the third change paragraph, change 'parameters' to 'subparameters'
4. In the second change paragraph, change references from I-V curves to I-V
tables.

Bob asked if there was a technical requirement that the usage of any of the 
C_comp* subparameters implies the existence of the corresponding I-V table.
Arpad Muranyi replied that this was not the intent.  After discussion,
a proposed wording was excepted that clarifies this point. 

Finally, Bob requested that references to "simulator tool(s)" be changed
to "EDA tool(s)", and this change was accepted.

The motion was made and seconded to accept BIRD76 with the above revisions,
with the understanding that this BIRD would become part of the draft version
of IBIS 4.0.  The motion passed unanimously.  This BIRD will be posted as
BIRD 76.1 and Bob Ross will upload it to the web page.

IBIS VERSION 4.0 REVIEW AND VOTE
Stephen Peters opened the discussion by noting that the draft IBIS 4.0 
specification is available under the Version 4.0 Work In Process link on
the IBIS web page under the file name of ver4_0wip1.txt. 

  http://www.eda.org/pub/ibis/ver4.0_wip/

Stephen noted that he has received the following three editorial comments on
the current draft:

1) Under the [Model] keyword, remove the word "and" from the sub-parameter
list

2) Under the [Model Spec] keyword table description, change "spec" to 
"specification"

3) Under the [Test Data] keyword description, the last sentence is 
incomplete. Based on the original editorial update from Guy de Burgh, the
sentence should conclude with the word "originated."

Stephen then asked for any other editorial or technical comments on the 
draft specification.  Bob Ross asked to remove any reference to SPICE, as 
this term has not been defined by the specification.  After discussion the 
group agreed to replacing SPICE with the phrase 'circuit model'. 

Bob Ross also noted the following:

- -Change all dates for Copyright keywords from 1999 to 2002 in examples

- -Change [File Name] name from ver3_2.ibs to ver4.0.ibs

- -Under [Package Model] change in Usage Rules to
  ... Section 3, "GENERAL SYNTAX RULES AND GUIDELINES".

  - to be consistent with same phrase under [File Name]

- -[Model Spec] example for Vref .. needs to be aligned with the rest
  of the subparameters

- -Extra linefeed in [Receiver Thresholds] before Usage Rules:

- -Under [Pulldown], [Pullup], [GND Clamp], [POWER Clamp] Other Notes:
 Change: To limit the complexity of the IBIS Version 2.x and Version 3.x
 syntax checking programs,  ....
 To: To limit the complexity of the IBIS syntax checking programs, ...

- -[Test Load] second example, remove the reference to the IBIS accuracy
 handbook section. 

Stephen asked for a motion to accept IBIS 4.0 with the editorial revisions
noted above. It was so moved and seconded.  The motion to accept IBIS 4.0
as amended passed unanimously.  After the editorial updates have been done,
Bob Ross will upload the final IBIS version 4.0 specification to the web
site.

IBIS CONNECTOR & FUTURES GROUP REPORT
Stephen Peters reported that weekly meetings continue, with meetings held
July 9, and again on July 18, 2002.  The next meeting is scheduled for
August 1, 2002.  The group reviewed the ICM specification keywords and
subparameters for self consistency and consistency with the conventions
established by IBIS3.2.  Numerous changes were made, and the latest
specification will be posted to the web site under the Connector Info
Link as ICM_999.txt

  http://www.eda.org/pub/ibis/connector/

The only remaining issue is including text that describes keyword
positioning
rules.  The intent is to resolve this issue over the next week or so, then
at the August 1, 2002 meeting vote to release the specification to the IBIS
Open Forum for review and comment.

BIRD74.1 - EMI Parameters
Guy de Burgh had no update, and discussion was differed to the next meeting.

BIRD75.2 - Multi-Lingual Modeling IBIS Modeling Support
BIRD77 - Differential Subparameter Additions
Bob Ross stated that BIRD75.2 and BIRD77 were both issued together as an
update to BIRD75.1.  The major change prompting a separate BIRD77 is the
proposed additions of true differential model types:

  Input_diff, I/O_diff, 3-state_diff, and Output_diff

and two differential timing test loads:

  Rref_diff, Cref_diff.

These required documentation as subparameters within the existing [Model]
and [Model Spec] keywords.  Furthermore, the differential timing test load
can be used as an extension to existing IBIS without any of the 
Multi-lingual extension of BIRD75.2.

On BIRD77, Bob noted several editorial comments were received at the IBIS
connector/futures group meeting, and he will incorporate them into a revised
BIRD77.1. These comments include clarifying the connection of the added 
timing test loads and adding an example of timing test load usage. Stephen 
Peters also noted that the added model types are only applicable if the 
[External Model] keyword is present, and that BIRD75 will have to be 
considered before BIRD77. 

Bob also covered a number of editorial improvements and changes in BIRD75.2
based on better tuning the capabilities to the needs.  Bob mentioned that 
the name of the "cell_port" subparameter were changed to "signal_pin".
For timing locations, the BIRD has reverted back to the current locations
used in IBIS version 3.2.  Some of the prototype port names have also been
changed. 

Bob proposed that we formally call for a vote at the next meeting on both
BIRDs.

IBISCHK3 & BUG TRACKING STATUS
Bob Ross reported that the source code for ibischk3.2.9 has been 
distributed. The executables have been generated and uploaded.  BUG57 
through BUG67 except BUG59 and BUG62 were fixed.

Bob thanked Matthew Flora for distributing the source code and creating the
Windows executable.  Thanks also go to Guy de Burgh and Lynne Green for the
Unix and Linux executables.  The new executables are found at:

  http://www.eda.org/pub/ibis/ibischk3/

Finally, Bob Ross reported that Michael Mirmak of Intel has submitted a
revised test case for BUG68.  This test case is shorter than the previous 
file that demonstrated the problem.  

NEXT MEETING:
The next teleconference meeting will be on August 9, 2002 from 8:00 AM to
10:00 AM Pacific Daylight Time.  Votes are scheduled on BIRD75.2 and
BIRD77.1. 
============================================================================

                                      NOTES

IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
            [email-masked]
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            M/S JF4-215
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            20 120th Ave NE, Suite 103, Bellevue, WA 98005-3016

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            [email-masked]
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------------------------------

Date: Sat, 27 Jul 2002 00:29:30 +0300
From: "Hegazy, Hazem" <[email-masked]>
Subject: RE: [IBIS-Users] LVDS RECEIVER TERMINATION Question

This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.

- ------_=_NextPart_001_01C234EB.667041E6
Content-Type: text/plain

 Hi,

Yes, this is correct and pointed out as one of solution in the previously
mentioned presentation. But, this is has some limitation as when you make a
complementary voltage using the VCVS you should make it around certain CM
voltage. That will drag us back to the point if the buffer common mode
voltage varies with load.

BR,

- -----Original Message-----
From: Kevin Fisher
To: Hegazy, Hazem
Cc: [email-masked] '; ''Hassan Ali ' ';
[email-masked] ' '; [email-masked] '; ''Peter
LaFlamme ' '
Sent: 7/27/02 2:29 AM
Subject: Re: [IBIS-Users] LVDS RECEIVER TERMINATION Question

All,

One technique we have used for terminated LVDS receivers is to model 
the differential termination behavior in the power clamp and ground 
clamp curves themselves. The setup for this technique is similar to a 
popular technique for LVDS drivers: tie the sweeping DC voltage source 
(v_sweep) to the p-pad, tie a VCVS equal to v_sweep and a gain of -1 on 
the n-pad (v_sweep_bar) and bias both pads at the desired common mode 
voltage.

Modeling termination using this approach can also be applied to 
single-ended receivers that have termination on-die. We have had success

using IBIS models generated with this technique in various simulators 
because it uses only basic IBIS syntax. As Hazem points out though, IBIS

models generated for a certain Vcm is limited to nets where the common 
mode voltage doesn't vary from the one used to model the receiver.

We are currently looking into other possible solutions that are portable

across multiple simulators and don't have the Vcm limitation.

Hope this helps.

- -- 
Kevin M. Fisher
Consultant
Signal Integrity Software Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
Phone: (978) 461-0449, ext 11
http://www.sisoft.com

Hegazy, Hazem wrote:
>  Hi,
> Yes, it's not supported in SOME simulators but not all.
> The Rdiff/2 to certain CM voltage might be a good solution if the
common 
> mode voltage itself doesn't change with different loads. I've seen a
lot 
> of LVDS driver with common mode voltage changes with the differential 
> load value. I don't see if this applicable in the receiver case or
not, 
> I'm just saying the one should be careful.
> 
> BR,
> 
> 
> -----Original Message-----
> From: [email-masked]
> To: Hegazy, Hazem
> Cc: 'Hassan Ali '; [email-masked] '; 
> [email-masked]; 'Peter LaFlamme '
> Sent: 7/25/02 4:10 PM
> Subject: RE: [IBIS-Users] LVDS RECEIVER TERMINATION Question
> 
> Hello All,
> 
> R Series appears to be not supported  by the Ibis simulators, which is
a
> shame, since it has been prepared so well in Ibis 3.2
> 
> What do you think about the following approach:
> Use a resistor of Rdiff/2 to a fixed point at the level of the desired
> common mode voltage.
> This could be achieved by using the model Terminator and using Rgnd
and
> Rpower.
> 
> Looking forward to your reactions,
> 
> Rob
>
________________________________________________________________________
> __
> Rob Mataheroe
> Philips Semiconductors bv
> P.G. Logic Product Group PD&S
> Building AM1.108
> Senior Design Modeling Engineer
> Gerstweg 2
> Tel. ++31 (0)24 353 2370
> 6534 AE Nijmegen
> Fax. ++31 (0)24 353 2820
> The Netherlands
> Email: [email-masked]
> Seri: matahero@nyhp04
> 
> 
> 
> 
> 
> 
>  
> 
>                       "Hegazy, Hazem"
> 
>                       <hazem_hegazy@mentor             To:  "'Peter
> LaFlamme '" <[email-masked]>
> 
>                       g.com>                            "'Hassan Ali
'"
> <[email-masked]>                                                
>                       Sent by:                         cc:
> "[email-masked] '" <[email-masked]>
> 
>                       owner-ibis-users@ser              (bcc: Rob
> Mataheroe/NYM/SC/PHILIPS)
> 
>                       ver.eda.org                      Subject:   RE:
> [IBIS-Users] LVDS RECEIVER TERMINATION Question

>  
> 
>                                                        Classification:
> 
>                       07/23/02 11:01 PM
> 
>  
> 
>  
> 
> 
> 
> 
> 
>  Hi,
> I've a solution...I didn't test it yet but, I suggest that based on an
> old solution of mine for 100 terminated LVDS DRIVERS in IBIS summit
Jan
> 2001 "hegazy.pdf or zip on IBIS home page".
> 
> 
> In the driver case, I consider the internal termination as a part of
the
> buffer itself, I could not take it away "In some cases we can" so, I
> want to get the I-V characteristics based on this.
> 
> 
> What are the I-V characteristics? Simply, it's the steady state
solution
> of the voltage and current at all possible loads.
> 
> 
> So, I put a resistor between P node and N node and measure "steady
state
> voltage and current" now, vary the resistor value from zero to
infinity
> (open circuit) and do the same extraction to complete your I-V table.
> You will have the actual behavior of the
> buffer (Interactive) on all possible loading conditions. This is
> verified  with a lot of LVDS buffers for very famous customer.
> 
> 
> For the receiver we can't do that as there is no source of current
like
> in the driver case to measure the I and V.
> So, my suggestion is to put a voltage source between the p and n nodes
> (differential voltage source). Vary the voltage source value in normal
> DC analysis and measure the P voltage with the current through the
> voltage source to form the I-V table with the
> interaction of the n node inherited inside it.
> 
> 
> I'll try this solution with some validation and keep you all informed.
> I might have goofed!!
> 
> 
> BR,
> 
> 
> 
> 
> 
> -----Original Message-----
> From: Peter LaFlamme
> To: Hassan Ali
> Cc: [email-masked]
> Sent: 7/23/02 6:52 PM
> Subject: Re: [IBIS-Users] LVDS RECEIVER TERMINATION Question
> 
> 
> Hi Hassan,
> Thanks alot for the comments and information. I have done the same
thing
> previously in simulations. I have also received input models that had
> the internal termination modeled as a dynamic clamp. In comparisons
> between dynamic clamp modeled terminations
> and your method, I found that (just in my case) there was not real
good
> correlation.
> 
> 
> Regards,
> Peter
> 
> 
> Peter LaFlamme
> 
> 
> Applied Micro Circuits Corp.
> System Applications Engineer
> 200 Minuteman Rd, 3rd Floor
> Andover, MA 01810
> 
> 
> 978-247-8470 phone
> 978-623-0055 Fax
> 
> 
> 
> 
> 
> Hassan Ali wrote:
>  >
>  > Hi Peter,
>  >
>  > I had the same situation a few months ago and I only had to go with
an
>  > adhoc solution.
>  >
>  > Yes indeed most simulators do not have good support for
differential
>  > models with [R Series] termination. I ended up creating a
single-ended
>  > input buffer model (same for the P and N side) with no termination
>  > between P and N sides. This only captured the clamping function.
>  >
>  > In my simulation I had to recreate the terminated differential
input
>  > buffer by using two single-ended buffers (one for the P and one for
> the
>  > N pin) with a termination resistor tied between them. The package
>  > parasitics were also tied to the two pins. I manually changed the
> values
>  > of the termination resistor and package parasitics to cover their
>  > variation in the typical, minimum and maximum corners.
>  >
>  > Probably there is a better solution, but that's what I did as a
>  > quick-and-dirty work-around.
>  >
>  > Regards.
>  >
>  > Hassan.
>  >
>  > Hassan Ali, Ph.D.
>  > Signal Integrity Specialist   -Talented, innovative designers
>  > Fidus Systems Inc.               -Highly competitive rates
>  > Tel: (613) 828-0063 Ext.342   -Fixed-price business model
>  > Fax: (613) 828-3113              -State-of-the-art design tools
>  > http://www.fidus.ca                -Customer-friendly attitude
>  >
>  > -----Original Message-----
>  > From: Peter LaFlamme [mailto:[email-masked]]
>  > Sent: Tuesday, July 23, 2002 9:01 AM
>  > To: [email-masked]
>  > Subject: [IBIS-Users] LVDS RECEIVER TERMINATION Question
>  >
>  > Hi All,
>  > I am tasked with creating an IBIS model for an LVDS receiver cell
that
>  > has an internal 100 ohm termination between the P and N nodes. I
had
>  > asked Bob Ross about this a while ago and as usual he was very
> helpful.
>  > >From his response I used the following
>  > implementation:
>  >
>  > |****************************************************************
>  > |                       Component:  LVDSRCV
>  > |****************************************************************
>  > |
>  > [Component]      LVDSRCV
>  > [Manufacturer]   AMCC
>  > |
>  > |
>  > |
>  > [Package]
>  > |  variable       typ          min           max
>  > R_pkg            1E-3          NA            NA
>  > L_pkg            1E-9          NA            NA
>  > C_pkg            1E-12          NA            NA
>  > |
>  > [Pin]        signal_name     model_name         R_pin   L_pin
C_pin
>  >   1             PAD          lvdsrcv            NA      NA      NA
>  >   2             PADN         lvdsrcv            NA      NA      NA
>  > |
>  > [Series Pin Mapping]    pin_2   model_name
function_table_group
>  > 1                     2           rterm_100
>  >
>  > |
>  > [Diff_pin]      inv_pin     vdiff     tdelay_typ    tdelay_min
>  > tdelay_max
>  > |
>  >    1               2          0.2          0             0
> 0
>  >
>  > [Model]  rterm_100
>  > C_comp                   0.1pF   0.1pF  0.1pF
>  >
>  > Model_type  Series
>  > |variable        R(typ)  R(min)  R(max)
>  > [R Series]      100     80      120
>  >
>  > [Temperature Range]     25.00    125.00    0.00
>  > [Voltage Range]         1.800    1.650   1.950
>  >
>  >
>
************************************************************************
>  > ****************
>  >
>  > I was able to get the model past the IBIS checker but my
simulations
> did
>  > not show the 100 ohm terminator. I was using a tool which I believe
> does
>  > not support this implementation (no need to mention names). I have
> seen
>  > other implementations where I believe
>  >
>  > a "Dynamic clamp" is used to model the termination behavior, but I
am
>  > unsure. Can anyone guide me to some reference material or weigh in
> with
>  > your experience or help.
>  >
>  > Thanks alot,
>  > Peter
>  >
>  >
>  >
>  > --
>  > Peter LaFlamme
>  >
>  > Applied Micro Circuits Corp.
>  > System Applications Engineer
>  > 200 Minuteman Rd, 3rd Floor
>  > Andover, MA 01810
>  >
>  > 978-247-8470 phone
>  > 978-623-0055 Fax
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> -- 
> 
> 
> 
> 
> 
> 
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> 

- -- 
Kevin M. Fisher
Consultant
Signal Integrity Software Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
Phone: (978) 461-0449, ext 11
http://www.sisoft.com

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<TITLE>RE: [IBIS-Users] LVDS RECEIVER TERMINATION Question</TITLE>
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<P><FONT SIZE=3D2>&nbsp;Hi,</FONT>
</P>

<P><FONT SIZE=3D2>Yes, this is correct and pointed out as one of =
solution in the previously mentioned presentation. But, this is has =
some limitation as when you make a complementary voltage using the VCVS =
you should make it around certain CM voltage. That will drag us back to =
the point if the buffer common mode voltage varies with =
load.</FONT></P>

<P><FONT SIZE=3D2>BR,</FONT>
</P>
<BR>

<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Kevin Fisher</FONT>
<BR><FONT SIZE=3D2>To: Hegazy, Hazem</FONT>
<BR><FONT SIZE=3D2>Cc: [email-masked] '; ''Hassan Ali ' '; =
[email-masked] ' '; [email-masked] '; =
''Peter LaFlamme ' '</FONT></P>

<P><FONT SIZE=3D2>Sent: 7/27/02 2:29 AM</FONT>
<BR><FONT SIZE=3D2>Subject: Re: [IBIS-Users] LVDS RECEIVER TERMINATION =
Question</FONT>
</P>

<P><FONT SIZE=3D2>All,</FONT>
</P>

<P><FONT SIZE=3D2>One technique we have used for terminated LVDS =
receivers is to model </FONT>
<BR><FONT SIZE=3D2>the differential termination behavior in the power =
clamp and ground </FONT>
<BR><FONT SIZE=3D2>clamp curves themselves. The setup for this =
technique is similar to a </FONT>
<BR><FONT SIZE=3D2>popular technique for LVDS drivers: tie the sweeping =
DC voltage source </FONT>
<BR><FONT SIZE=3D2>(v_sweep) to the p-pad, tie a VCVS equal to v_sweep =
and a gain of -1 on </FONT>
<BR><FONT SIZE=3D2>the n-pad (v_sweep_bar) and bias both pads at the =
desired common mode </FONT>
<BR><FONT SIZE=3D2>voltage.</FONT>
</P>

<P><FONT SIZE=3D2>Modeling termination using this approach can also be =
applied to </FONT>
<BR><FONT SIZE=3D2>single-ended receivers that have termination on-die. =
We have had success</FONT>
</P>

<P><FONT SIZE=3D2>using IBIS models generated with this technique in =
various simulators </FONT>
<BR><FONT SIZE=3D2>because it uses only basic IBIS syntax. As Hazem =
points out though, IBIS</FONT>
</P>

<P><FONT SIZE=3D2>models generated for a certain Vcm is limited to nets =
where the common </FONT>
<BR><FONT SIZE=3D2>mode voltage doesn't vary from the one used to model =
the receiver.</FONT>
</P>

<P><FONT SIZE=3D2>We are currently looking into other possible =
solutions that are portable</FONT>
</P>

<P><FONT SIZE=3D2>across multiple simulators and don't have the Vcm =
limitation.</FONT>
</P>

<P><FONT SIZE=3D2>Hope this helps.</FONT>
</P>

<P><FONT SIZE=3D2>-- </FONT>
<BR><FONT SIZE=3D2>Kevin M. Fisher</FONT>
<BR><FONT SIZE=3D2>Consultant</FONT>
<BR><FONT SIZE=3D2>Signal Integrity Software Inc.</FONT>
<BR><FONT SIZE=3D2>6 Clock Tower Place, Suite 250</FONT>
<BR><FONT SIZE=3D2>Maynard, MA 01754</FONT>
<BR><FONT SIZE=3D2>Phone: (978) 461-0449, ext 11</FONT>
<BR><FONT SIZE=3D2><A HREF=3D"http://www.sisoft.com" =
TARGET=3D"_blank">http://www.sisoft.com</A></FONT>
</P>

<P><FONT SIZE=3D2>Hegazy, Hazem wrote:</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; Hi,</FONT>
<BR><FONT SIZE=3D2>&gt; Yes, it's not supported in SOME simulators but =
not all.</FONT>
<BR><FONT SIZE=3D2>&gt; The Rdiff/2 to certain CM voltage might be a =
good solution if the</FONT>
<BR><FONT SIZE=3D2>common </FONT>
<BR><FONT SIZE=3D2>&gt; mode voltage itself doesn't change with =
different loads. I've seen a</FONT>
<BR><FONT SIZE=3D2>lot </FONT>
<BR><FONT SIZE=3D2>&gt; of LVDS driver with common mode voltage changes =
with the differential </FONT>
<BR><FONT SIZE=3D2>&gt; load value. I don't see if this applicable in =
the receiver case or</FONT>
<BR><FONT SIZE=3D2>not, </FONT>
<BR><FONT SIZE=3D2>&gt; I'm just saying the one should be =
careful.</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; BR,</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; -----Original Message-----</FONT>
<BR><FONT SIZE=3D2>&gt; From: [email-masked]</FONT>
<BR><FONT SIZE=3D2>&gt; To: Hegazy, Hazem</FONT>
<BR><FONT SIZE=3D2>&gt; Cc: 'Hassan Ali '; [email-masked] =
'; </FONT>
<BR><FONT SIZE=3D2>&gt; [email-masked]; 'Peter =
LaFlamme '</FONT>
<BR><FONT SIZE=3D2>&gt; Sent: 7/25/02 4:10 PM</FONT>
<BR><FONT SIZE=3D2>&gt; Subject: RE: [IBIS-Users] LVDS RECEIVER =
TERMINATION Question</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; Hello All,</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; R Series appears to be not supported&nbsp; by =
the Ibis simulators, which is</FONT>
<BR><FONT SIZE=3D2>a</FONT>
<BR><FONT SIZE=3D2>&gt; shame, since it has been prepared so well in =
Ibis 3.2</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; What do you think about the following =
approach:</FONT>
<BR><FONT SIZE=3D2>&gt; Use a resistor of Rdiff/2 to a fixed point at =
the level of the desired</FONT>
<BR><FONT SIZE=3D2>&gt; common mode voltage.</FONT>
<BR><FONT SIZE=3D2>&gt; This could be achieved by using the model =
Terminator and using Rgnd</FONT>
<BR><FONT SIZE=3D2>and</FONT>
<BR><FONT SIZE=3D2>&gt; Rpower.</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; Looking forward to your reactions,</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; Rob</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT =
SIZE=3D2>_______________________________________________________________=
_________</FONT>
<BR><FONT SIZE=3D2>&gt; __</FONT>
<BR><FONT SIZE=3D2>&gt; Rob Mataheroe</FONT>
<BR><FONT SIZE=3D2>&gt; Philips Semiconductors bv</FONT>
<BR><FONT SIZE=3D2>&gt; P.G. Logic Product Group PD&amp;S</FONT>
<BR><FONT SIZE=3D2>&gt; Building AM1.108</FONT>
<BR><FONT SIZE=3D2>&gt; Senior Design Modeling Engineer</FONT>
<BR><FONT SIZE=3D2>&gt; Gerstweg 2</FONT>
<BR><FONT SIZE=3D2>&gt; Tel. ++31 (0)24 353 2370</FONT>
<BR><FONT SIZE=3D2>&gt; 6534 AE Nijmegen</FONT>
<BR><FONT SIZE=3D2>&gt; Fax. ++31 (0)24 353 2820</FONT>
<BR><FONT SIZE=3D2>&gt; The Netherlands</FONT>
<BR><FONT SIZE=3D2>&gt; Email: [email-masked]</FONT>
<BR><FONT SIZE=3D2>&gt; Seri: matahero@nyhp04</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT =
SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; &quot;Hegazy, Hazem&quot;</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT =
SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; =
&lt;hazem_hegazy@mentor&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp; To:&nbsp; &quot;'Peter</FONT>
<BR><FONT SIZE=3D2>&gt; LaFlamme '&quot; =
&lt;[email-masked]&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT =
SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; =
g.com&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp; &quot;'Hassan Ali</FONT>
<BR><FONT SIZE=3D2>'&quot;</FONT>
<BR><FONT SIZE=3D2>&gt; =
&lt;[email-masked]&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nb=
sp;&nbsp;&nbsp;&nbsp; </FONT>
<BR><FONT =
SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; Sent by:&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp; cc:</FONT>
<BR><FONT SIZE=3D2>&gt; &quot;[email-masked] '&quot; =
&lt;[email-masked]&gt;</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT =
SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; =
owner-ibis-users@ser&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp;&nbsp;&nbsp; (bcc: Rob</FONT>
<BR><FONT SIZE=3D2>&gt; Mataheroe/NYM/SC/PHILIPS)</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT =
SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; =
ver.eda.org&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Subject:&nbsp;&nbsp; RE:</FONT>
<BR><FONT SIZE=3D2>&gt; [IBIS-Users] LVDS RECEIVER TERMINATION =
Question</FONT>
</P>

<P><FONT SIZE=3D2>&gt;&nbsp; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT =
SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Classification:</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT =
SIZE=3D2>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; 07/23/02 11:01 PM</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; Hi,</FONT>
<BR><FONT SIZE=3D2>&gt; I've a solution...I didn't test it yet but, I =
suggest that based on an</FONT>
<BR><FONT SIZE=3D2>&gt; old solution of mine for 100 terminated LVDS =
DRIVERS in IBIS summit</FONT>
<BR><FONT SIZE=3D2>Jan</FONT>
<BR><FONT SIZE=3D2>&gt; 2001 &quot;hegazy.pdf or zip on IBIS home =
page&quot;.</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; In the driver case, I consider the internal =
termination as a part of</FONT>
<BR><FONT SIZE=3D2>the</FONT>
<BR><FONT SIZE=3D2>&gt; buffer itself, I could not take it away =
&quot;In some cases we can&quot; so, I</FONT>
<BR><FONT SIZE=3D2>&gt; want to get the I-V characteristics based on =
this.</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; What are the I-V characteristics? Simply, it's =
the steady state</FONT>
<BR><FONT SIZE=3D2>solution</FONT>
<BR><FONT SIZE=3D2>&gt; of the voltage and current at all possible =
loads.</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; So, I put a resistor between P node and N node =
and measure &quot;steady</FONT>
<BR><FONT SIZE=3D2>state</FONT>
<BR><FONT SIZE=3D2>&gt; voltage and current&quot; now, vary the =
resistor value from zero to</FONT>
<BR><FONT SIZE=3D2>infinity</FONT>
<BR><FONT SIZE=3D2>&gt; (open circuit) and do the same extraction to =
complete your I-V table.</FONT>
<BR><FONT SIZE=3D2>&gt; You will have the actual behavior of the</FONT>
<BR><FONT SIZE=3D2>&gt; buffer (Interactive) on all possible loading =
conditions. This is</FONT>
<BR><FONT SIZE=3D2>&gt; verified&nbsp; with a lot of LVDS buffers for =
very famous customer.</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; For the receiver we can't do that as there is =
no source of current</FONT>
<BR><FONT SIZE=3D2>like</FONT>
<BR><FONT SIZE=3D2>&gt; in the driver case to measure the I and =
V.</FONT>
<BR><FONT SIZE=3D2>&gt; So, my suggestion is to put a voltage source =
between the p and n nodes</FONT>
<BR><FONT SIZE=3D2>&gt; (differential voltage source). Vary the voltage =
source value in normal</FONT>
<BR><FONT SIZE=3D2>&gt; DC analysis and measure the P voltage with the =
current through the</FONT>
<BR><FONT SIZE=3D2>&gt; voltage source to form the I-V table with =
the</FONT>
<BR><FONT SIZE=3D2>&gt; interaction of the n node inherited inside =
it.</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; I'll try this solution with some validation and =
keep you all informed.</FONT>
<BR><FONT SIZE=3D2>&gt; I might have goofed!!</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; BR,</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; -----Original Message-----</FONT>
<BR><FONT SIZE=3D2>&gt; From: Peter LaFlamme</FONT>
<BR><FONT SIZE=3D2>&gt; To: Hassan Ali</FONT>
<BR><FONT SIZE=3D2>&gt; Cc: [email-masked]</FONT>
<BR><FONT SIZE=3D2>&gt; Sent: 7/23/02 6:52 PM</FONT>
<BR><FONT SIZE=3D2>&gt; Subject: Re: [IBIS-Users] LVDS RECEIVER =
TERMINATION Question</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; Hi Hassan,</FONT>
<BR><FONT SIZE=3D2>&gt; Thanks alot for the comments and information. I =
have done the same</FONT>
<BR><FONT SIZE=3D2>thing</FONT>
<BR><FONT SIZE=3D2>&gt; previously in simulations. I have also received =
input models that had</FONT>
<BR><FONT SIZE=3D2>&gt; the internal termination modeled as a dynamic =
clamp. In comparisons</FONT>
<BR><FONT SIZE=3D2>&gt; between dynamic clamp modeled =
terminations</FONT>
<BR><FONT SIZE=3D2>&gt; and your method, I found that (just in my case) =
there was not real</FONT>
<BR><FONT SIZE=3D2>good</FONT>
<BR><FONT SIZE=3D2>&gt; correlation.</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; Regards,</FONT>
<BR><FONT SIZE=3D2>&gt; Peter</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; Peter LaFlamme</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; Applied Micro Circuits Corp.</FONT>
<BR><FONT SIZE=3D2>&gt; System Applications Engineer</FONT>
<BR><FONT SIZE=3D2>&gt; 200 Minuteman Rd, 3rd Floor</FONT>
<BR><FONT SIZE=3D2>&gt; Andover, MA 01810</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; 978-247-8470 phone</FONT>
<BR><FONT SIZE=3D2>&gt; 978-623-0055 Fax</FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; Hassan Ali wrote:</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Hi Peter,</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; I had the same situation a few =
months ago and I only had to go with</FONT>
<BR><FONT SIZE=3D2>an</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; adhoc solution.</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Yes indeed most simulators do not =
have good support for</FONT>
<BR><FONT SIZE=3D2>differential</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; models with [R Series] termination. =
I ended up creating a</FONT>
<BR><FONT SIZE=3D2>single-ended</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; input buffer model (same for the P =
and N side) with no termination</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; between P and N sides. This only =
captured the clamping function.</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; In my simulation I had to recreate =
the terminated differential</FONT>
<BR><FONT SIZE=3D2>input</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; buffer by using two single-ended =
buffers (one for the P and one for</FONT>
<BR><FONT SIZE=3D2>&gt; the</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; N pin) with a termination resistor =
tied between them. The package</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; parasitics were also tied to the two =
pins. I manually changed the</FONT>
<BR><FONT SIZE=3D2>&gt; values</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; of the termination resistor and =
package parasitics to cover their</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; variation in the typical, minimum =
and maximum corners.</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Probably there is a better solution, =
but that's what I did as a</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; quick-and-dirty work-around.</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Regards.</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Hassan.</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Hassan Ali, Ph.D.</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Signal Integrity =
Specialist&nbsp;&nbsp; -Talented, innovative designers</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Fidus Systems =
Inc.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp; -Highly competitive rates</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Tel: (613) 828-0063 =
Ext.342&nbsp;&nbsp; -Fixed-price business model</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Fax: (613) =
828-3113&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbs=
p;&nbsp;&nbsp; -State-of-the-art design tools</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; <A HREF=3D"http://www.fidus.ca" =
TARGET=3D"_blank">http://www.fidus.ca</A>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&=
nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
- -Customer-friendly attitude</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; -----Original Message-----</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; From: Peter LaFlamme [<A =
HREF=3D"mailto:[email-masked]">mailto:[email-masked]</A>]</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Sent: Tuesday, July 23, 2002 9:01 =
AM</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; To: [email-masked]</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Subject: [IBIS-Users] LVDS RECEIVER =
TERMINATION Question</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Hi All,</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; I am tasked with creating an IBIS =
model for an LVDS receiver cell</FONT>
<BR><FONT SIZE=3D2>that</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; has an internal 100 ohm termination =
between the P and N nodes. I</FONT>
<BR><FONT SIZE=3D2>had</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; asked Bob Ross about this a while =
ago and as usual he was very</FONT>
<BR><FONT SIZE=3D2>&gt; helpful.</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; &gt;From his response I used the =
following</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; implementation:</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; =
|****************************************************************</FONT>=

<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; =
|&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
Component:&nbsp; LVDSRCV</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; =
|****************************************************************</FONT>=

<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; |</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; =
[Component]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; LVDSRCV</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; [Manufacturer]&nbsp;&nbsp; =
AMCC</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; |</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; |</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; |</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; [Package]</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; |&nbsp; =
variable&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
typ&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
min&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
max</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; =
R_pkg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
1E-3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; L_pkg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&n=
bsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
1E-9&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; =
C_pkg&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
1E-12&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; |</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; =
[Pin]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
signal_name&nbsp;&nbsp;&nbsp;&nbsp; =
model_name&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
R_pin&nbsp;&nbsp; L_pin</FONT>
<BR><FONT SIZE=3D2>C_pin</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;&nbsp;&nbsp; =
1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; PAD&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
lvdsrcv&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;&nbsp;&nbsp; =
2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; PADN&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
lvdsrcv&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; NA&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
NA</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; |</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; [Series Pin =
Mapping]&nbsp;&nbsp;&nbsp; pin_2&nbsp;&nbsp; model_name</FONT>
<BR><FONT SIZE=3D2>function_table_group</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; =
1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
rterm_100</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; |</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; =
[Diff_pin]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
inv_pin&nbsp;&nbsp;&nbsp;&nbsp; vdiff&nbsp;&nbsp;&nbsp;&nbsp; =
tdelay_typ&nbsp;&nbsp;&nbsp; tdelay_min</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; tdelay_max</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; |</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;&nbsp;&nbsp;&nbsp; =
1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
;&nbsp;&nbsp; 2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
0.2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
0&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp=
; 0</FONT>
<BR><FONT SIZE=3D2>&gt; 0</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; [Model]&nbsp; rterm_100</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; =
C_comp&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.1pF&nbsp;&nbsp; =
0.1pF&nbsp; 0.1pF</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Model_type&nbsp; Series</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; =
|variable&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; R(typ)&nbsp; =
R(min)&nbsp; R(max)</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; [R =
Series]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 100&nbsp;&nbsp;&nbsp;&nbsp; =
80&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 120</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; [Temperature =
Range]&nbsp;&nbsp;&nbsp;&nbsp; 25.00&nbsp;&nbsp;&nbsp; =
125.00&nbsp;&nbsp;&nbsp; 0.00</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; [Voltage =
Range]&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
1.800&nbsp;&nbsp;&nbsp; 1.650&nbsp;&nbsp; 1.950</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;</FONT>
<BR><FONT =
SIZE=3D2>***************************************************************=
*********</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; ****************</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; I was able to get the model past the =
IBIS checker but my</FONT>
<BR><FONT SIZE=3D2>simulations</FONT>
<BR><FONT SIZE=3D2>&gt; did</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; not show the 100 ohm terminator. I =
was using a tool which I believe</FONT>
<BR><FONT SIZE=3D2>&gt; does</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; not support this implementation (no =
need to mention names). I have</FONT>
<BR><FONT SIZE=3D2>&gt; seen</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; other implementations where I =
believe</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; a &quot;Dynamic clamp&quot; is used =
to model the termination behavior, but I</FONT>
<BR><FONT SIZE=3D2>am</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; unsure. Can anyone guide me to some =
reference material or weigh in</FONT>
<BR><FONT SIZE=3D2>&gt; with</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; your experience or help.</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Thanks alot,</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Peter</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; --</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Peter LaFlamme</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Applied Micro Circuits Corp.</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; System Applications Engineer</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; 200 Minuteman Rd, 3rd Floor</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; Andover, MA 01810</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt;</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; 978-247-8470 phone</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; 978-623-0055 Fax</FONT>
<BR><FONT SIZE=3D2>&gt;&nbsp; &gt; =
|------------------------------------------------------------------</FON=
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<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; -- </FONT>
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<BR><FONT SIZE=3D2>&gt; </FONT>
<BR><FONT SIZE=3D2>&gt; </FONT>
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<BR><FONT SIZE=3D2>&gt; </FONT>
</P>
<BR>
<BR>

<P><FONT SIZE=3D2>-- </FONT>
<BR><FONT SIZE=3D2>Kevin M. Fisher</FONT>
<BR><FONT SIZE=3D2>Consultant</FONT>
<BR><FONT SIZE=3D2>Signal Integrity Software Inc.</FONT>
<BR><FONT SIZE=3D2>6 Clock Tower Place, Suite 250</FONT>
<BR><FONT SIZE=3D2>Maynard, MA 01754</FONT>
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</P>

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------------------------------

Date: Mon, 29 Jul 2002 19:37:46 -0700
From: Kar Hooi Kuan <[email-masked]>
Subject: [IBIS-Users] Modeling Differential I/O

Hi all,

I have problems modeling differential I/O model like PCML and LVDS. Is that
the method described in the IBIS cookbook can be used? If the cookbook
method cannot be used, how I can generate the IBIS model for differential
I/O?

Regards,
________________________________
Kar Hooi Kuan
Applications Engineer
Altera Corporation Penang
Plot 6, Bayan Lepas Technoplex, Medan Bayan Lepas
11900 Penang, Malaysia
Tel(hp): 6012-5611508
     (O) : 604-6366471
   (Fax): 604-642-8525 

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|with just the appropriate command message(s) in the body:
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------------------------------

Date: Tue, 30 Jul 2002 09:38:16 -0700
From: "Peters, Stephen" <[email-masked]>
Subject: RE: [IBIS-Users] Modeling Differential I/O

Hello Kar:

  The current cookbook does not contain information on creating differential
models in IBIS.  However, there have been several IBIS summit presentations
on the subject.  The following link is for a paper presented at the January
2001 IBIS summit.

http://www.eda.org/pub/ibis/summits/jan01/

  Download the file hegazy.zip.   It's a long paper, but it should get you
started.  In addition, I believe Adam Tambone from Fairchild has published a
paper on LVDS modeling in IBIS -- it's available on the web, although I
don't have the URL handy at the moment.

Good Luck.

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: Kar Hooi Kuan [mailto:[email-masked]]
Sent: Monday, July 29, 2002 7:38 PM
To: [email-masked]
Subject: [IBIS-Users] Modeling Differential I/O

Hi all,

I have problems modeling differential I/O model like PCML and LVDS. Is that
the method described in the IBIS cookbook can be used? If the cookbook
method cannot be used, how I can generate the IBIS model for differential
I/O?

Regards,
________________________________
Kar Hooi Kuan
Applications Engineer
Altera Corporation Penang
Plot 6, Bayan Lepas Technoplex, Medan Bayan Lepas
11900 Penang, Malaysia
Tel(hp): 6012-5611508
     (O) : 604-6366471
   (Fax): 604-642-8525 

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|with just the appropriate command message(s) in the body:
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------------------------------

Date: Wed, 31 Jul 2002 01:48:09 -0700
From: Kar Hooi Kuan <[email-masked]>
Subject: RE: [IBIS-Users] Modeling Differential I/O

Adam,

I see your method, I think that is a more accurate method. However, that is
for LVDS, is that applicable for other differential I/O like lvpecl or pcml?
I found that there is no voltage offset for these two differential models.
Can we set a constant reference voltage accross the non-inverted and
inverted pins instead of using the offset voltage. Thanks.

Regards,
________________________________
Kar Hooi

- -----Original Message-----
From: [email-masked]
[mailto:[email-masked]]
Sent: Wednesday, July 31, 2002 1:13 AM
To: 'Kar Hooi Kuan'; [email-masked]
Subject: RE: [IBIS-Users] Modeling Differential I/O

Hello Kar,

I hope this attachment makes it through...

Attached is a URL to a paper I wrote, and attached is a .ppt presentation
describing my experiences and methods of creating LVDS IBIS models ( check
the speaker notes in the presentation for descriptions of the slides ).  If
the attachments do not make it through to the IBIS users list, and there is
anyone who wishes to have copies, just contact me offline.

The methods described have worked well for me, and for the most part the
feedback I have received has said that the methods have been working for
others.  Although recently two people have contacted me about correlation
difficulties they are having.   All feedback is welcome.

Rgds,
Adam

http://www.planetanalog.com/features/OEG20020403S0018

(See attached file: present2_bkup.ppt)

|---------+--------------------------->
|         |           "Peters,        |
|         |           Stephen"        |
|         |           <stephen.peters@|
|         |           intel.com>      |
|         |           Sent by:        |
|         |           owner-ibis-users|
|         |           @eda.org        |
|         |                           |
|         |                           |
|         |           07/30/02 12:38  |
|         |           PM              |
|         |                           |
|---------+--------------------------->
 
>---------------------------------------------------------------------------
- ----------------------------------------------------|
  |
|
  |        To:      "'Kar Hooi Kuan'" <[email-masked]>,
[email-masked]                                                     |
  |        cc:
|
  |        Subject: RE: [IBIS-Users] Modeling Differential I/O
|
 
>---------------------------------------------------------------------------
- ----------------------------------------------------|

Hello Kar:

  The current cookbook does not contain information on creating
differential
models in IBIS.  However, there have been several IBIS summit presentations
on the subject.  The following link is for a paper presented at the January
2001 IBIS summit.

http://www.eda.org/pub/ibis/summits/jan01/

  Download the file hegazy.zip.   It's a long paper, but it should get you
started.  In addition, I believe Adam Tambone from Fairchild has published
a
paper on LVDS modeling in IBIS -- it's available on the web, although I
don't have the URL handy at the moment.

Good Luck.

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: Kar Hooi Kuan [mailto:[email-masked]]
Sent: Monday, July 29, 2002 7:38 PM
To: [email-masked]
Subject: [IBIS-Users] Modeling Differential I/O

Hi all,

I have problems modeling differential I/O model like PCML and LVDS. Is that
the method described in the IBIS cookbook can be used? If the cookbook
method cannot be used, how I can generate the IBIS model for differential
I/O?

Regards,
________________________________
Kar Hooi Kuan
Applications Engineer
Altera Corporation Penang
Plot 6, Bayan Lepas Technoplex, Medan Bayan Lepas
11900 Penang, Malaysia
Tel(hp): 6012-5611508
     (O) : 604-6366471
   (Fax): 604-642-8525

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
|
|  help
|  subscribe   ibis       <optional e-mail address, if different>
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|  unsubscribe ibis       <optional e-mail address, if different>
|  unsubscribe ibis-users <optional e-mail address, if different>
|
|or email a written request to [email-masked].
|
|IBIS reflector archives exist under:
|
|  http://www.eda.org/pub/ibis/email_archive/  Recent
|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993
|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
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|or email a written request to [email-masked].
|
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|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
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|  unsubscribe ibis       <optional e-mail address, if different>
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|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Wed, 31 Jul 2002 09:08:00 -0400
From: [email-masked]
Subject: RE: [IBIS-Users] Modeling Differential I/O

Hello Kar,

I'll be honest...  I just don't know.  Perhaps there are others who can
shed some light on creating lvpecl and pcml IBIS models.  Soon I will be
creating such models, but it will be a first for me and I don't have the
experience to share right now.  Sorry I can't be more helpful.

Rgds,
Adam

|---------+--------------------------->
|         |           Kar Hooi Kuan   |
|         |           <[email-masked]|
|         |           om>             |
|         |                           |
|         |           07/31/02 04:48  |
|         |           AM              |
|         |                           |
|---------+--------------------------->
  >-------------------------------------------------------------------------------------------------------------------------------|
  |                                                                                                                               |
  |        To:      Adam Tambone/SouthPortland/Fairchild@Fairchild                                                                |
  |        cc:      [email-masked]                                                                                            |
  |        Subject: RE: [IBIS-Users] Modeling Differential I/O                                                                    |
  >-------------------------------------------------------------------------------------------------------------------------------|

Adam,

I see your method, I think that is a more accurate method. However, that is
for LVDS, is that applicable for other differential I/O like lvpecl or
pcml?
I found that there is no voltage offset for these two differential models.
Can we set a constant reference voltage accross the non-inverted and
inverted pins instead of using the offset voltage. Thanks.

Regards,
________________________________
Kar Hooi

- -----Original Message-----
From: [email-masked]
[mailto:[email-masked]]
Sent: Wednesday, July 31, 2002 1:13 AM
To: 'Kar Hooi Kuan'; [email-masked]
Subject: RE: [IBIS-Users] Modeling Differential I/O

Hello Kar,

I hope this attachment makes it through...

Attached is a URL to a paper I wrote, and attached is a .ppt presentation
describing my experiences and methods of creating LVDS IBIS models ( check
the speaker notes in the presentation for descriptions of the slides ).  If
the attachments do not make it through to the IBIS users list, and there is
anyone who wishes to have copies, just contact me offline.

The methods described have worked well for me, and for the most part the
feedback I have received has said that the methods have been working for
others.  Although recently two people have contacted me about correlation
difficulties they are having.   All feedback is welcome.

Rgds,
Adam

http://www.planetanalog.com/features/OEG20020403S0018

(See attached file: present2_bkup.ppt)

|---------+--------------------------->
|         |           "Peters,        |
|         |           Stephen"        |
|         |           <stephen.peters@|
|         |           intel.com>      |
|         |           Sent by:        |
|         |           owner-ibis-users|
|         |           @eda.org        |
|         |                           |
|         |                           |
|         |           07/30/02 12:38  |
|         |           PM              |
|         |                           |
|---------+--------------------------->

>
- ---------------------------------------------------------------------------
- ----------------------------------------------------|
  |
|
  |        To:      "'Kar Hooi Kuan'" <[email-masked]>,
[email-masked]                                                     |
  |        cc:
|
  |        Subject: RE: [IBIS-Users] Modeling Differential I/O
|

>
- ---------------------------------------------------------------------------
- ----------------------------------------------------|

Hello Kar:

  The current cookbook does not contain information on creating
differential
models in IBIS.  However, there have been several IBIS summit presentations
on the subject.  The following link is for a paper presented at the January
2001 IBIS summit.

http://www.eda.org/pub/ibis/summits/jan01/

  Download the file hegazy.zip.   It's a long paper, but it should get you
started.  In addition, I believe Adam Tambone from Fairchild has published
a
paper on LVDS modeling in IBIS -- it's available on the web, although I
don't have the URL handy at the moment.

Good Luck.

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: Kar Hooi Kuan [mailto:[email-masked]]
Sent: Monday, July 29, 2002 7:38 PM
To: [email-masked]
Subject: [IBIS-Users] Modeling Differential I/O

Hi all,

I have problems modeling differential I/O model like PCML and LVDS. Is that
the method described in the IBIS cookbook can be used? If the cookbook
method cannot be used, how I can generate the IBIS model for differential
I/O?

Regards,
________________________________
Kar Hooi Kuan
Applications Engineer
Altera Corporation Penang
Plot 6, Bayan Lepas Technoplex, Medan Bayan Lepas
11900 Penang, Malaysia
Tel(hp): 6012-5611508
     (O) : 604-6366471
   (Fax): 604-642-8525

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
|
|  help
|  subscribe   ibis       <optional e-mail address, if different>
|  subscribe   ibis-users <optional e-mail address, if different>
|  unsubscribe ibis       <optional e-mail address, if different>
|  unsubscribe ibis-users <optional e-mail address, if different>
|
|or email a written request to [email-masked].
|
|IBIS reflector archives exist under:
|
|  http://www.eda.org/pub/ibis/email_archive/  Recent
|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993
|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
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|or email a written request to [email-masked].
|
|IBIS reflector archives exist under:
|
|  http://www.eda.org/pub/ibis/email_archive/  Recent
|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
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|  help
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|or email a written request to [email-masked].
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|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Wed, 31 Jul 2002 17:01:03 -0700
From: Kar Hooi Kuan <[email-masked]>
Subject: RE: [IBIS-Users] Modeling Differential I/O

Adam,

It is fine, you don't need to say sorry. Since we will experiencing creating
the other models. Maybe next time we can share our experience.

Thanks for your reply.

Regards,
________________________________
Kar Hooi Kuan
Applications Engineer
Altera Corporation Penang
Plot 6, Bayan Lepas Technoplex, Medan Bayan Lepas
11900 Penang, Malaysia
Tel(hp): 6012-5611508
     (O) : 604-6366471
   (Fax): 604-642-8525 

- -----Original Message-----
From: [email-masked]
[mailto:[email-masked]]
Sent: Wednesday, July 31, 2002 9:08 PM
To: Kar Hooi Kuan
Cc: [email-masked]
Subject: RE: [IBIS-Users] Modeling Differential I/O

Hello Kar,

I'll be honest...  I just don't know.  Perhaps there are others who can
shed some light on creating lvpecl and pcml IBIS models.  Soon I will be
creating such models, but it will be a first for me and I don't have the
experience to share right now.  Sorry I can't be more helpful.

Rgds,
Adam

|---------+--------------------------->
|         |           Kar Hooi Kuan   |
|         |           <[email-masked]|
|         |           om>             |
|         |                           |
|         |           07/31/02 04:48  |
|         |           AM              |
|         |                           |
|---------+--------------------------->
 
>---------------------------------------------------------------------------
- ----------------------------------------------------|
  |
|
  |        To:      Adam Tambone/SouthPortland/Fairchild@Fairchild
|
  |        cc:      [email-masked]
|
  |        Subject: RE: [IBIS-Users] Modeling Differential I/O
|
 
>---------------------------------------------------------------------------
- ----------------------------------------------------|

Adam,

I see your method, I think that is a more accurate method. However, that is
for LVDS, is that applicable for other differential I/O like lvpecl or
pcml?
I found that there is no voltage offset for these two differential models.
Can we set a constant reference voltage accross the non-inverted and
inverted pins instead of using the offset voltage. Thanks.

Regards,
________________________________
Kar Hooi

- -----Original Message-----
From: [email-masked]
[mailto:[email-masked]]
Sent: Wednesday, July 31, 2002 1:13 AM
To: 'Kar Hooi Kuan'; [email-masked]
Subject: RE: [IBIS-Users] Modeling Differential I/O

Hello Kar,

I hope this attachment makes it through...

Attached is a URL to a paper I wrote, and attached is a .ppt presentation
describing my experiences and methods of creating LVDS IBIS models ( check
the speaker notes in the presentation for descriptions of the slides ).  If
the attachments do not make it through to the IBIS users list, and there is
anyone who wishes to have copies, just contact me offline.

The methods described have worked well for me, and for the most part the
feedback I have received has said that the methods have been working for
others.  Although recently two people have contacted me about correlation
difficulties they are having.   All feedback is welcome.

Rgds,
Adam

http://www.planetanalog.com/features/OEG20020403S0018

(See attached file: present2_bkup.ppt)

|---------+--------------------------->
|         |           "Peters,        |
|         |           Stephen"        |
|         |           <stephen.peters@|
|         |           intel.com>      |
|         |           Sent by:        |
|         |           owner-ibis-users|
|         |           @eda.org        |
|         |                           |
|         |                           |
|         |           07/30/02 12:38  |
|         |           PM              |
|         |                           |
|---------+--------------------------->

>
- ---------------------------------------------------------------------------
- ----------------------------------------------------|
  |
|
  |        To:      "'Kar Hooi Kuan'" <[email-masked]>,
[email-masked]                                                     |
  |        cc:
|
  |        Subject: RE: [IBIS-Users] Modeling Differential I/O
|

>
- ---------------------------------------------------------------------------
- ----------------------------------------------------|

Hello Kar:

  The current cookbook does not contain information on creating
differential
models in IBIS.  However, there have been several IBIS summit presentations
on the subject.  The following link is for a paper presented at the January
2001 IBIS summit.

http://www.eda.org/pub/ibis/summits/jan01/

  Download the file hegazy.zip.   It's a long paper, but it should get you
started.  In addition, I believe Adam Tambone from Fairchild has published
a
paper on LVDS modeling in IBIS -- it's available on the web, although I
don't have the URL handy at the moment.

Good Luck.

  Regards,
  Stephen Peters
  Intel Corp.

- -----Original Message-----
From: Kar Hooi Kuan [mailto:[email-masked]]
Sent: Monday, July 29, 2002 7:38 PM
To: [email-masked]
Subject: [IBIS-Users] Modeling Differential I/O

Hi all,

I have problems modeling differential I/O model like PCML and LVDS. Is that
the method described in the IBIS cookbook can be used? If the cookbook
method cannot be used, how I can generate the IBIS model for differential
I/O?

Regards,
________________________________
Kar Hooi Kuan
Applications Engineer
Altera Corporation Penang
Plot 6, Bayan Lepas Technoplex, Medan Bayan Lepas
11900 Penang, Malaysia
Tel(hp): 6012-5611508
     (O) : 604-6366471
   (Fax): 604-642-8525

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
|
|  help
|  subscribe   ibis       <optional e-mail address, if different>
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|  unsubscribe ibis       <optional e-mail address, if different>
|  unsubscribe ibis-users <optional e-mail address, if different>
|
|or email a written request to [email-masked].
|
|IBIS reflector archives exist under:
|
|  http://www.eda.org/pub/ibis/email_archive/  Recent
|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993
|------------------------------------------------------------------
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|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

|------------------------------------------------------------------
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|or email a written request to [email-masked].
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|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Tue, 13 Aug 2002 09:59:02 -0700
From: Hiten Bhagat <[email-masked]>
Subject: [IBIS-Users] IBIS model

Hi IBIS users,

I remember articles, which mention that one has to 
correct IBIS model before releasing it to the customer, 
on the basis of actual silicon reading.

How should I tweak my IBIS model on the basis of actual 
reading? Is there any script available?

thanks,
Hiten

|------------------------------------------------------------------
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|with just the appropriate command message(s) in the body:
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------------------------------

Date: 14 Aug 2002 14:00:53 -0400
From: "Perry Qu" <[email-masked]>
Subject: [IBIS-Users] Simplified model for receiver

Hi,

Can anyone share your experience to use a simple die capacitance to
replace IBIS receiver model, especially for differential receivers ? I
run into such situations frequently when some IBIS models does not
behave properly in HSPICE and I have to do the simulation using other
IBIS-based tools. e.g., i had a case right now when the driver is an
IBIS model (LVDS) and receiver is in HSPICE. The apparent choice is to
run the simulation in HSPICE. Unfortunately, the IBIS model does not
behave properly in HSPICE, whereas it works fine in XTK. I was forced to
run the simulation in XTK but I have to replace the HSPICE model of
receiver with a simplified model to at least get some feeling about the
signal integrity. Of course, I will add packaging in the simulation.

Thanks

- --
Perry Qu

Product Integrity         |      600 March Road
Alcatel Canada            |      Ottawa, ON K2K 2E6, Canada

DID: (613) 7846720        |      FAX: (613) 5993642

|------------------------------------------------------------------
|For help or to subscribe/unsubscribe, email [email-masked]
|with just the appropriate command message(s) in the body:
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|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

Date: Wed, 14 Aug 2002 16:31:57 -0400
From: Kevin Fisher <[email-masked]>
Subject: Re: [IBIS-Users] Simplified model for receiver

Perry,

What version of Hspice are you running?

In the combined IV curves for the LVDS driver model, where do the 
pullup/p-clamp and pulldown/g-clamp cross 0mA, and are there data points 
explicitly stating the 0mA crossing in the tables?

Have you ran other simulations with the IBIS driver model in Hspice that 
  gave you expected results?

I would suggest running an IV sweep on the LVDS IBIS model and comparing 
the resulting IV curves with the IV curves in the IBIS model.

- -- 
Kevin M. Fisher
Consultant
Signal Integrity Software Inc.
6 Clock Tower Place, Suite 250
Maynard, MA 01754
Phone: (978) 461-0449, ext 11
http://www.sisoft.com

Perry Qu wrote:
> Hi,
> 
> Can anyone share your experience to use a simple die capacitance to
> replace IBIS receiver model, especially for differential receivers ? I
> run into such situations frequently when some IBIS models does not
> behave properly in HSPICE and I have to do the simulation using other
> IBIS-based tools. e.g., i had a case right now when the driver is an
> IBIS model (LVDS) and receiver is in HSPICE. The apparent choice is to
> run the simulation in HSPICE. Unfortunately, the IBIS model does not
> behave properly in HSPICE, whereas it works fine in XTK. I was forced to
> run the simulation in XTK but I have to replace the HSPICE model of
> receiver with a simplified model to at least get some feeling about the
> signal integrity. Of course, I will add packaging in the simulation.
> 
> Thanks
> 
> --
> Perry Qu
> 
> Product Integrity         |      600 March Road
> Alcatel Canada            |      Ottawa, ON K2K 2E6, Canada
> 
> DID: (613) 7846720        |      FAX: (613) 5993642
> 
> 
> |------------------------------------------------------------------
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|  http://www.eda.org/pub/ibis/users_archive/  Recent
|  http://www.eda.org/pub/ibis/email/          E-mail since 1993

------------------------------

End of ibis-users V1 #8
***********************