Subject: FPGA IBIS model

From: KokTongTHAM <[email-masked]>
Date: Wed, 22 Nov 2000 17:52:27 +0900

Dear SI gurus,

I have an interconnect between Virtex FPGA(Xilinx) and SDRAM(Hitachi).
When Data read back from SDRAM, the waveform contain a lot of terrible 
ringing and overshoot.
I have doubt about the [Power Clamp] in FPGA(I/O model) to have any effect 
at all.

Can anybody give me any comments and solutions regarding the models?
(see attachment files)

Regards,
KTTHAM