Subject: the 4 V-t curves of IBIS 2.1

From: "Betty Luk" <[email-masked]>
Date: Wed, 27 Sep 2000 16:39:34 -0400

Hello,

Why do we need four V-t curves to describe the rising and falling edges of a CMOS buffer (as described in the IBIS cookbook)?

Many thanks,

Betty Luk

IC Technology
Genesis Microchip Inc.
165 Commerce Valley Dr. W.
Thornhill, Ont. L3T 7V8
(905) 889-5400 x2256

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From: Offer Kaye <[email-masked]>
Date: Thu, 28 Sep 2000 10:38:20 +0300 (IDT)

Betty, this is from a seminar given by Mr. Arpad Muranyi from Intel, so
all rights are reserved to him :)

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What do we get in the I-V curves?
Digital buffers can only be measured in two modes (if not one)
* Receive or 3-state mode
  * allows us to measure the currents of 
    parasitic diodes (for MOSFETS)
    ESD protection circuits
    pullup or pulldown "resistors"
    static overshoot protection clamps
    integrated static terminators
(comment by O.K.- the above are ALWAYS ON)

* Drive mode (driving high or low)
  * allows us to measure the currents of all of the above, plus
                                                           ----
    channel currents for pulldown and/or pullup structures
    dynamic clamps
    dynamic bus hold circuits
    integrated active terminators

BOTH MODES ARE NEEDED FOR SIMULATIONS

DRIVE/RECEIVE MODE TRANSITIONING
* Phase out "reciever model" as the "driver model" is phased in, or vive
versa
   It may be difficult to come up with an algorithm that can cross fade
   the two models so that the static currents remain constant during the
   transitioning process.

* Keep "receiver model" constantly in the circuit and phase in/out the
difference between the driver and receiver models
----------
   Note that a drive mode model includes the static currents of those
   circuit or device elements that make up a receive mode model because
   these are never turned off. These currents would be doubled if the
   drive mode model would simply be added to a receive mode model.

THE SECOND APPROACH IS USED IN IBIS.

---------------------------------------------------------------------

Hope this helped :)

Offer Kaye
[email-masked]
Web Site: http://t2.technion.ac.il/~sofferk

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From: Al Davis <[email-masked]>
Date: Thu, 28 Sep 2000 18:59:04 -0700

On Wed, 27 Sep 2000, Betty Luk wrote:
> Why do we need four V-t curves to describe the rising and falling
edges of a CMOS buffer (as described in the IBIS cookbook)?

I assume you mean 2 per edge.

One per edge describes what it does with a particular load.  What it
does into any other load is a guess.

By supplying more than one waveform per edge, with different loads, it
is possible to represent changes in the output resistance in the
driver, in addition to the voltage.

Usually, if you can provide 2 tables per edge, the best loads are to
use the same resistance in both cases, but connect one to ground and
the other to the power supply.  To see why, consider that the typical
driver consists of a pull-up device and a pull-down device.  A
resistor from the terminal to ground will tend to swamp out the
pull-down device, and characterize the pull-up device fairly well.  A
resistor to power will do the opposite.  Usually, the best resistance
to use is as close as possible to the load it will actually drive.

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From: Todd Westerhoff <[email-masked]>
Date: Fri, 29 Sep 2000 10:42:34 -0400

Hi everyone,

I've attached a .PDF from from a presentation by Donald Telian that shows why two sets of V-T curves per-driver-per-edge.  It's because you need to capture the relative timing of the different transistors that make up the output.  With that information, you can determine the "dynamic thevenin equivalent" (a term coined by Chris Rokusek that I REALLY like) and predict the output's behavior into a different load.

FYI, this is also why V-T curves MUST be into a PURE resistive load, while the output buffer delay can be measured into a complex (i.e. with capacitance and inductance) load.  If you know a device's behavior into a pure resistive load, you can use Ohm's law to back out the effect of the resistor and predict the behavior into another load.  The minute the load is complex, backing-out (technical term: de-embedding) the effect of the load is MUCH more difficult.

Todd.

>to use is as close as possible to the load it will actually drive.

    Todd Westerhoff
    Product Marketing Director | High Speed Systems Design | Performance Engineering
    Cadence Design Systems | 270 Billerica Road | Chelmsford, MA  01824
    
    ph: (978) 262-6327
    fx: (978) 446-6798
    email: [email-masked]
    internal information website: http://www-ma.cadence.com/~toddw