Subject: the 4 V-t curves of IBIS 2.1

From: [email-masked]
Date: Wed, 27 Sep 2000 16:52:41 -0500

Betty,

Imagine a standard push-pull CMOS output driver with a PMOS pull-up device
and an NMOS pull-down device.  In a behavioral model, you have information
about the Ids vs. Vds characteristics of these transistors, but you don't
know what their gate voltages look like as a function of time.  Using the
four V-T tables, a behavioral simulator can cleverly deduce when to
"activate" the I-V tables in time to make the behavioral simulation look as
much like the real circuit as possible.  A good example of this is crowbar
current.  I/O circuit designers will often time-shift the gate voltage
waveform of the PMOS device with respect to the NMOS device to keep both
devices from being on at the same time.  This minimizes the amount of
current shooting from Vdd to Vss and thereby minimizes noise.

Greg Edlund
Advisory Engineer
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
[email-masked]
---------------------- Forwarded by Gregory R Edlund/Rochester/IBM on
09/27/2000 04:41 PM ---------------------------

"Betty Luk" <[email-masked]> on 09/27/2000 03:39:34 PM

To:   <[email-masked]>
cc:

Subject:  the 4 V-t curves of IBIS 2.1

Hello,

Why do we need four V-t curves to describe the rising and falling edges of
a CMOS buffer (as described in the IBIS cookbook)?

Many thanks,

Betty Luk

IC Technology
Genesis Microchip Inc.
165 Commerce Valley Dr. W.
Thornhill, Ont. L3T 7V8
(905) 889-5400 x2256

---

From: Todd Westerhoff <[email-masked]>
Date: Fri, 29 Sep 2000 11:46:21 -0400

Hi all,

The previous document had "Cadence Confidential" on it - which it isn't.  My apologies.  This copy has been corrected.

Todd.

At 06:59 PM 9/28/2000 -0700, Al Davis wrote:
>On Wed, 27 Sep 2000, Betty Luk wrote:
> > Why do we need four V-t curves to describe the rising and falling
>edges of a CMOS buffer (as described in the IBIS cookbook)?
>
>I assume you mean 2 per edge.
>
>One per edge describes what it does with a particular load.  What it
>does into any other load is a guess.
>
>By supplying more than one waveform per edge, with different loads, it
>is possible to represent changes in the output resistance in the
>driver, in addition to the voltage.
>
>Usually, if you can provide 2 tables per edge, the best loads are to
>use the same resistance in both cases, but connect one to ground and
>the other to the power supply.  To see why, consider that the typical
>driver consists of a pull-up device and a pull-down device.  A
>resistor from the terminal to ground will tend to swamp out the
>pull-down device, and characterize the pull-up device fairly well.  A
>resistor to power will do the opposite.  Usually, the best resistance
>to use is as close as possible to the load it will actually drive.

    Todd Westerhoff
    Product Marketing Director | High Speed Systems Design | Performance Engineering
    Cadence Design Systems | 270 Billerica Road | Chelmsford, MA  01824
    
    ph: (978) 262-6327
    fx: (978) 446-6798
    email: [email-masked]
    internal information website: http://www-ma.cadence.com/~toddw