Subject: Overclocked driver schedule.

From: Al Davis <[email-masked]>
Date: Fri, 11 Aug 2000 00:06:43 -0700

What is the correct behavior for a simulator when driver
schedule is overclocked?

Consider this ....

[Driver Schedule]
foo  3.5ps  5ns  NA  NA

..  this gives it an extra kick on a rising edge.

The question ...

What should happen when the device is triggered to fall 3ns
after the rise begins?

Some possibilities .....

1. It waits another 2 ns (for the total of 5 ns) to turn
off?

2. It turns off on the falling edge? as if the line was:
foo 3.5ps 5ns 0ns NA

3. Other?

Should the standard be changed to clarify this?

---

From: "Beal, Weston" <[email-masked]>
Date: Mon, 14 Aug 2000 13:10:02 -0700

Al,

The few cases I've seen that use [driver_schedule] use the clock as the
timing key anyway.  The comments in the file state the model is only
accurate at a certain clock frequency and the parameters need to be changed
in order to work at a different clock frequency.  I would make the master
stimulus a real master and force drivers to follow it.

Later,
Weston

+ -----Original Message-----
+ From: Al Davis [mailto:[email-masked]]
+ Sent: Friday, August 11, 2000 12:07 AM
+ To: [email-masked]; [email-masked]
+ Subject: Overclocked driver schedule.
+ 
+ 
+ What is the correct behavior for a simulator when driver
+ schedule is overclocked?
+ 
+ Consider this ....
+ 
+ [Driver Schedule]
+ foo  3.5ps  5ns  NA  NA
+ 
+ ..  this gives it an extra kick on a rising edge.
+ 
+ The question ...
+ 
+ What should happen when the device is triggered to fall 3ns
+ after the rise begins?
+ 
+ Some possibilities .....
+ 
+ 1. It waits another 2 ns (for the total of 5 ns) to turn
+ off?
+ 
+ 2. It turns off on the falling edge? as if the line was:
+ foo 3.5ps 5ns 0ns NA
+ 
+ 3. Other?
+ 
+ 
+ Should the standard be changed to clarify this?
+

---

From: "Muranyi, Arpad" <[email-masked]>
Date: Thu, 17 Aug 2000 16:35:56 -0700

Al,

Sorry for that, I misread your first posting.

In this case it should be 1), but I need to clarify it to make
sure we mean the same thing.

On the rising edge the kicker you describe turns on with the
3.5 ps delay.  A timer in the buffer will start and shut it
off 5 ns later.  If the input to the buffer goes low in the
meantime, the normal part of the buffer should switch high to
low, but the kicker part should remain high until the timer
(5 ns) expires.  This will result in a crowbar current
between the kicker and the pulldown.  So I would question
whether this is what the model maker (or buffer designer)
really had in mind, but this is how the IBIS spec should be
interpreted.

Arpad Muranyi
Intel Corporation
===========================================================

-----Original Message-----
From: [email-masked] [mailto:[email-masked]]
Sent: Thursday, August 17, 2000 2:55 PM
To: Muranyi, Arpad
Cc: 'Al Davis'; [email-masked]; [email-masked]
Subject: RE: Overclocked driver schedule.

On Thu, 17 Aug 2000, Muranyi, Arpad wrote:
> So, if the rise on delay is 3.5ns, and the logic high pulse is less that
in
> duration, that means that the t0 time for this scheduled pullup device
never
> happened.  So it should not even begin to turn on.  The pulldown that was
> holding the signal low prior to this rising edge is turned off earlier by
> the rising edge when the signal level goes above Vinl.
> 
> Therefore the answer is NO to both 1) and 2).

That one is obvious, but I said the rise on delay was 3.5 PICO seconds, 
so it DID turn on since the pulse width was 2 ns.  So, it doesn't apply to
the case I asked about.

Given that it did turn on, when should it turn off?

> -----Original Message-----