Subject: C_comp confusion

From: "Steve Constable" <[email-masked]>
Date: Tue, 15 Feb 2000 17:30:27 -0500

I'm confused about C_comp. All of the data tables in an IBIS file are ordered as TYP, MIN then MAX.
But it looks like C_comp is ordered as TYP, MAX then MIN....that's were the confusion is.
The reason I think C_comp is ordered differently is that the MAX should have the smallest capacitance associated with it _not_ the greatest. In the example below (taken from the 21152_aa.ibs model from Intel), the C_comp has a max value of 0.50pF, this will slow down the I/O buffer (compared to the TYP case of 0.40pF), this contradicts what the rest of the model is trying achieve when the simulator is referring to the MAX columns (i.e. MAXimize speed).
Likewise I think the C_comp_min should be 0.50pF NOT what the model indicates as 0.30pF.
And the C_comp_max should be 0.30pF NOT 0.50pF as the model indicates.

Just in case I've not made myself all that clear....below I have added a line to the original C_comp line:

|                                   TYP           MIN           MAX
[Temperature Range]      25.00         100.00        0.000
[Voltage Range]             3.30V         3.00V        3.60V
C_comp                        0.40pF       0.30pF       0.50pF
| should be: C_comp      0.40pF       0.50pF       0.30pF
I.E swap the 0.30pF with the 0.50pF......

I've checked with several different models and they all seem to have C_comp as TYP,MAX,MIN
Even the IBIS spec has the MAX value as the largest and not the smallest capacitance...as below:
Vref = 0                   |Timing specification test load voltage
| variable      typ             min             max
C_comp      12.0pF       10.0pF        15.0pF

If that's the way the spec has it, then I guess everyone will follow the spec, but I'm still confused as to why the MAX parameter has the largest capacitance when the objective of using MAX is to get the fastest switching time possible.....

Any ideas or suggestions....?????

Steve Constable
Tundra Semiconductor

---

From: "Chris Rokusek" <[email-masked]>
Date: Tue, 15 Feb 2000 15:02:07 -0800

Steve,

To my knowledge, an IBIS file defines three independently selectable process
points:

1) C_comp.
2) VI/VT/Ramp data.
3) Package data.

The spec only says that VI data at a TYP/MIN/MAX must match the VT and RAMP
data at the same process point.  The other groups may be chosen
independently.

You're right, to get the fastest you need MAX VI/VT/Ramp, MIN Pkg, and Min
C_comp.

Chris Rokusek
Viewlogic Systems

 -----Original Message-----
From: Steve Constable [mailto:[email-masked]]
Sent: Tuesday, February 15, 2000 2:30 PM
To: [email-masked]
Subject: C_comp confusion

  I'm confused about C_comp. All of the data tables in an IBIS file are
ordered as TYP, MIN then MAX.
  But it looks like C_comp is ordered as TYP, MAX then MIN....that's were
the confusion is.
  The reason I think C_comp is ordered differently is that the MAX should
have the smallest capacitance associated with it _not_ the greatest. In the
example below (taken from the 21152_aa.ibs model from Intel), the C_comp has
a max value of 0.50pF, this will slow down the I/O buffer (compared to the
TYP case of 0.40pF), this contradicts what the rest of the model is trying
achieve when the simulator is referring to the MAX columns (i.e. MAXimize
speed).
  Likewise I think the C_comp_min should be 0.50pF NOT what the model
indicates as 0.30pF.
  And the C_comp_max should be 0.30pF NOT 0.50pF as the model indicates.

  Just in case I've not made myself all that clear....below I have added a
line to the original C_comp line:

  |                                   TYP           MIN           MAX

  I've checked with several different models and they all seem to have
C_comp as TYP,MAX,MIN
  Even the IBIS spec has the MAX value as the largest and not the smallest
capacitance...as below:
  Vref = 0                   |Timing specification test load voltage
  | variable      typ             min             max
  C_comp      12.0pF       10.0pF        15.0pF

  If that's the way the spec has it, then I guess everyone will follow the
spec, but I'm still confused as to why the MAX parameter has the largest
capacitance when the objective of using MAX is to get the fastest switching
time possible.....

  Steve Constable
  Tundra Semiconductor