Subject: Series MOSFET model

From: Stephen Nolan <[email-masked]>
Date: Wed, 19 Jul 2000 08:30:22 -0500

IBIS experts, please help with another question. When making an IBIS model of a
FET switch, the IBIS spec calls for the following model:

|               The model is:
|
|                                Table Current
|                                   ------->
|                               +     Vds     -
|                             Pin 1           Pin 2
|                               <---|     |--->  +
|                               d   |_____| - s
|                                    --+-- Vgs   Vs
|                                      | g  +
|                                                -
|
|                       Vg = [Voltage Range] = Vcc
|                       Vgs = Table Voltage = Vtable = Vcc - Vs
|                       Ids = Table Current for a given Vcc and Vds

The table voltage that is reported is Vgs, the voltage difference between pin 2
(in this example) and the gate voltage (usually Vcc). This is an entirely
adequate model for n-FET only series switches, however several FET switch
devices use a full transmission-gate (n-FET in parallel with p-FET). When the
switch is enabled [On] the gate of the n-FET is usually at Vcc and the gate of
the p-FET is usually at ground. 

        GND
         |
         o
       =====
      |     | p-FET
    --|     |--
    |         |
----+-|     |-+----
      |_____| n-FET
       --+--
         |
        Vcc

The question, obviously is "Which Vgs do I report in the table?"

-- 
Regards,
Stephen M. Nolan

---

From: Bob Ross <[email-masked]>
Date: Thu, 20 Jul 2000 17:19:24 -0700

Stephen:

At this time, I would pretend that this is still an n-FET
device and use Vgs based on the "Vcc" node.  However, the
setup and measurements would be for both the n-FET and p-FET
devices in parallel.

Bob Ross
Mentor Graphics

---

From: Stephen Nolan <[email-masked]>
Date: Thu, 20 Jul 2000 22:05:59 -0500

I wonder if this will hold true for all simulators. The currents that you get
will be unsolvable if you assume that it is only an nFET and you are seeing the
pFET in parallel with it. I'd be afraid on nonconvergance, or simulators giving
errors about erroneous currents.

The only alternate solution that I could provide is to use [Series current]
instead of [Series MOSFET].

Thanks, Bob, for answering my questions.
-- 
Regards,
Stephen M. Nolan