Subject: How to determine per length RLC in a board

From: "Yaping Zhou" <[email-masked]>
Date: Tue, 5 Jun 2001 10:16:43 -0500

Hi, All:

If the stackup in a board is a symmetric stripline structure (GND-SIG-PWR),
the characteristic impedance is the same for switching high and low, and the
per length RLC are also the same for both switching cases.

How to determine the per length RLC in a board with a stackup like
SIG-GND-PWR? The characteristic impedance and per length RLC are
switching-dependent, but there is no way to put two values for each trace in
an ebd file.

Intel uses ebd to describe packages used for Pentium processors,I have the
same question there on the way to determine RLC values.

Your help is appreciated.

Thanks,

--
**************************************
Yaping Zhou (r3aadv)
(512) 933-5803
Motorola Semiconductor Products Sector
Final Manufacturing Technology Center
Ed Bluestein, Austin, Texas
**************************************

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From: Alan Hilton-Nickel <[email-masked]>
Date: Tue, 05 Jun 2001 10:26:33 -0700

Yaping,

In the SIG-GND-PWR, the PWR plane is not a return path for the signal
layer. I suggest you model it as SIG-GND (microstrip). The high-speed
currents will always use the GND plane, assuming good decoupling between
PWR and GND.

Alan

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From: Vinu Arumugham <[email-masked]>
Date: Tue, 05 Jun 2001 10:08:37 -0700

Yaping,

In both cases, the characteristic impedance and per length RLC are independent
of switching direction.

Thanks,
Vinu

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From: Scott McMorrow <[email-masked]>
Date: Tue, 05 Jun 2001 11:11:07 -0700

All,

Huh?

"Return path" as it is applied to AC Impedance, is the
instantaneous path that the fields take in traveling between multiple
conductors.

For balanced stripline, PWR-SIG-GND, the fields most absolutely
do propagate between the signal and both the power and ground
planes.  The field equally divides between the two.  As a result,
the high speed currents will use both planes.  Even a floating
conductor will "capture" fields and carry a "return current".
The fields don't know to stop until they reach a metalic object.
This follows from Maxwell's first Law.

The RLC characteristic of a stripline trace (with the same dimensions)
between two ground planes, two power planes, one power and one ground
plane are identical.  They are also identical for floating metal once
the fields are established.

The only difference in all of these configurations is in the "transition
region" to get onto the structure.  Here things get interesting.  However,
IBIS ebd models, and most of the Intel literature do not concern
themselves with modeling these effects, anyway.

regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com

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From: "Yaping Zhou" <[email-masked]>
Date: Tue, 5 Jun 2001 13:00:20 -0500

Alan & Vinu:

Thank your for your reply.

I am actually interested in package modeling, is "good decoupling" usually a
good assumption in high-speed devices with a limited on-chip decoupling
capacitance?

Yaping

----- Original Message -----
From: "Alan Hilton-Nickel" <[email-masked]>
To: "Yaping Zhou (r3aadv)" <[email-masked]>
Cc: <[email-masked]>
Sent: Tuesday, June 05, 2001 12:26 PM
Subject: Re: How to determine per length RLC in a board

Yaping,

Alan

---

From: Alan Hilton-Nickel <[email-masked]>
Date: Tue, 05 Jun 2001 11:31:41 -0700

Scott,

I think you may want to re-read my reply to Yaping. He had the balanced
stripline case covered, although I agree with everything you say. 

My reply was meant to address his *other* stackup, SIG-GND-PWR. In that
case, he SIG layer is NOT between the planes. If the SIG is only
adjacent to the GND, and the PWR is on ther other side of the GND plane
from the SIG, the GND will be the dominant return path for the higher
frequency components, unless poor decoupling prevents the current from
reaching GND. 

Not wanting to argue with Maxwell (I'm under-armed) but I doubt it's
worth trying to figure out the current/frequency component of the return
current in the PWR plane in that case.

Alan

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From: Scott McMorrow <[email-masked]>
Date: Tue, 05 Jun 2001 11:47:19 -0700

Yaping,

Oh ...  packages become much more interesting, because
this is where the return path transitions occur.  An RLC package
model, even a multisectioned one, is based upon loop
inductances, rather than partial inductances.  As a result,
it is only an approximation ... which begins to fail with lots
of simultaneous switching.

The best that one can do is to characterize a package
section, including signals, powers and grounds with some
sort of 3D partial inductance method, and then perform the
appropriate mathematical transformations to develop
IBIS compatable models which use a loop formulation.
What you will end up with, is several different models,
rather then just one, since the problem is not unique and
depends upon the switching directions of the signals
and the power and grounds.

regards,

scott

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From: Vinu Arumugham <[email-masked]>
Date: Tue, 05 Jun 2001 13:47:26 -0700

Yaping,

The recommended bump pattern for the SIG-GND-PWR package stackup would be as
follows:

GND bumps distributed uniformly throughout the package.
PWR bumps only at the center (area BGA) or only on the inner periphery
(perimeter BGA).

With the above pattern, since you have only one signal layer, the return
current will always flow on the nearest plane (GND in this case) even when
there is no decoupling capacitance on the chip/package between PWR and GND.

If the PWR bumps are distributed over the entire package, it gets complicated.
PWR-GND decoupling on the package may be important (depends on the
stack-up/routing/decoupling on the board on which the BGA is mounted). In any
case, the impedance will be independent of the signal transition direction.

Thanks,
Vinu