Subject: RE: How to determine per length RLC in a board

From: "Mellitz, Richard" <[email-masked]>
Date: Wed, 6 Jun 2001 04:59:43 -0700

Vinu,

PWG and GND bumps distributed within the signal bumps pattern minimizes the
non TEM discontinuity impact of the return structure of a GND-SIG-PWR board
stackup. Doesn't this sound good in theory? :-) You need to return the
current induced on all planes. One of those energy things 'ya know. Any
thing that is non TEM can be models with a lumped mesh. What you find out
when you do this is that you must add more on die PWR decoupling if the PWR
bumps are in the center of the BGA. This is especially true if IO PWR is not
the same as CORE power. 'Gotta keep core happy too, but that's another
story.  Of course you may be talking about a wire bond package... which has
another set of challenges. :-( In short, there is no general best way. There
are always trade offs. The challenge is to put good analysis data behind the
decision.

One simple approach is to model TEM structures with transmission lines and
non TEM with PEEC meshes and hope you can figure out how to ground the whole
mess so you don't have convergence problems. Then you can simplify and guard
band the bounding cases in ground referenced black boxed equivalent circuit
TEM simulation and be kind to your customers. ... enter stage right... IBIS.
It doesn't always work, but that's the challenge. :-)

... Rich

-----Original Message-----
From: Vinu Arumugham [mailto:[email-masked]]
Sent: Tuesday, June 05, 2001 4:47 PM
To: Yaping Zhou
Cc: Alan Hilton-Nickel; [email-masked]
Subject: Re: How to determine per length RLC in a board

Yaping,

The recommended bump pattern for the SIG-GND-PWR package stackup would be as
follows:

GND bumps distributed uniformly throughout the package.
PWR bumps only at the center (area BGA) or only on the inner periphery
(perimeter BGA).

With the above pattern, since you have only one signal layer, the return
current will always flow on the nearest plane (GND in this case) even when
there is no decoupling capacitance on the chip/package between PWR and GND.

If the PWR bumps are distributed over the entire package, it gets
complicated.
PWR-GND decoupling on the package may be important (depends on the
stack-up/routing/decoupling on the board on which the BGA is mounted). In
any
case, the impedance will be independent of the signal transition direction.

Thanks,
Vinu

Yaping Zhou wrote:

> Alan & Vinu:
>
> Thank your for your reply.
>
> I am actually interested in package modeling, is "good decoupling" usually
a
> good assumption in high-speed devices with a limited on-chip decoupling
> capacitance?
>
> Yaping
>
> ----- Original Message -----
> From: "Alan Hilton-Nickel" <[email-masked]>
> To: "Yaping Zhou (r3aadv)" <[email-masked]>
> Cc: <[email-masked]>
> Sent: Tuesday, June 05, 2001 12:26 PM
> Subject: Re: How to determine per length RLC in a board
>
> Yaping,
>
> In the SIG-GND-PWR, the PWR plane is not a return path for the signal
> layer. I suggest you model it as SIG-GND (microstrip). The high-speed
> currents will always use the GND plane, assuming good decoupling between
> PWR and GND.
>
> Alan
>
> Yaping Zhou wrote:
> >
> > Hi, All:
> >
> > If the stackup in a board is a symmetric stripline structure
> (GND-SIG-PWR),
> > the characteristic impedance is the same for switching high and low, and
> the
> > per length RLC are also the same for both switching cases.
> >
> > How to determine the per length RLC in a board with a stackup like
> > SIG-GND-PWR? The characteristic impedance and per length RLC are
> > switching-dependent, but there is no way to put two values for each
trace
> in
> > an ebd file.
> >
> > Intel uses ebd to describe packages used for Pentium processors,I have
the
> > same question there on the way to determine RLC values.
> >
> > Your help is appreciated.
> >
> > Thanks,
> >
> > --
> > **************************************
> > Yaping Zhou (r3aadv)
> > (512) 933-5803
> > Motorola Semiconductor Products Sector
> > Final Manufacturing Technology Center
> > Ed Bluestein, Austin, Texas
> > **************************************

---

From: Vinu Arumugham <[email-masked]>
Date: Wed, 06 Jun 2001 11:26:24 -0700

Rich,

I am assuming a SIG-GND-PWR package stack-up and a board stack-up that may be 4
to say 20 layers (not GND-SIG-PWR). Boards usually have one to several ground
planes and a few power planes. With the number of different power supply
voltages on current boards, power planes tend to be split up into islands or
are implemented as shapes on surface layers. Hence power structures tend to be
poor references for signals and most routing is referenced to ground. Even if
signals were referenced to power planes, the plane voltage may not be the same
as PWR on the package. My bump pattern recommendation was based on the above.

Thanks,
Vinu

---

From: Hailong Wang <[email-masked]>
Date: Thu, 07 Jun 2001 10:53:43 +0800

Hi,
    In Page 73 - Page 75 of the IBIS Specification Ver3.2, there are the following
lines:

[Path Description] CAS_2
Pin J25
Len = 0.5 L=8.35n C=3.34p R=0.01 /
Node u21.15
Len = 0.5 L=8.35n C=3.34p R=0.01 /
Node u22.15
Len = 0.5 L=8.35n C=3.34p R=0.01 /
Node u23.15

....

[Reference Designator Map]
|
| External Part References:
|
| Ref Des File name Component name
u23 pp100.ibs Pentium(R)__Pro_Processor
u24 simm.ebd 16Meg X 36 SIMM Module
u25 ls244.ibs National 74LS244a
u26 r10K.ibs My_10K_Pullup

I want to know which node of buffer in pp100.ibs(node of B element) pin u23.15
connects to.

Your help is appreciated very much.

--
Best Regards.
Hai-long Wang
Tel:021-62837026x228
Avant! Shanghai R&D Center,  16th Floor, SunTong InfoPort Plaza
No.55, West Huaihai Road, Shanghai, 200030, P.R.China