Subject: RE: LVDS models and s2ibis2

From: "Hegazy, Hazem" <[email-masked]>
Date: Sun, 27 May 2001 10:59:43 +0300

Hi,

As The presentation shows, we classify LVDS buffer into two categories:

	- Without internal termination: (If we are lucky)
		- This one I consider it just a normal differential buffer.
No special setting for it, just the normal differential buffers  settings.

	- With internal termination: (The usual received sub circuit) 
		- If the internal termination (the resistance shunted
between the +ve & -ve PADS) has a discrete value (and a linear one) then you
can use the approach of decomposing the resistance behavior as shown in
Munich summit meeting presentation.

		- If the termination is not linear or you can't specify its
value then you can use the variable resistance approach in the presentation
you already have.

Regarding your questions:

>>>> 1.  If differential inputs or outputs
	switch between 1.1 and 1.3 volts, what
	range of voltages do you use for the I/V
	curves?  

The IBIS standard recommends the I-V curves extraction from -VDD to 2*VDD
But if you have difficulties in that you can sweep in the active region only
(from 0 to VDD) in this case you should expect bad validation out of the DC
range (if you have some high reflection above/under VDD/zero respectively).

>>>> 2.  What load do you use on differential
outputs to generate the V/T curves? (What
are Rfix, Rref, Vref, ... and how are these
plus the  terminating resistor connected?)
By the way, this has to be done in a way 
that HPSICE converges.

The loads are normally 50 Ohm to the reference voltage. Apparently the
reference voltage in your case is 1.2 volt as the wave form swings between
1.1 & 1.3 (i.e. around 1.2) .
Rfix is the load you but while extracting the V-T tables, Rref&Vref are the
value of the timing test loads stated in the data sheets of that buffer.

BR,

Hazem Hegazy
Development Engineer

Tel: (20 2) 4135458
Fax: (20 2) 4186945
Mobile: (+20)  105129341
Email: [email-masked]

-----Original Message-----
From: Greg Haynes [mailto:[email-masked]]
Sent: Saturday, May 26, 2001 1:23 AM
To: [email-masked]
Subject: LVDS models and s2ibis2

I'm trying to create IBIS models for some
parts that we make using s2ibis2, and for
single-output buffers it works pretty well.
LVDS buffers are another story. In some
cases I've had a little success, but I
don't know if s2ibis2 is even supposed to
be capable of creating the required SPICE
decks for simulating LVDS buffers.

From a previous post I was referred to
a presentation on LVDS modeling by
Hegazy and Korany, but it's just foils
with no detailed explanations.

Among my questions:

1.  If differential inputs or outputs
switch between 1.1 and 1.3 volts, what
range of voltages do you use for the I/V
curves? 
2.  What load do you use on differential
outputs to generate the V/T curves? (What
are Rfix, Rref, Vref, ... and how are these
plus the  terminating resistor connected?)
By the way, this has to be done in a way 
that HPSICE converges.

-- 
Greg Haynes		  [email-masked]
Aeroflex UTMC Microelectronic Systems
4350 Centennial Blvd           phone: 719 594-8197
Colorado Springs, CO 80907       fax: 719 594-5541

---

From: Hailong Wang <[email-masked]>
Date: Mon, 28 May 2001 14:14:08 +0800

Hi,
    I am a developer of IBIS Model in HSpice Group of Avanti
Corporation. Now I want to improve the line and function coverage of my
code,  so I need some testcases(some .ibs files) including .ebd and .pkg
files. If you have some, please send me some cases of contact with me.
   Thanks in advance.

--
Best Regards.
Hai-long Wang
Tel:021-62837026x228
Avant! Shanghai R&D Center,  16th Floor, SunTong InfoPort Plaza
No.55, West Huaihai Road, Shanghai, 200030, P.R.China

---

From: Zhiping Yang <[email-masked]>
Date: Wed, 30 May 2001 10:14:19 -0700

Hi,

Could you please specify the titles of the presentation you mentioned?
Where can I get them? Thanks.

Zhiping

"Hegazy, Hazem" wrote:

>                - This one I consider it just a normal differential
> buffer. No special setting for it, just the normal differential
> buffers  settings.
>
> between the +ve & -ve PADS) has a discrete value (and a linear one)
> then you can use the approach of decomposing the resistance behavior
> as shown in Munich summit meeting presentation.
>
>                - If the termination is not linear or you can't specify
> its value then you can use the variable resistance approach in the
> presentation you already have.
>
> The IBIS standard recommends the I-V curves extraction from -VDD to
> 2*VDD But if you have difficulties in that you can sweep in the active
> region only (from 0 to VDD) in this case you should expect bad
> validation out of the DC range (if you have some high reflection
> above/under VDD/zero respectively).
>
> reference voltage in your case is 1.2 volt as the wave form swings
> between 1.1 & 1.3 (i.e. around 1.2) .
>
> Rfix is the load you but while extracting the V-T tables, Rref&Vref
> are the value of the timing test loads stated in the data sheets of
> that buffer.
>
> BR,
>
> Hazem Hegazy
> Development Engineer
>
> Tel: (20 2) 4135458
> Fax: (20 2) 4186945
> Mobile: (+20)  105129341

--
   Zhiping Yang, Ph. D.
   Hardware Engineer
   Cisco Systems
   270 West Tasman Drive
   Mail Stop:SJCG/2/2
   San Jose, CA 95134             |          |
   email: [email-masked]      :|:        :|:
   Tel  : 408 525 5690          :|||:      :|||:
   Fax  : 408 526 5504       .:|||||||:..:|||||||:.
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