Subject: Clarification needed.

From: [email-masked]
Date: Thu, 24 May 2001 12:18:13 +0530

Hello Users,

        I am using XTK to simulate a PCBA. The board has a 100pin ASIC.  In
order to model the ASIC properly I need the IBIS model of the ASIC which I
can convert it to XTK format. Now if I directly request for an IBIS model
the vendor may hesistate. So I am requesting the following data from the
vendor with which I can create a IBIS model. Below is the data I am
requesting them. Is it OK. Does it cover everything necessary to create a
proper IBIS model?. The ASIC does not have any clamp diodes. Please reply.
The following data whichever is applicable for each pin of the ASIC are
needed
 1. Package parasitics namely, the Resistance, capacitance and Inductance.
Typical, max, min values required.

2. Die capacitance as seen at the die pad. Typical, max, min values
required

3. Output impedance of the I/O buffers. Typical, max, min values required.

4. Rise time and fall time values (dv/dt typical, max, min) of buffers
excluding the effect of packaging but including the effect of die
capacitance. Load conditions required.

6. Rising edge and falling edge waveforms (Voltage vs. time curve with the
voltage values having typical, max, min values) of the driver along with
the test conditions.

5. V/I characteristics of Pull up and Pull down resistor, if present, when
the buffer is driven high and low respectively. The voltage sweep must be
from ?3.3V to +6.6V. Current measurement with typical, max, min values are
required.

Thanks,

Anbazhagan.

---

From: [email-masked]
Date: Thu, 24 May 2001 09:15:38 -0400

Anbazhagan,

Sounds good to me...  I haven't modeled a ASIC but you seem to be on the
right track.

Regarding point 3.  I'm not sure how the output impedance of the I/O buffer
can be included in a IBIS datasheet so this is probably not necessary.
Others with more experience may correct me on this.

Regarding point 5.  the DC sweep for I/V data is -Vcc to 2Vcc, so in your
case this seems to be -3.3V to 6.6V.  Do not forget that Pullup data has a
domain of  Vtable=Vcc - Vin, where Vin is the DC voltage sweep.

For a I/O buffer here are the parameters and data you will want to form a
IBIS model, you have already described most of these:

     Polarity
     Vref, Rref, Cref
     Ccomp
     Temperature Range
     Voltage Range
     Pulldown Data
     Pullup Data
     Rising and Falling Waveforms across the Voltage Range, one set at 50
Ohms to gnd, another set at 50 Ohms to Vcc  ( assuming the ASIC is CMOS )
     Ramp Data

     additionally you will want the R L C packaging parameters either pin
specific or general typ, min, max values
     you would also want the I/V curves for the Power and GND Clamps but
you have stated that these do not exist

Refer to the 3.2 spec for definitions and descriptions of the above data
and parameters.

One other point, when requesting this data be sure to mention you want no
more than 100 points per data curve.

Hope this is of some help.

Adam Tambone

[email-masked] on 05/24/2001 02:48:13 AM

To:   "[email-masked]":@server.eda.org
cc:

Subject:  Clarification needed.

Hello Users,

Thanks,

Anbazhagan.

---

From: "ruston, matt" <[email-masked]>
Date: Thu, 24 May 2001 09:26:19 -0400

Adam, Anbazhagan:

 Hi. The output impedance of an I/O buffer is contained directly in the I/V
curves of the pullup and pulldown. Add to this the package parasitics and
you should have the impedance of the I/O buffer looking back through the
package.

Regards,

Matt

-----Original Message-----
From: [email-masked]
[mailto:[email-masked]]
Sent: Thursday, May 24, 2001 9:16 AM
To: [email-masked]; [email-masked]
Subject: Re: Clarification needed.

Anbazhagan,

     Polarity
     Vref, Rref, Cref
     Ccomp
     Temperature Range
     Voltage Range
     Pulldown Data
     Pullup Data

Adam Tambone

Hello Users,

Thanks,

Anbazhagan.

---

From: [email-masked]
Date: Thu, 24 May 2001 09:32:47 -0400

Matt, yes and thank you, in fact when I created a Mathematica based IBIS to
HSPICE translator I modeled the pullup, pulldown, GND and Power clamp
structures as voltage controlled resistors based on the I/V data.

Adam

"ruston, matt" <[email-masked]> on 05/24/2001 09:26:19 AM

To:   Adam Tambone/SouthPortland/Fairchild@Fairchild, [email-masked],
      [email-masked]
cc:

Subject:  RE: Clarification needed.

Adam, Anbazhagan:

Regards,

Matt

-----Original Message-----

Anbazhagan,

     Polarity
     Vref, Rref, Cref
     Ccomp
     Temperature Range
     Voltage Range
     Pulldown Data
     Pullup Data

Adam Tambone

Hello Users,

Thanks,

Anbazhagan.

---

From: [email-masked]
Date: Thu, 24 May 2001 09:36:19 -0400

Adam

Adam, Anbazhagan:

Regards,

Matt

-----Original Message-----

Anbazhagan,

     Polarity
     Vref, Rref, Cref
     Ccomp
     Temperature Range
     Voltage Range
     Pulldown Data
     Pullup Data

Adam Tambone

Hello Users,

Thanks,

Anbazhagan.

---

From: "Gregory R Edlund" <[email-masked]>
Date: Thu, 24 May 2001 07:53:03 -0500

Anbazhagan,

Looks like you're on the right track.  I would recommend your ASIC vendor
read the "IBIS Cookbook," which can be found on the IBIS web page:
http://www.eigroup.org/ibis/tools.htm

As part of the "I/O Buffer Accuracy Handbook" (also available on the IBIS
web page), we published a checklist that should help you.  This list was
compiled from suggestions by members of the SI community who have
experience with IBIS.  I am attaching the most recent version of this list.

Bob, Could you please post this list as an ASCII text file under Accuracy?
Pleas name it "checklist.txt."  Thanks.

IBIS Datasheet Checklist                                  version 1.1,
05/07/01
------------------------

IBIS datasheet:
Component manufacturer:
Component part number:
Engineer verifying this component:
Email address:
Behavioral simulator and version:
Date:

Note:   If answer is N or N/A, provide explanation.
        The user may verify items 1-9 but is unable to verify items 10-20
        because the data involved are only available to the semiconductor
        vendor.

___  1. Does the IBIS datasheet pass the IBIS syntax checker?
        (Note: Some models generate warnings for non-monotonicities that
are
        actually part of the characteristics of the device. Other non-
        monotonicities are so small as to be irrelevant.)

___  2. Is an "I/O Buffer Accuracy Report" available for this component?
        (http://www.vhdl.org/pub/ibis/accuracy)

___  3. Has the modeling engineer performed a visual inspection of IV and
VT
        curves to screen for non-monotonicity, discontinuities, and other
        obvious errors?

___  4. Has the modeling engineer tested the IBIS datasheet using a
behavioral
        simulator?

___  5. Do MIN and MAX data exist for all keywords and sub-parameters?

___  6. Does the IBIS datasheet include all four 50 Ohm VT tables as
described
        in the IBIS Cookbook?

___  7. Do the keywords Cref, Rref, Vref, and Vmeas match the values
specified
        in the component datasheet for all output and bidirectional models?

___  8. Does the output reach Vmeas under standard load conditions for
rising
        and falling waveforms?

___  9. Does the pin table match the component datasheet?

___ 10. Do the keywords Vihl and Vinh represent the unity gain points
derived
        from the dc transfer characteristics for all inputs?

___ 11. Has the modeling engineer verified the accuracy of the C_comp
        subparameter?

___ 12. Has the modeling engineer verified the accuracy of the R_pkg,
L_pkg,
        and C_pkg subparameters?

___ 13. For CMOS logic, do all MAX data represent maximum voltage, minimum
        temperature, and fast process?

___ 14. For CMOS logic, do all MIN data represent minimum voltage, maximum
        temperature, and slow process?

___ 15. For bipolar logic, do all MAX data represent maximum voltage,
maximum
        temperature, and fast process?

___ 16. For bipolar logic, do all MIN data represent minimum voltage,
minimum
        temperature, and slow process?

___ 17. Do the keywords dV/dt_r and dV/dt_f contain the correct 20%-80%
edge
        rate data measured using a 50 & load as specified in IBIS?

___ 18. If the I/O buffer employs dynamic clamping, does the IBIS datasheet
        contain the appropriate keywords and subparameters?

___ 19. If the I/O buffer employs a multi-stage driver, does the IBIS
datasheet
        contain the appropriate keywords and subparameters?

___ 20. If the I/O buffer design employs dynamic edge rate control, dynamic
        impedance control, or any form of feedback, has the modeling
engineer
        assessed the impact of this circuitry on behavioral model accuracy?

Greg Edlund
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
[email-masked]

[email-masked] on 05/24/2001 01:48:13 AM

To:   "[email-masked]":
cc:
Subject:  Clarification needed.

Hello Users,

Thanks,

Anbazhagan.