Subject: Zt question

From: "Jeff Mills" <[email-masked]>
Date: Fri, 25 May 2001 08:10:48 -0000

I guess I feel a little new at this as most of my questions are probably off the wall to anyone whos done much practice with the design tool methodology and mostly I have measurement characterisation background at high speed bus and a bit of rusty theory.

Im uncomfortable with the 50 ohm spec that is always thrown around. Are all lines desinged to this typically unless with heavy drivers (I understand some of hte IO cells on arrays are programmable of can be selected as high or low drivers - tuned to different Zt load speed mix). Does I bis and desing tools just consider this as a spec reference point or is the assumtion all these lines will run as 50 ohm nominal lines.

I read some tables in High performance Printed Circuit Boards  (pretty cool: ISBN 0-07-026713-8) which for the lower relatvie permeability and smaller line space that a typical desing may provide in computer hihg speed bus ( consider maybe 6 mil track, 6 mil space on 1 oz copper - its yieldable with practice), suggest a higher Zt.

Also consider actual functional implementable boards at the higher bus speeds (low hundreds per standard architectures. Looking at the waveform at driver relative to reciver on a bidirectional almost never run right at TEM waveshape. Do modeling consider termination loading at end of line (at input) as desireable and this is characteristic impedance at frequency, not just the Rterm? I think you have to figure the resultant of the complex load vector and figure the imaginay term as well as it winds up not very negligible for things Ive seen.

Isnt a better way of verification of properties by startign wiht chip vendor specs, modeling it, and then see where the desing is at in characterisation and then adjust the measured back to the simulation, I dont think many of these come right out on the intial models without iterating a few times unless process scale factors have already been determined. Its just  a model that assumes many things. Whats great in characterization method is one can determine much of the actual Zo Co and Ls, as well as Zl, reflection td as flight td and coorelate this to the design model rather than relying on ibis generated to a standard method but ignoring what the board will see. With model difficiencies I dont hear how this gap is being filled yet. $20k Scope or $40k software simulator - flip a coin.

Jeff

>From: "Gregory R Edlund"

>To: [email-masked]

>CC: [email-masked]

>Subject: Re: Clarification needed.

>Date: Thu, 24 May 2001 07:53:03 -0500

>Anbazhagan,

>Looks like you're on the right track. I would recommend your ASIC vendor

>read the "IBIS Cookbook," which can be found on the IBIS web page:

>http://www.eigroup.org/ibis/tools.htm

>As part of the "I/O Buffer Accuracy Handbook" (also available on the IBIS

>web page), we published a checklist that should help you. This list was

>compiled from suggestions by members of the SI community who have

>experience with IBIS. I am attaching the most recent version of this list.

>Bob, Could you please post this list as an ASCII text file under Accuracy?

>Pleas name it "checklist.txt." Thanks.

>IBIS Datasheet Checklist version 1.1,

>05/07/01

>------------------------

>IBIS datasheet:

>Component manufacturer:

>Component part number:

>Engineer verifying this component:

>Email address:

>Behavioral simulator and version:

>Date:

>Note: If answer is N or N/A, provide explanation.

> The user may verify items 1-9 but is unable to verify items 10-20

> because the data involved are only available to the semiconductor

> vendor.

>___ 1. Does the IBIS datasheet pass the IBIS syntax checker?

> (Note: Some models generate warnings for non-monotonicities that

>are

> actually part of the characteristics of the device. Other non-

> monotonicities are so small as to be irrelevant.)

>___ 2. Is an "I/O Buffer Accuracy Report" available for this component?

> (http://www.vhdl.org/pub/ibis/accuracy)

>___ 3. Has the modeling engineer performed a visual inspection of IV and

>VT

> curves to screen for non-monotonicity, discontinuities, and other

> obvious errors?

>___ 4. Has the modeling engineer tested the IBIS datasheet using a

>behavioral

> simulator?

>___ 5. Do MIN and MAX data exist for all keywords and sub-parameters?

>___ 6. Does the IBIS datasheet include all four 50 Ohm VT tables as

>described

> in the IBIS Cookbook?

>___ 7. Do the keywords Cref, Rref, Vref, and Vmeas match the values

>specified

> in the component datasheet for all output and bidirectional models?

>___ 8. Does the output reach Vmeas under standard load conditions for

>rising

> and falling waveforms?

>___ 9. Does the pin table match the component datasheet?

>___ 10. Do the keywords Vihl and Vinh represent the unity gain points

>derived

> from the dc transfer characteristics for all inputs?

>___ 11. Has the modeling engineer verified the accuracy of the C_comp

> subparameter?

>___ 12. Has the modeling engineer verified the accuracy of the R_pkg,

>L_pkg,

> and C_pkg subparameters?

>___ 13. For CMOS logic, do all MAX data represent maximum voltage, minimum

> temperature, and fast process?

>___ 14. For CMOS logic, do all MIN data represent minimum voltage, maximum

> temperature, and slow process?

>___ 15. For bipolar logic, do all MAX data represent maximum voltage,

>maximum

> temperature, and fast process?

>___ 16. For bipolar logic, do all MIN data represent minimum voltage,

>minimum

> temperature, and slow process?

>___ 17. Do the keywords dV/dt_r and dV/dt_f contain the correct 20%-80%

>edge

> rate data measured using a 50 & load as specified in IBIS?

>___ 18. If the I/O buffer employs dynamic clamping, does the IBIS datasheet

> contain the appropriate keywords and subparameters?

>___ 19. If the I/O buffer employs a multi-stage driver, does the IBIS

>datasheet

> contain the appropriate keywords and subparameters?

>___ 20. If the I/O buffer design employs dynamic edge rate control, dynamic

> impedance control, or any form of feedback, has the modeling

>engineer

> assessed the impact of this circuitry on behavioral model accuracy?

>Greg Edlund

>Electrical Packaging

>IBM Server Technology Development

>3605 Hwy. 52 N, Dept. HDC

>Rochester, MN 55901

>[email-masked]

>[email-masked] on 05/24/2001 01:48:13 AM

>To: "[email-masked]":

>cc:

>Subject: Clarification needed.

>Hello Users,

> I am using XTK to simulate a PCBA. The board has a 100pin ASIC. In

>order to model the ASIC properly I need the IBIS model of the ASIC which I

>can convert it to XTK format. Now if I directly request for an IBIS model

>the vendor may hesistate. So I am requesting the following data from the

>vendor with which I can create a IBIS model. Below is the data I am

>requesting them. Is it OK. Does it cover everything necessary to create a

>proper IBIS model?. The ASIC does not have any clamp diodes. Please reply.

>The following data whichever is applicable for each pin of the ASIC are

>needed

> 1. Package parasitics namely, the Resistance, capacitance and Inductance.

>Typical, max, min values required.

>2. Die capacitance as seen at the die pad. Typical, max, min values

>required

>3. Output impedance of the I/O buffers. Typical, max, min values required.

>4. Rise time and fall time values (dv/dt typical, max, min) of buffers

>excluding the effect of packaging but including the effect of die

>capacitance. Load conditions required.

>6. Rising edge and falling edge waveforms (Voltage vs. time curve with the

>voltage values having typical, max, min values) of the driver along with

>the test conditions.

>5. V/I characteristics of Pull up and Pull down resistor, if present, when

>the buffer is driven high and low respectively. The voltage sweep must be

>from ?3.3V to +6.6V. Current measurement with typical, max, min values are

>required.

>Thanks,

>Anbazhagan.

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